int main(int argc, char **argv) {
EncoderTestRequestProxy *device = new EncoderTestRequestProxy(IfcNames_EncoderTestRequestS2H);
EncoderTestIndication deviceIndication(IfcNames_EncoderTestIndicationH2S);
MemServerRequestProxy *hostMemServerRequest = new MemServerRequestProxy(IfcNames_MemServerRequestS2H);
MMURequestProxy *dmap = new MMURequestProxy(IfcNames_MMURequestS2H);
DmaManager *dma = new DmaManager(dmap);
MemServerIndication hostMemServerIndication(hostMemServerRequest, IfcNames_MemServerIndicationH2S);
MMUIndication hostMMUIndication(dma, IfcNames_MMUIndicationH2S);
const std::string path="../../data/xgmii.data";
std::ifstream traceinfo(path.c_str());
std::string line;
int srcAlloc;
srcAlloc = portalAlloc(alloc_sz, 0);
unsigned long int *srcBuffer = (unsigned long int *)portalMmap(srcAlloc, alloc_sz);
for (int i = 0; i < numWords; /*NONE*/ ) {
std::getline(traceinfo, line);
std::istringstream iss(line);
std::string first_64;
iss >> first_64;
std::string second_64;
iss >> second_64;
srcBuffer[i++] = strtoul(second_64.c_str(), NULL, 16); /*second_64 is LSB*/
srcBuffer[i++] = strtoul(first_64.c_str(), NULL, 16);
}
portalCacheFlush(srcAlloc, srcBuffer, alloc_sz, 1);
unsigned int ref_srcAlloc = dma->reference(srcAlloc);
printf( "Main::starting read %08x\n", numWords);
device->startEncoder(ref_srcAlloc, numWords, burstLen, 1);
sem_wait(&test_sem);
return 0;
}
int main(int argc, const char **argv)
{
int mismatch = 0;
uint32_t sg = 0;
int max_error = 10;
if (sem_init(&test_sem, 1, 0)) {
fprintf(stderr, "error: failed to init test_sem\n");
exit(1);
}
fprintf(stderr, "testmemwrite: start %s %s\n", __DATE__, __TIME__);
DmaManager *dma = platformInit();
MemwriteRequestProxy *device = new MemwriteRequestProxy(IfcNames_MemwriteRequestS2H);
MemwriteIndication deviceIndication(IfcNames_MemwriteIndicationH2S);
fprintf(stderr, "main::allocating memory...\n");
int dstAlloc = portalAlloc(alloc_sz, 0);
unsigned int *dstBuffer = (unsigned int *)portalMmap(dstAlloc, alloc_sz);
#ifdef FPGA0_CLOCK_FREQ
long req_freq = FPGA0_CLOCK_FREQ, freq = 0;
setClockFrequency(0, req_freq, &freq);
fprintf(stderr, "Requested FCLK[0]=%ld actually %ld\n", req_freq, freq);
#endif
unsigned int ref_dstAlloc = dma->reference(dstAlloc);
for (int i = 0; i < numWords; i++)
dstBuffer[i] = 0xDEADBEEF;
portalCacheFlush(dstAlloc, dstBuffer, alloc_sz, 1);
fprintf(stderr, "testmemwrite: flush and invalidate complete\n");
fprintf(stderr, "testmemwrite: starting write %08x\n", numWords);
portalTimerStart(0);
device->startWrite(ref_dstAlloc, 0, numWords, burstLen, iterCnt);
sem_wait(&test_sem);
for (int i = 0; i < numWords; i++) {
if (dstBuffer[i] != sg) {
mismatch++;
if (max_error-- > 0)
fprintf(stderr, "testmemwrite: [%d] actual %08x expected %08x\n", i, dstBuffer[i], sg);
}
sg++;
}
platformStatistics();
fprintf(stderr, "testmemwrite: mismatch count %d.\n", mismatch);
exit(mismatch);
}
int main(int argc, const char **argv)
{
ReadTestRequestProxy *device = new ReadTestRequestProxy(IfcNames_ReadTestRequestS2H);
ReadTestIndication deviceIndication(IfcNames_ReadTestIndicationH2S);
DmaManager *dma = platformInit();
int srcAlloc;
srcAlloc = portalAlloc(test_sz, 0);
unsigned int *srcBuffer = (unsigned int *)portalMmap(srcAlloc, test_sz);
for (unsigned int i = 0; i < test_sz/sizeof(unsigned int); i++)
srcBuffer[i] = i;
portalCacheFlush(srcAlloc, srcBuffer, test_sz, 1);
unsigned int ref_srcAlloc = dma->reference(srcAlloc);
printf( "Main::starting read %lx\n", test_sz);
device->startRead(ref_srcAlloc, test_sz, burstLen, 1);
sem_wait(&test_sem);
return 0;
}
int main(int argc, const char **argv)
{
size_t alloc_sz = 1024*1024;
MemwriteRequestProxy *device = new MemwriteRequestProxy(IfcNames_MemwriteRequestS2H);
MemwriteIndication deviceIndication(IfcNames_MemwriteIndicationH2S);
DmaManager *dma = platformInit();
sem_init(&done_sem, 1, 0);
int dstAlloc = portalAlloc(alloc_sz, 0);
unsigned int *dstBuffer = (unsigned int *)portalMmap(dstAlloc, alloc_sz);
for (unsigned int i = 0; i < alloc_sz/sizeof(uint32_t); i++)
dstBuffer[i] = 0xDEADBEEF;
portalCacheFlush(dstAlloc, dstBuffer, alloc_sz, 1);
fprintf(stderr, "parent::starting write\n");
unsigned int ref_dstAlloc = dma->reference(dstAlloc);
device->startWrite(ref_dstAlloc, alloc_sz, 2 * sizeof(uint32_t));
sem_wait(&done_sem);
memdump((unsigned char *)dstBuffer, 32, "MEM");
fprintf(stderr, "%s: done\n", __FUNCTION__);
}
int runtest(int argc, const char ** argv)
{
int test_result = 0;
int srcAlloc;
unsigned int *srcBuffer = 0;
fprintf(stderr, "Main::%s %s\n", __DATE__, __TIME__);
MemreadRequestProxy *device = new MemreadRequestProxy(IfcNames_MemreadRequestS2H);
MemreadIndication deviceIndication(IfcNames_MemreadIndicationH2S);
DmaManager *dma = platformInit();
fprintf(stderr, "Main::allocating memory...\n");
srcAlloc = portalAlloc(alloc_sz, 0);
srcBuffer = (unsigned int *)portalMmap(srcAlloc, alloc_sz);
#ifdef FPGA0_CLOCK_FREQ
long req_freq = FPGA0_CLOCK_FREQ;
long freq = 0;
setClockFrequency(0, req_freq, &freq);
fprintf(stderr, "Requested FCLK[0]=%ld actually %ld\n", req_freq, freq);
#endif
for (int i = 0; i < numWords; i++){
srcBuffer[i] = i;
}
portalCacheFlush(srcAlloc, srcBuffer, alloc_sz, 1);
fprintf(stderr, "Main::flush and invalidate complete\n");
unsigned int ref_srcAlloc = dma->reference(srcAlloc);
fprintf(stderr, "ref_srcAlloc=%d\n", ref_srcAlloc);
if(true) {
fprintf(stderr, "Main::test read %08x\n", numWords);
// first attempt should get the right answer
device->startRead(ref_srcAlloc, 0, numWords, burstLen);
sem_wait(&test_sem);
if (mismatchCount) {
fprintf(stderr, "Main::first test failed to match %d.\n", mismatchCount);
test_result++; // failed
}
}
int err = 5;
switch (err){
case 0:
{
fprintf(stderr, "Main: attempt to use a de-referenced sglist\n");
dma->dereference(ref_srcAlloc);
device->startRead(ref_srcAlloc, 0, numWords, burstLen);
break;
}
case 1:
{
fprintf(stderr, "Main: attempt to use an out-of-range sglist\n");
device->startRead(ref_srcAlloc+32, 0, numWords, burstLen);
break;
}
case 2:
{
fprintf(stderr, "Main: attempt to use an invalid sglist\n");
device->startRead(ref_srcAlloc+1, 0, numWords, burstLen);
break;
}
case 3:
{
fprintf(stderr, "Main: attempt to use an invalid mmusel\n");
device->startRead(ref_srcAlloc | (1<<16), 0, numWords, burstLen);
break;
}
case 4:
{
fprintf(stderr, "Main: attempt to read off the end of the region\n");
device->startRead(ref_srcAlloc, numWords<<2, burstLen, burstLen);
break;
}
default:
{
device->startRead(ref_srcAlloc, 0, numWords, burstLen);
}
}
sem_wait(&test_sem);
if (mismatchCount) {
fprintf(stderr, "Main::first test failed to match %d.\n", mismatchCount);
test_result++; // failed
}
return test_result;
}
int main(int argc, const char **argv)
{
testPassed=true;
fprintf(stderr, "Initializing Connectal & DMA...\n");
device = new FlashRequestProxy(IfcNames_FlashRequestS2H);
FlashIndication deviceIndication(IfcNames_FlashIndicationH2S);
DmaManager *dma = platformInit();
fprintf(stderr, "Main::allocating memory...\n");
// Memory for DMA
srcAlloc = portalAlloc(srcAlloc_sz, 0);
dstAlloc = portalAlloc(dstAlloc_sz, 0);
srcBuffer = (unsigned int *)portalMmap(srcAlloc, srcAlloc_sz); // Host->Flash Write
dstBuffer = (unsigned int *)portalMmap(dstAlloc, dstAlloc_sz); // Flash->Host Read
// Memory for FTL
blkmapAlloc = portalAlloc(blkmapAlloc_sz * 2, 0);
char *ftlPtr = (char*)portalMmap(blkmapAlloc, blkmapAlloc_sz * 2);
blkmap = (uint16_t(*)[NUM_LOGBLKS]) (ftlPtr); // blkmap[Seg#][LogBlk#]
blkmgr = (uint16_t(*)[NUM_CHIPS][NUM_BLOCKS]) (ftlPtr+blkmapAlloc_sz); // blkmgr[Bus][Chip][Block]
fprintf(stderr, "dstAlloc = %x\n", dstAlloc);
fprintf(stderr, "srcAlloc = %x\n", srcAlloc);
fprintf(stderr, "blkmapAlloc = %x\n", blkmapAlloc);
pthread_mutex_init(&flashReqMutex, NULL);
pthread_cond_init(&flashFreeTagCond, NULL);
printf( "Done initializing hw interfaces\n" ); fflush(stdout);
portalCacheFlush(dstAlloc, dstBuffer, dstAlloc_sz, 1);
portalCacheFlush(srcAlloc, srcBuffer, srcAlloc_sz, 1);
portalCacheFlush(blkmapAlloc, blkmap, blkmapAlloc_sz*2, 1);
ref_dstAlloc = dma->reference(dstAlloc);
ref_srcAlloc = dma->reference(srcAlloc);
ref_blkmapAlloc = dma->reference(blkmapAlloc);
device->setDmaWriteRef(ref_dstAlloc);
device->setDmaReadRef(ref_srcAlloc);
device->setDmaMapRef(ref_blkmapAlloc);
for (int t = 0; t < NUM_TAGS; t++) {
readTagTable[t].busy = false;
writeTagTable[t].busy = false;
eraseTagTable[t].busy = false;
int byteOffset = t * FPAGE_SIZE;
readBuffers[t] = dstBuffer + byteOffset/sizeof(unsigned int);
writeBuffers[t] = srcBuffer + byteOffset/sizeof(unsigned int);
}
for (int lpa=0; lpa < NUM_SEGMENTS*NUM_LOGBLKS*NUM_PAGES_PER_BLK; lpa++) {
flashStatus[lpa] = UNINIT;
}
for (int t = 0; t < NUM_TAGS; t++) {
for ( unsigned int i = 0; i < FPAGE_SIZE/sizeof(unsigned int); i++ ) {
readBuffers[t][i] = 0xDEADBEEF;
writeBuffers[t][i] = 0xBEEFDEAD;
}
}
long actualFrequency=0;
long requestedFrequency=1e9/MainClockPeriod;
int status = setClockFrequency(0, requestedFrequency, &actualFrequency);
fprintf(stderr, "Requested Freq: %5.2f, Actual Freq: %5.2f, status=%d\n"
,(double)requestedFrequency*1.0e-6
,(double)actualFrequency*1.0e-6,status);
printf( "Start!\n" ); fflush(stdout);
device->start(0);
device->setDebugVals(0,0); //flag, delay
device->debugDumpReq(0);
sleep(1);
printf( "Read initial FTL table from table.dump.0\n" ); fflush(stdout);
// Read Initial FTL table
if (readFTLfromFile("table.dump.0", ftlPtr) != 0) {
fprintf(stderr, "Read Failure\n");
return -1;
}
printf( "Done reading table.dump.0\n" ); fflush(stdout);
printf( "MAP Upload to HW!\n" ); fflush(stdout);
device->uploadMap();
timespec start, now;
clock_gettime(CLOCK_REALTIME, & start);
printf( "Test Write!\n" ); fflush(stdout);
for (int logblk = 0; logblk < NUM_LOGBLKS; logblk++){
// test only 1024 segments due to some bad blocks (cannot allocate full 4096 segments)
for (int segnum = 0; segnum < 1024; segnum++) {
// assuming page_ofs = 0
int lpa = (segnum<<14) + logblk;
int freeTag = waitIdleWriteBuffer();
// fill write memory
for (unsigned int w=0; w<FPAGE_SIZE_VALID/sizeof(unsigned int); w++) {
writeBuffers[freeTag][w] = hashAddrToData(lpa, w);
}
writePage(freeTag, lpa);
}
}
while (true) {
usleep(100);
if ( getNumWritesInFlight() == 0 ) break;
}
// read back Map and Save to table.dump.1
device->downloadMap(); // read table from FPGA
if(writeFTLtoFile("table.dump.1", ftlPtr) != 0) {
fprintf(stderr, "Write Failure\n");
return -1;
}
printf( "Test Read!\n" ); fflush(stdout);
for (int logblk = 0; logblk < NUM_LOGBLKS; logblk++){
// test only 1024 segments due to some bad blocks (cannot allocate full 4096 segments)
for (int segnum = 0; segnum < 1024; segnum++) {
// assuming page_ofs = 0
int lpa = (segnum<<14) + logblk;
readPage(waitIdleReadBuffer(), lpa);
}
}
while (true) {
usleep(100);
if ( getNumReadsInFlight() == 0 ) break;
}
printf( "Test Erase!\n" ); fflush(stdout);
for (int logblk = 0; logblk < NUM_LOGBLKS; logblk++){
// test only 1024 segments due to some bad blocks (cannot allocate full 4096 segments)
for (int segnum = 0; segnum < 1024; segnum++) {
// assuming page_ofs = 0
int lpa = (segnum<<14) + logblk;
eraseBlock(waitIdleEraseTag(), lpa);
}
}
while (true) {
usleep(100);
if ( getNumErasesInFlight() == 0 ) break;
}
int elapsed = 0;
while (true) {
usleep(100);
if (elapsed == 0) {
elapsed=10000;
device->debugDumpReq(0);
}
else {
elapsed--;
}
if ( getNumReadsInFlight() == 0 ) break;
}
device->debugDumpReq(0);
clock_gettime(CLOCK_REALTIME, & now);
fprintf(stderr, "LOG: finished reading from page! %f\n", timespec_diff_sec(start, now) );
sleep(2);
}
