void ReinvokeISP(int can)
{
disable_timer32(0);
disable_timer32(1);
NVIC_DisableIRQ(UART_IRQn);
NVIC_DisableIRQ(CAN_IRQn);
LPC_SYSCON->SYSAHBCLKCTRL &= ~(1<<12); //Disable UART clock
LPC_SYSCON->SYSAHBCLKCTRL &= ~(1<<17); //Disable CAN clock
LPC_SYSCON->MAINCLKSEL = 0; /* Select IRC Clock Output */
LPC_SYSCON->MAINCLKUEN = 0x01; /* Update MCLK Clock Source */
LPC_SYSCON->MAINCLKUEN = 0x00; /* Toggle Update Register */
LPC_SYSCON->MAINCLKUEN = 0x01;
while (!(LPC_SYSCON->MAINCLKUEN & 0x01)); /* Wait Until Updated */
GPIOSetDir(PORT0, 3, E_IO_OUTPUT);
GPIOSetValue(PORT0, 3, can==0);
iap_command_param[0] = IAP_COMMAND_REINVOKE_ISP;
iap_entry(iap_command_param, iap_status_result);
}
/******************************************************************************
** Function name: init_timer32PWM
**
** Descriptions: Initialize timer as PWM
**
** parameters: timer number, period and match enable:
** match_enable[0] = PWM for MAT0
** match_enable[1] = PWM for MAT1
** match_enable[2] = PWM for MAT2
** Returned value: None
**
******************************************************************************/
void init_timer32PWM(uint8_t timer_num, uint32_t period, uint8_t match_enable)
{
disable_timer32(timer_num);
if (timer_num == 1)
{
LPC_SYSCON->SYSAHBCLKCTRL |= (1<<10);
/* Setup the external match register */
LPC_CT32B1->EMR = (1<<EMC3)|(1<<EMC2)|(2<<EMC1)|(1<<EMC0)|MATCH3|(match_enable);
/* Setup the outputs */
/* If match0 is enabled, set the output, use location 0 for test. */
set_timer32_match( timer_num, match_enable, 0 );
/* Enable the selected PWMs and enable Match3 */
LPC_CT32B1->PWMC = MATCH3|(match_enable);
/* Setup the match registers */
/* set the period value to a global variable */
timer32_1_period = period;
LPC_CT32B1->MR3 = timer32_1_period;
LPC_CT32B1->MR0 = timer32_1_period/2;
LPC_CT32B1->MR1 = timer32_1_period/2;
LPC_CT32B1->MR2 = timer32_1_period/2;
LPC_CT32B1->MCR = 1<<10; /* Reset on MR3 */
}
else
{
/* Some of the I/O pins need to be clearfully planned if
you use below module because JTAG and TIMER CAP/MAT pins are muxed. */
LPC_SYSCON->SYSAHBCLKCTRL |= (1<<9);
/* Setup the external match register */
LPC_CT32B0->EMR = (1<<EMC3)|(2<<EMC2)|(1<<EMC1)|(1<<EMC0)|MATCH3|(match_enable);
/* Setup the outputs */
/* If match0 is enabled, set the output, use location 0 for test. */
set_timer32_match( timer_num, match_enable, 0 );
/* Enable the selected PWMs and enable Match3 */
LPC_CT32B0->PWMC = MATCH3|(match_enable);
/* Setup the match registers */
/* set the period value to a global variable */
timer32_0_period = period;
LPC_CT32B0->MR3 = timer32_0_period;
LPC_CT32B0->MR0 = timer32_0_period/2;
LPC_CT32B0->MR1 = timer32_0_period/2;
LPC_CT32B0->MR2 = timer32_0_period/2;
LPC_CT32B0->MCR = 1<<10; /* Reset on MR3 */
}
}
/******************************************************************************
** Function name: init_timer32PWM
**
** Descriptions: Initialize timer as PWM
**
** parameters: timer number, period and match enable:
** match_enable[0] = PWM for MAT0
** match_enable[1] = PWM for MAT1
** match_enable[2] = PWM for MAT2
**
** Returned value: None
**
******************************************************************************/
void init_timer32PWM(uint8_t timer_num, uint32_t period, uint8_t match_enable)
{
disable_timer32(timer_num);
if (timer_num == 1)
{
/* Some of the I/O pins need to be clearfully planned if
you use below module because JTAG and TIMER CAP/MAT pins are muxed. */
LPC_SYSCON->SYSAHBCLKCTRL |= (1<<10);
/* Setup the external match register */
LPC_TMR32B1->EMR = (1<<EMC3)|(1<<EMC2)|(2<<EMC1)|(1<<EMC0)|(1<<3)|(match_enable);
/* Setup the outputs */
/* If match0 is enabled, set the output */
if (match_enable & 0x01)
{
LPC_IOCON->R_PIO1_1 &= ~0x07;
LPC_IOCON->R_PIO1_1 |= 0x03; /* Timer1_32 MAT0 */
}
/* If match1 is enabled, set the output */
if (match_enable & 0x02)
{
LPC_IOCON->R_PIO1_2 &= ~0x07;
LPC_IOCON->R_PIO1_2 |= 0x03; /* Timer1_32 MAT1 */
}
/* If match2 is enabled, set the output */
if (match_enable & 0x04)
{
LPC_IOCON->SWDIO_PIO1_3 &= ~0x07;
LPC_IOCON->SWDIO_PIO1_3 |= 0x03; /* Timer1_32 MAT2 */
}
/* If match3 is enabled, set the output */
if (match_enable & 0x08)
{
LPC_IOCON->PIO1_4 &= ~0x07;
LPC_IOCON->PIO1_4 |= 0x02; /* Timer1_32 MAT3 */
}
//#ifdef __JTAG_DISABLED
// PIO1_0_JTAG_TMS &= ~0x07; /* Timer1_32 I/O config */
// PIO1_0_JTAG_TMS |= 0x03; /* Timer1_32 CAP0 */
//#endif
/* Enable the selected PWMs and enable Match3 */
LPC_TMR32B1->PWMC = (1<<3)|(match_enable);
/* Setup the match registers */
/* set the period value to a global variable */
timer32_1_period = period;
LPC_TMR32B1->MR3 = timer32_1_period;
LPC_TMR32B1->MR0 = timer32_1_period/2;
LPC_TMR32B1->MR1 = timer32_1_period/2;
LPC_TMR32B1->MR2 = timer32_1_period/2;
/* */
LPC_TMR32B1->MCR = 1<<10; /* Reset on MR3 */
}
else
{
/* Some of the I/O pins need to be clearfully planned if
you use below module because JTAG and TIMER CAP/MAT pins are muxed. */
LPC_SYSCON->SYSAHBCLKCTRL |= (1<<9);
/* Setup the external match register */
LPC_TMR32B0->EMR = (1<<EMC3)|(2<<EMC2)|(1<<EMC1)|(1<<EMC0)|(1<<3)|(match_enable);
/* Setup the outputs */
/* If match0 is enabled, set the output */
if (match_enable & 0x01)
{
// LPC_IOCON->PIO1_6 &= ~0x07;
// LPC_IOCON->PIO1_6 |= 0x02; /* Timer0_32 MAT0 */
}
/* If match1 is enabled, set the output */
if (match_enable & 0x02)
{
LPC_IOCON-> PIO1_7 &= ~0x07;
LPC_IOCON->PIO1_7 |= 0x02; /* Timer0_32 MAT1 */
}
/* If match2 is enabled, set the output */
if (match_enable & 0x04)
{
LPC_IOCON->PIO0_1 &= ~0x07;
LPC_IOCON->PIO0_1 |= 0x02; /* Timer0_32 MAT2 */
}
/* If match3 is enabled, set the output */
if (match_enable & 0x08)
{
LPC_IOCON->R_PIO0_11 &= ~0x07;
LPC_IOCON->R_PIO0_11 |= 0x03; /* Timer0_32 MAT3 */
}
/* Enable the selected PWMs and enable Match3 */
LPC_TMR32B0->PWMC = (1<<3)|(match_enable);
/* Setup the match registers */
/* set the period value to a global variable */
timer32_0_period = period;
LPC_TMR32B0->MR3 = timer32_0_period;
LPC_TMR32B0->MR0 = timer32_0_period; ///2;
LPC_TMR32B0->MR1 = timer32_0_period/2;
LPC_TMR32B0->MR2 = timer32_0_period/2;
LPC_TMR32B0->MCR = 1<<10; /* Reset on MR3 */
}
}
