int display_hibernation_power_on(struct display_driver *dispdrv)
{
int ret = 0;
struct s3c_fb *sfb = dispdrv->decon_driver.sfb;
pm_info("##### +");
disp_pm_gate_lock(dispdrv, true);
mutex_lock(&dispdrv->pm_status.pm_lock);
if (sfb->power_state == POWER_ON) {
pr_info("%s, DECON are already power on state\n", __func__);
goto done;
}
request_dynamic_hotplug(false);
pm_runtime_get_sync(dispdrv->display_driver);
__display_hibernation_power_on(dispdrv);
sfb->power_state = POWER_ON;
done:
mutex_unlock(&dispdrv->pm_status.pm_lock);
disp_pm_gate_lock(dispdrv, false);
pm_info("##### -\n");
return ret;
}
int display_hibernation_power_off(struct display_driver *dispdrv)
{
int ret = 0;
struct s3c_fb *sfb = dispdrv->decon_driver.sfb;
disp_pm_gate_lock(dispdrv, true);
mutex_lock(&dispdrv->pm_status.pm_lock);
if (sfb->power_state == POWER_DOWN) {
pr_info("%s, DECON are already power off state\n", __func__);
goto done;
}
if (atomic_read(&dispdrv->pm_status.lock_count) > GATE_LOCK_CNT) {
pr_info("%s, DECON does not need power-off\n", __func__);
goto done;
}
if (get_display_line_count(dispdrv)) {
pm_debug("wait until last frame is totally transferred %d:",
get_display_line_count(dispdrv));
goto done;
}
pm_info("##### +");
sfb->power_state = POWER_HIBER_DOWN;
__display_hibernation_power_off(dispdrv);
disp_pm_runtime_put_sync(dispdrv);
request_dynamic_hotplug(true);
pm_info("##### -\n");
done:
mutex_unlock(&dispdrv->pm_status.pm_lock);
disp_pm_gate_lock(dispdrv, false);
return ret;
}
/* disp_pm_sched_power_on - it is called in the early start of the
* fb_ioctl to exit HDM */
int disp_pm_sched_power_on(struct display_driver *dispdrv, unsigned int cmd)
{
struct s3c_fb *sfb = dispdrv->decon_driver.sfb;
init_gating_idle_count(dispdrv);
/* First WIN_CONFIG should be on clock and power-gating */
if (dispdrv->platform_status < DISP_STATUS_PM1) {
if (cmd == S3CFB_WIN_CONFIG)
disp_pm_set_plat_status(dispdrv, true);
}
flush_kthread_worker(&dispdrv->pm_status.control_power_gating);
if (sfb->power_state == POWER_HIBER_DOWN) {
switch (cmd) {
case S3CFB_PLATFORM_RESET:
disp_pm_gate_lock(dispdrv, true);
queue_kthread_work(&dispdrv->pm_status.control_power_gating,
&dispdrv->pm_status.control_power_gating_work);
/* Prevent next clock and power-gating */
disp_pm_set_plat_status(dispdrv, false);
break;
case S3CFB_WIN_PSR_EXIT:
case S3CFB_WIN_CONFIG:
case S3CFB_SET_VSYNC_INT:
request_dynamic_hotplug(false);
disp_pm_gate_lock(dispdrv, true);
queue_kthread_work(&dispdrv->pm_status.control_power_gating,
&dispdrv->pm_status.control_power_gating_work);
break;
default:
return -EBUSY;
}
} else {
switch (cmd) {
case S3CFB_PLATFORM_RESET:
/* Prevent next clock and power-gating */
disp_pm_set_plat_status(dispdrv, false);
break;
}
}
return 0;
}
static void decon_clock_gating_handler(struct kthread_work *work)
{
struct display_driver *dispdrv = get_display_driver();
if (dispdrv->pm_status.clk_idle_count > MAX_CLK_GATING_COUNT)
display_block_clock_off(dispdrv);
init_gating_idle_count(dispdrv);
disp_pm_gate_lock(dispdrv, false);
pm_debug("display_block_clock_off -");
}
static void display_driver_shutdown(struct platform_device *pdev)
{
#ifdef CONFIG_FB_HIBERNATION_DISPLAY
struct display_driver *dispdrv = get_display_driver();
disp_set_pm_status(DISP_STATUS_PM2);
disp_pm_gate_lock(dispdrv, true);
disp_pm_add_refcount(get_display_driver());
#endif
#ifdef CONFIG_DECON_MIPI_DSI
s5p_mipi_dsi_disable(g_display_driver.dsi_driver.dsim);
#endif
}
static void decon_power_gating_handler(struct kthread_work *work)
{
struct display_driver *dispdrv = get_display_driver();
if (dispdrv->pm_status.pwr_idle_count > MAX_PWR_GATING_COUNT) {
if (!check_camera_is_running()) {
display_hibernation_power_off(dispdrv);
init_gating_idle_count(dispdrv);
}
} else if (dispdrv->decon_driver.sfb->power_state == POWER_HIBER_DOWN) {
display_hibernation_power_on(dispdrv);
}
disp_pm_gate_lock(dispdrv, false);
}
/* disp_pm_te_triggered - check clock gating or not.
* this function is called in the TE interrupt handler */
void disp_pm_te_triggered(struct display_driver *dispdrv)
{
te_count++;
if (!dispdrv->pm_status.power_gating_on) return;
spin_lock(&dispdrv->pm_status.slock);
if (dispdrv->platform_status > DISP_STATUS_PM0 &&
atomic_read(&dispdrv->pm_status.lock_count) == 0) {
++dispdrv->pm_status.pwr_idle_count;
if (dispdrv->pm_status.power_gating_on &&
dispdrv->pm_status.pwr_idle_count > MAX_PWR_GATING_COUNT) {
disp_pm_gate_lock(dispdrv, true);
queue_kthread_work(&dispdrv->pm_status.control_power_gating,
&dispdrv->pm_status.control_power_gating_work);
}
}
spin_unlock(&dispdrv->pm_status.slock);
}
/* disp_pm_te_triggered - check clock gating or not.
* this function is called in the TE interrupt handler */
void disp_pm_te_triggered(struct display_driver *dispdrv)
{
te_count++;
if (!dispdrv->pm_status.clock_gating_on) return;
spin_lock(&dispdrv->pm_status.slock);
if (dispdrv->platform_status > DISP_STATUS_PM0 &&
atomic_read(&dispdrv->pm_status.lock_count) == 0) {
if (dispdrv->pm_status.clock_enabled) {
if (!dispdrv->pm_status.trigger_masked)
enable_mask(dispdrv);
}
if (dispdrv->pm_status.clock_enabled &&
MAX_CLK_GATING_COUNT > 0) {
if (!dispdrv->pm_status.trigger_masked) {
enable_mask(dispdrv);
}
++dispdrv->pm_status.clk_idle_count;
if (dispdrv->pm_status.clk_idle_count > MAX_CLK_GATING_COUNT) {
disp_pm_gate_lock(dispdrv, true);
pm_debug("display_block_clock_off +");
queue_kthread_work(&dispdrv->pm_status.control_clock_gating,
&dispdrv->pm_status.control_clock_gating_work);
}
} else {
++dispdrv->pm_status.pwr_idle_count;
if (dispdrv->pm_status.power_gating_on &&
dispdrv->pm_status.pwr_idle_count > MAX_PWR_GATING_COUNT) {
queue_kthread_work(&dispdrv->pm_status.control_power_gating,
&dispdrv->pm_status.control_power_gating_work);
}
}
}
spin_unlock(&dispdrv->pm_status.slock);
}
