static void tegra_spi_dma_start(struct tegra_spi_channel *spi)
{
/*
* The RDY bit in SPI_TRANS_STATUS needs to be cleared manually
* (set bit to clear) between each transaction. Otherwise the next
* transaction does not start.
*/
setbits_le32(&spi->regs->trans_status, SPI_STATUS_RDY);
if (spi->dma_out)
setbits_le32(&spi->regs->command1, SPI_CMD1_TX_EN);
if (spi->dma_in)
setbits_le32(&spi->regs->command1, SPI_CMD1_RX_EN);
/*
* To avoid underrun conditions, enable APB DMA before SPI DMA for
* Tx and enable SPI DMA before APB DMA before Rx.
*/
if (spi->dma_out)
dma_start(spi->dma_out);
setbits_le32(&spi->regs->dma_ctl, SPI_DMA_CTL_DMA);
if (spi->dma_in)
dma_start(spi->dma_in);
}
static void tegra_spi_dma_start(struct tegra_spi_channel *spi)
{
/*
* The RDY bit in SPI_TRANS_STATUS needs to be cleared manually
* (set bit to clear) between each transaction. Otherwise the next
* transaction does not start.
*/
setbits_le32(&spi->regs->trans_status, SPI_STATUS_RDY);
struct apb_dma * const apb_dma = (struct apb_dma *)TEGRA_APB_DMA_BASE;
/*
* The DMA triggers have units of packets. As each packet is currently
* 1 byte the triggers need to be set to 4 packets (0b01) to match
* the AHB 32-bit (4 byte) tranfser. Otherwise the FIFO errors can
* occur.
*/
if (spi->dma_out) {
/* Enable secure access for the channel. */
setbits_le32(&apb_dma->security_reg,
SECURITY_EN_BIT(spi->dma_out->num));
clrsetbits_le32(&spi->regs->dma_ctl,
SPI_DMA_CTL_TX_TRIG_MASK << SPI_DMA_CTL_TX_TRIG_SHIFT,
1 << SPI_DMA_CTL_TX_TRIG_SHIFT);
setbits_le32(&spi->regs->command1, SPI_CMD1_TX_EN);
}
if (spi->dma_in) {
/* Enable secure access for the channel. */
setbits_le32(&apb_dma->security_reg,
SECURITY_EN_BIT(spi->dma_in->num));
clrsetbits_le32(&spi->regs->dma_ctl,
SPI_DMA_CTL_RX_TRIG_MASK << SPI_DMA_CTL_RX_TRIG_SHIFT,
1 << SPI_DMA_CTL_RX_TRIG_SHIFT);
setbits_le32(&spi->regs->command1, SPI_CMD1_RX_EN);
}
/*
* To avoid underrun conditions, enable APB DMA before SPI DMA for
* Tx and enable SPI DMA before APB DMA before Rx.
*/
if (spi->dma_out)
dma_start(spi->dma_out);
setbits_le32(&spi->regs->dma_ctl, SPI_DMA_CTL_DMA);
if (spi->dma_in)
dma_start(spi->dma_in);
}
static void xdma_start_transfer(struct xdma_chan *chan,
int start_index,
int end_index)
{
dma_addr_t cur_phys;
dma_addr_t tail_phys;
u32 regval;
if (chan->err)
return;
cur_phys = chan->bd_phys_addr + (start_index *
sizeof(struct xdma_desc_hw));
tail_phys = chan->bd_phys_addr + (end_index *
sizeof(struct xdma_desc_hw));
/* If hardware is busy, move the tail & return */
if (dma_is_running(chan) || dma_is_idle(chan)) {
/* Update tail ptr register and start the transfer */
DMA_OUT(&chan->regs->tdr, tail_phys);
return;
}
DMA_OUT(&chan->regs->cdr, cur_phys);
dma_start(chan);
/* Enable interrupts */
regval = DMA_IN(&chan->regs->cr);
regval |= (chan->poll_mode ? XDMA_XR_IRQ_ERROR_MASK
: XDMA_XR_IRQ_ALL_MASK);
DMA_OUT(&chan->regs->cr, regval);
/* Update tail ptr register and start the transfer */
DMA_OUT(&chan->regs->tdr, tail_phys);
}
void rcar_dma_exec(uintptr_t dst, uint32_t src, uint32_t len)
{
uint32_t dma_len = len;
if (len & DMA_FRACTION_MASK)
dma_len = (len + DMA_SIZE_UNIT) & ~DMA_FRACTION_MASK;
if (!dma_len || dma_len > DMA_LENGTH_LIMIT) {
ERROR("BL2: DMA - size invalid, length (0x%x)\n", dma_len);
panic();
}
if (src & DMA_FRACTION_MASK) {
ERROR("BL2: DMA - source address invalid (0x%x), "
"length (0x%x)\n", src, dma_len);
panic();
}
if ((dst & UINT32_MAX) + dma_len > DMADAR_BOUNDARY_ADDR ||
(dst + dma_len > DMA_DST_LIMIT) ||
(dst & DMA_FRACTION_MASK)) {
ERROR("BL2: DMA - destination address invalid (0x%lx), "
"length (0x%x)\n", dst, dma_len);
panic();
}
dma_start(dst, src, dma_len);
dma_end();
}
int dm9000_write(unsigned char data)
{
apbh_dma_gpmi1_t write;
write.nxt = (apbh_dma_gpmi1_t *)0;
write.cmd.u = 0x000110ca;
write.buff = &data;
write.gpmi_ctrl0.u = 0x00920001;
dma_start(5, &write, 1);
}
void pcm_play_data(void (*get_more)(unsigned char** start, long* size))
{
unsigned char *start;
long size;
callback_for_more = get_more;
get_more((unsigned char **)&start, (long *)&size);
get_more(&next_start, &next_size);
dma_start(start, size);
}
void dma_test(uint8_t *buf)
{
uint16_t i;
for (i = 0; i < 2048; i ++) buf[i] = 'd';
dma_start(buf, 2048);
//spi_write(CMD_FOO);
while (!(LPC_GPDMA->DMACIntTCStat & 0x01));
dma_test_data(buf);
}
int cdi_dma_open(struct cdi_dma_handle* handle,uint8_t channel,uint8_t mode,size_t length,void* buffer) {
if (dma_isready(channel) && length<=DMA_MAXCOUNT) {
handle->dmabuf = dma_alloc(length);
if (handle->dmabuf!=NULL) {
handle->channel = channel;
handle->mode = mode;
handle->length = length;
handle->buffer = buffer;
return dma_start(channel,handle->dmabuf,length,mode);
}
}
return -1;
}
ALWAYS_INLINE void tv_start_line_video() {
uint32_t lineIdx;
if (tvCurrentLine <= 313) {
lineIdx = ((uint32_t)tvCurrentLine-(5+PAL_VBLANK)) ;
} else {
lineIdx = ((uint32_t)tvCurrentLine-(317+PAL_VBLANK));
}
if (lineIdx<270) {
lineIdx = lineIdx*tvHeight/270;
jshPinSetState(tvPinVideo, JSHPINSTATE_AF_OUT); // re-enable output for SPI
uint32_t lsize = tvWidth>>3/*bytes*/;
dma_start((uint32_t)tvPixelPtr + lineIdx*lsize, lsize);
}
int dm9000_index(unsigned char cmd)
{
apbh_dma_gpmi1_t index;
index.nxt = (apbh_dma_gpmi1_t *)0;
index.cmd.u = 0x000110ca;
index.buff = &cmd;
index.gpmi_ctrl0.u = 0x00900001;
dma_start(5, &index, 1);
return 0;
}
unsigned char dm9000_read(void)
{
unsigned char data;
apbh_dma_gpmi1_t read;
read.nxt = (apbh_dma_gpmi1_t *)0;
read.cmd.u = 0x000110c9;
read.buff = &data;
read.gpmi_ctrl0.u = 0x01920001;
dma_start(5, &read, 1);
return data;
}
////////////////////////////////////////////////////
// 功能: 触发DMA中断，传送数据
// 输入:
// 输出:
// 返回:
// 说明:
////////////////////////////////////////////////////
void DmaDataToAic(int arg,unsigned int sour_addr, unsigned int len,unsigned char mode)
{
if( !arg )
{ //放音DMA
dma_cache_wback_inv(sour_addr, len);
CLRREG32(AIC_SR, AIC_SR_TUR);
SETREG32(AIC_CR, AIC_CR_ERPL);
dma_start(PLAYBACK_CHANNEL, PHYADDR(sour_addr), PHYADDR(AIC_DR),len,mode);
if (INREG32(AIC_SR) & AIC_SR_TUR)
CLRREG32(AIC_SR, AIC_SR_TUR);
}
else
{ //录音DMA
__dcache_inv((unsigned long)sour_addr, len);
SETREG32(AIC_CR, AIC_CR_EREC);
dma_start(RECORD_CHANNEL, PHYADDR(AIC_DR), PHYADDR(sour_addr),len,mode);
if (INREG32(A_AIC_AICSR) & AICSR_ROR)
CLRREG32(A_AIC_AICSR, AICSR_ROR);
}
}
static int reload_dma(struct device *dev_dma, u32_t channel,
struct dma_config *dcfg, void *src, void *dst,
u32_t blk_size)
{
int ret;
ret = dma_reload(dev_dma, channel, (u32_t)src, (u32_t)dst,
blk_size / sizeof(u16_t));
if (ret < 0) {
return ret;
}
ret = dma_start(dev_dma, channel);
return ret;
}
static long axi_dma_ioctl(struct file *filp, unsigned int cmd,
unsigned long arg)
{
struct axi_dma_config_info *config_info = (struct axi_dma_config_info *)arg;
switch (cmd) {
case XDMA_IOCTL_RESET:
if(config_info->channel == S2MM_CHANNEL){
dma_reset(config_info->channel, dma_wr_reg, config_info->reset_type);
}
break;
case XDMA_IOCTL_CONFIG:
if(config_info->channel == S2MM_CHANNEL){
//dma_init(config_info->channel, config_info->length, config_info->cycle,
// config_info->mem_addr, dma_wr_reg);
break;
}
break;
case XDMA_START_WAIT_COMPLETE:
if(config_info->channel == S2MM_CHANNEL){
dma_start(config_info->channel, 0, dma_wr_reg);
wait_for_completion(&dma_completion);
}
break;
case XDMA_MEM_ALLOC:
if(config_info->length > 8 && config_info->length <= MEM_MAX_SIZE) {
config_info->length = PAGE_ALIGN(config_info->length);
mem_info.size = config_info->length;
if(mem_info.size == 0) {
printk(KERN_ERR"alloc memory failed\n");
return -ENOMEM;
}
mem_info.mem_base = dma_alloc_writecombine(NULL, mem_info.size, &(mem_info.phy_base), GFP_KERNEL);
if(!mem_info.mem_base) {
mem_info.phy_base = 0;
printk(KERN_ERR"alloc memory failed\n");
return -ENOMEM;
}
config_info->mem_addr = (unsigned long)mem_info.phy_base;
mem_info.mark = MEM_ALLOC;
}
break;
default:
return -EINVAL;
break;
}
return 0;
}
static int start_dma(struct device *dev_dma, u32_t channel,
struct dma_config *dcfg, void *src, void *dst,
u32_t blk_size)
{
struct dma_block_config blk_cfg;
int ret;
memset(&blk_cfg, 0, sizeof(blk_cfg));
blk_cfg.block_size = blk_size / sizeof(u16_t);
blk_cfg.source_address = (u32_t)src;
blk_cfg.dest_address = (u32_t)dst;
dcfg->head_block = &blk_cfg;
ret = dma_config(dev_dma, channel, dcfg);
if (ret < 0) {
return ret;
}
ret = dma_start(dev_dma, channel);
return ret;
}
/*
* Pseudo (chained) interrupt from the esp driver to kick the
* current running DMA transfer. Called from ncr53c9x_intr()
* for now.
*
* return 1 if it was a DMA continue.
*/
int
lsi64854_scsi_intr(void *arg)
{
struct lsi64854_softc *sc = arg;
struct ncr53c9x_softc *nsc = sc->sc_client;
char bits[64];
int trans, resid;
uint32_t csr;
csr = L64854_GCSR(sc);
DPRINTF(LDB_SCSI, ("%s: %s: addr 0x%x, csr %s\n",
device_xname(sc->sc_dev), __func__,
bus_space_read_4(sc->sc_bustag, sc->sc_regs, L64854_REG_ADDR),
bitmask_snprintf(csr, DDMACSR_BITS, bits, sizeof(bits))));
if (csr & (D_ERR_PEND|D_SLAVE_ERR)) {
printf("%s: error: csr=%s\n", device_xname(sc->sc_dev),
bitmask_snprintf(csr, DDMACSR_BITS, bits,sizeof(bits)));
csr &= ~D_EN_DMA; /* Stop DMA */
/* Invalidate the queue; SLAVE_ERR bit is write-to-clear */
csr |= D_INVALIDATE|D_SLAVE_ERR;
L64854_SCSR(sc, csr);
return -1;
}
/* This is an "assertion" :) */
if (sc->sc_active == 0)
panic("%s: DMA wasn't active", __func__);
DMA_DRAIN(sc, 0);
/* DMA has stopped */
csr &= ~D_EN_DMA;
L64854_SCSR(sc, csr);
sc->sc_active = 0;
if (sc->sc_dmasize == 0) {
/* A "Transfer Pad" operation completed */
DPRINTF(LDB_SCSI, ("%s: discarded %d bytes (tcl=%d, tcm=%d)\n",
__func__,
NCR_READ_REG(nsc, NCR_TCL) |
(NCR_READ_REG(nsc, NCR_TCM) << 8),
NCR_READ_REG(nsc, NCR_TCL),
NCR_READ_REG(nsc, NCR_TCM)));
return 0;
}
resid = 0;
/*
* If a transfer onto the SCSI bus gets interrupted by the device
* (e.g. for a SAVEPOINTER message), the data in the FIFO counts
* as residual since the NCR53C9X counter registers get decremented
* as bytes are clocked into the FIFO.
*/
if (!(csr & D_WRITE) &&
(resid = (NCR_READ_REG(nsc, NCR_FFLAG) & NCRFIFO_FF)) != 0) {
DPRINTF(LDB_SCSI, ("%s: empty esp FIFO of %d ",
__func__, resid));
if (nsc->sc_rev == NCR_VARIANT_FAS366 &&
(NCR_READ_REG(nsc, NCR_CFG3) & NCRFASCFG3_EWIDE))
resid <<= 1;
}
if ((nsc->sc_espstat & NCRSTAT_TC) == 0) {
/*
* `Terminal count' is off, so read the residue
* out of the NCR53C9X counter registers.
*/
resid += (NCR_READ_REG(nsc, NCR_TCL) |
(NCR_READ_REG(nsc, NCR_TCM) << 8) |
((nsc->sc_cfg2 & NCRCFG2_FE) ?
(NCR_READ_REG(nsc, NCR_TCH) << 16) : 0));
if (resid == 0 && sc->sc_dmasize == 65536 &&
(nsc->sc_cfg2 & NCRCFG2_FE) == 0)
/* A transfer of 64K is encoded as `TCL=TCM=0' */
resid = 65536;
}
trans = sc->sc_dmasize - resid;
if (trans < 0) { /* transferred < 0 ? */
#if 0
/*
* This situation can happen in perfectly normal operation
* if the ESP is reselected while using DMA to select
* another target. As such, don't print the warning.
*/
printf("%s: xfer (%d) > req (%d)\n",
device_xname(&sc->sc_dev), trans, sc->sc_dmasize);
#endif
trans = sc->sc_dmasize;
}
DPRINTF(LDB_SCSI, ("%s: tcl=%d, tcm=%d, tch=%d; trans=%d, resid=%d\n",
__func__,
NCR_READ_REG(nsc, NCR_TCL),
NCR_READ_REG(nsc, NCR_TCM),
(nsc->sc_cfg2 & NCRCFG2_FE) ?
NCR_READ_REG(nsc, NCR_TCH) : 0,
trans, resid));
if (sc->sc_dmamap->dm_nsegs > 0) {
bus_dmamap_sync(sc->sc_dmatag, sc->sc_dmamap, 0, sc->sc_dmasize,
(csr & D_WRITE) != 0 ?
BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
bus_dmamap_unload(sc->sc_dmatag, sc->sc_dmamap);
}
*sc->sc_dmalen -= trans;
*sc->sc_dmaaddr += trans;
#if 0 /* this is not normal operation just yet */
if (*sc->sc_dmalen == 0 ||
nsc->sc_phase != nsc->sc_prevphase)
return 0;
/* and again */
dma_start(sc, sc->sc_dmaaddr, sc->sc_dmalen, DMACSR(sc) & D_WRITE);
return 1;
#endif
return 0;
}
/*
* Pseudo (chained) interrupt from the esp driver to kick the
* current running DMA transfer. Called from ncr53c9x_intr()
* for now.
*
* return 1 if it was a DMA continue.
*/
static int
lsi64854_scsi_intr(void *arg)
{
struct lsi64854_softc *sc = arg;
struct ncr53c9x_softc *nsc = sc->sc_client;
bus_dma_tag_t dmat;
bus_dmamap_t dmam;
size_t dmasize;
int lxfer, resid, trans;
uint32_t csr;
csr = L64854_GCSR(sc);
DPRINTF(LDB_SCSI, ("%s: addr 0x%x, csr %b\n", __func__,
bus_read_4(sc->sc_res, L64854_REG_ADDR), csr, DDMACSR_BITS));
if (csr & (D_ERR_PEND | D_SLAVE_ERR)) {
device_printf(sc->sc_dev, "error: csr=%b\n", csr,
DDMACSR_BITS);
csr &= ~D_EN_DMA; /* Stop DMA. */
/* Invalidate the queue; SLAVE_ERR bit is write-to-clear */
csr |= D_INVALIDATE | D_SLAVE_ERR;
L64854_SCSR(sc, csr);
return (-1);
}
/* This is an "assertion" :) */
if (sc->sc_active == 0)
panic("%s: DMA wasn't active", __func__);
DMA_DRAIN(sc, 0);
/* DMA has stopped */
csr &= ~D_EN_DMA;
L64854_SCSR(sc, csr);
sc->sc_active = 0;
dmasize = sc->sc_dmasize;
if (dmasize == 0) {
/* A "Transfer Pad" operation completed. */
DPRINTF(LDB_SCSI, ("%s: discarded %d bytes (tcl=%d, "
"tcm=%d)\n", __func__, NCR_READ_REG(nsc, NCR_TCL) |
(NCR_READ_REG(nsc, NCR_TCM) << 8),
NCR_READ_REG(nsc, NCR_TCL), NCR_READ_REG(nsc, NCR_TCM)));
return (0);
}
resid = 0;
/*
* If a transfer onto the SCSI bus gets interrupted by the device
* (e.g. for a SAVEPOINTER message), the data in the FIFO counts
* as residual since the NCR53C9X counter registers get decremented
* as bytes are clocked into the FIFO.
*/
if ((csr & D_WRITE) == 0 &&
(resid = (NCR_READ_REG(nsc, NCR_FFLAG) & NCRFIFO_FF)) != 0) {
DPRINTF(LDB_SCSI, ("%s: empty esp FIFO of %d ", __func__,
resid));
if (nsc->sc_rev == NCR_VARIANT_FAS366 &&
(NCR_READ_REG(nsc, NCR_CFG3) & NCRFASCFG3_EWIDE))
resid <<= 1;
}
if ((nsc->sc_espstat & NCRSTAT_TC) == 0) {
lxfer = nsc->sc_features & NCR_F_LARGEXFER;
/*
* "Terminal count" is off, so read the residue
* out of the NCR53C9X counter registers.
*/
resid += (NCR_READ_REG(nsc, NCR_TCL) |
(NCR_READ_REG(nsc, NCR_TCM) << 8) |
(lxfer != 0 ? (NCR_READ_REG(nsc, NCR_TCH) << 16) : 0));
if (resid == 0 && dmasize == 65536 && lxfer == 0)
/* A transfer of 64k is encoded as TCL=TCM=0. */
resid = 65536;
}
trans = dmasize - resid;
if (trans < 0) { /* transferred < 0? */
#if 0
/*
* This situation can happen in perfectly normal operation
* if the ESP is reselected while using DMA to select
* another target. As such, don't print the warning.
*/
device_printf(sc->sc_dev, "xfer (%d) > req (%d)\n", trans,
dmasize);
#endif
trans = dmasize;
}
DPRINTF(LDB_SCSI, ("%s: tcl=%d, tcm=%d, tch=%d; trans=%d, resid=%d\n",
__func__, NCR_READ_REG(nsc, NCR_TCL), NCR_READ_REG(nsc, NCR_TCM),
(nsc->sc_features & NCR_F_LARGEXFER) != 0 ?
NCR_READ_REG(nsc, NCR_TCH) : 0, trans, resid));
if (dmasize != 0) {
dmat = sc->sc_buffer_dmat;
dmam = sc->sc_dmamap;
bus_dmamap_sync(dmat, dmam, (csr & D_WRITE) != 0 ?
BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
bus_dmamap_unload(dmat, dmam);
}
*sc->sc_dmalen -= trans;
*sc->sc_dmaaddr = (char *)*sc->sc_dmaaddr + trans;
#if 0 /* this is not normal operation just yet */
if (*sc->sc_dmalen == 0 || nsc->sc_phase != nsc->sc_prevphase)
return (0);
/* and again */
dma_start(sc, sc->sc_dmaaddr, sc->sc_dmalen, DMACSR(sc) & D_WRITE);
return (1);
#endif
return (0);
}
int gboot_main()
{
int num;
//unsigned char buf[1024*4];
#ifdef MMU_ON
mmu_init();
#endif
uart_init();
led_init();
button_init();
//init_irq();
led_on();
dma_init();
dma_start();
/*
NF_Erase(128*1+1);
buf[0] = 100;
NF_WritePage(128*1+1,buf);
buf[0] = 10;
NF_PageRead(128*1+1,buf);
if( buf[0] == 100 )
led_on();
*/
//putc(0x0d);
//putc(0x0a);
//putc('H');
//uart_send_string(buff);
//printf("Hello GBOOT!\n");
while(1)
{
//getc();
printf("\n\r***************************************\n\r");
printf("\n\r*****************GBOOT*****************\n\r");
printf("1:Download Linux Kernel from TFTP Server!\n\r");
printf("2:Boot Linux from RAM!\n\r");
printf("3:Boor Linux from Nand Flash!\n\r");
printf("\n Plese Select:");
scanf("%d",&num);
switch (num)
{
case 1:
//tftp_load();
break;
case 2:
//boot_linux_ram();
break;
case 3:
//boot_linux_nand();
break;
default:
printf("Error: wrong selection!\n\r");
break;
}
}
return 0;
}
/*
* Pseudo (chained) interrupt from the esp driver to kick the
* current running DMA transfer. I am replying on espintr() to
* pickup and clean errors for now
*
* return 1 if it was a DMA continue.
*/
int
espdmaintr(struct esp_softc *sc)
{
struct ncr53c9x_softc *nsc = (struct ncr53c9x_softc *)sc;
int trans, resid;
u_long csr = sc->sc_dma_direction;
#if 0
if (csr & D_ERR_PEND) {
DMACSR(sc) &= ~D_EN_DMA; /* Stop DMA */
DMACSR(sc) |= D_INVALIDATE;
printf("%s: error: csr=%s\n", device_xname(nsc->sc_dev),
bitmask_snprintf(csr, DMACSRBITS, bits, sizeof(bits)));
return -1;
}
#endif
/* This is an "assertion" :) */
if (sc->sc_dmaactive == 0)
panic("%s: DMA wasn't active", __func__);
/* dbdma_flush(sc->sc_dmareg); */
/* DMA has stopped */
dbdma_stop(sc->sc_dmareg);
sc->sc_dmaactive = 0;
if (sc->sc_dmasize == 0) {
/* A "Transfer Pad" operation completed */
NCR_DMA(("dmaintr: discarded %d bytes (tcl=%d, tcm=%d)\n",
NCR_READ_REG(nsc, NCR_TCL) |
(NCR_READ_REG(nsc, NCR_TCM) << 8),
NCR_READ_REG(nsc, NCR_TCL),
NCR_READ_REG(nsc, NCR_TCM)));
return 0;
}
resid = 0;
/*
* If a transfer onto the SCSI bus gets interrupted by the device
* (e.g. for a SAVEPOINTER message), the data in the FIFO counts
* as residual since the ESP counter registers get decremented as
* bytes are clocked into the FIFO.
*/
if (!(csr & D_WRITE) &&
(resid = (NCR_READ_REG(nsc, NCR_FFLAG) & NCRFIFO_FF)) != 0) {
NCR_DMA(("dmaintr: empty esp FIFO of %d ", resid));
}
if ((nsc->sc_espstat & NCRSTAT_TC) == 0) {
/*
* `Terminal count' is off, so read the residue
* out of the ESP counter registers.
*/
resid += (NCR_READ_REG(nsc, NCR_TCL) |
(NCR_READ_REG(nsc, NCR_TCM) << 8) |
((nsc->sc_cfg2 & NCRCFG2_FE)
? (NCR_READ_REG(nsc, NCR_TCH) << 16)
: 0));
if (resid == 0 && sc->sc_dmasize == 65536 &&
(nsc->sc_cfg2 & NCRCFG2_FE) == 0)
/* A transfer of 64K is encoded as `TCL=TCM=0' */
resid = 65536;
}
trans = sc->sc_dmasize - resid;
if (trans < 0) { /* transferred < 0 ? */
#if 0
/*
* This situation can happen in perfectly normal operation
* if the ESP is reselected while using DMA to select
* another target. As such, don't print the warning.
*/
printf("%s: xfer (%d) > req (%d)\n",
device_xname(nsc->sc_dev), trans, sc->sc_dmasize);
#endif
trans = sc->sc_dmasize;
}
NCR_DMA(("dmaintr: tcl=%d, tcm=%d, tch=%d; trans=%d, resid=%d\n",
NCR_READ_REG(nsc, NCR_TCL),
NCR_READ_REG(nsc, NCR_TCM),
(nsc->sc_cfg2 & NCRCFG2_FE)
? NCR_READ_REG(nsc, NCR_TCH) : 0,
trans, resid));
#if 0
if (csr & D_WRITE)
flushcache(*sc->sc_dmaaddr, trans);
#endif
*sc->sc_dmalen -= trans;
*sc->sc_dmaaddr += trans;
#if 0 /* this is not normal operation just yet */
if (*sc->sc_dmalen == 0 ||
nsc->sc_phase != nsc->sc_prevphase)
return 0;
/* and again */
dma_start(sc, sc->sc_dmaaddr, sc->sc_dmalen, DMACSR(sc) & D_WRITE);
return 1;
#endif
return 0;
}
/**
* Render the PWM DMA buffer from the user supplied LED arrays and start the DMA
* controller. This will update all LEDs on both PWM channels.
*
* @param ws2811 ws2811 instance pointer.
*
* @returns None
*/
int ws2811_render(ws2811_t *ws2811)
{
volatile uint8_t *pwm_raw = ws2811->device->pwm_raw;
int bitpos = 31;
int i, k, l, chan;
unsigned j;
for (chan = 0; chan < RPI_PWM_CHANNELS; chan++) // Channel
{
ws2811_channel_t *channel = &ws2811->channel[chan];
int wordpos = chan;
int scale = (channel->brightness & 0xff) + 1;
int wshift = (channel->strip_type >> 24) & 0xff;
int rshift = (channel->strip_type >> 16) & 0xff;
int gshift = (channel->strip_type >> 8) & 0xff;
int bshift = (channel->strip_type >> 0) & 0xff;
for (i = 0; i < channel->count; i++) // Led
{
uint8_t color[] =
{
(((channel->leds[i] >> rshift) & 0xff) * scale) >> 8, // red
(((channel->leds[i] >> gshift) & 0xff) * scale) >> 8, // green
(((channel->leds[i] >> bshift) & 0xff) * scale) >> 8, // blue
(((channel->leds[i] >> wshift) & 0xff) * scale) >> 8, // white
};
uint8_t array_size = 3; // Assume 3 color LEDs, RGB
// If our shift mask includes the highest nibble, then we have 4
// LEDs, RBGW.
if (channel->strip_type & SK6812_SHIFT_WMASK)
{
array_size = 4;
}
for (j = 0; j < array_size; j++) // Color
{
for (k = 7; k >= 0; k--) // Bit
{
uint8_t symbol = SYMBOL_LOW;
if (color[j] & (1 << k))
{
symbol = SYMBOL_HIGH;
}
for (l = 2; l >= 0; l--) // Symbol
{
uint32_t *wordptr = &((uint32_t *)pwm_raw)[wordpos];
*wordptr &= ~(1 << bitpos);
if (symbol & (1 << l))
{
*wordptr |= (1 << bitpos);
}
bitpos--;
if (bitpos < 0)
{
// Every other word is on the same channel
wordpos += 2;
bitpos = 31;
}
}
}
}
}
}
// Wait for any previous DMA operation to complete.
if (ws2811_wait(ws2811))
{
return -1;
}
dma_start(ws2811);
return 0;
}
int
scsiicmd(char target, char lun,
u_char *cbuf, int clen,
char *addr, int len)
{
volatile caddr_t sr;
int i;
DPRINTF(("scsiicmd: [%x, %d] -> %d (%lx, %d)\n",*cbuf, clen,
target, (long)addr, len));
sr = P_SCSI;
if (sc->sc_state != SCSI_IDLE) {
scsierror("scsiiscmd: bad state");
return EIO;
}
sc->sc_result = 0;
/* select target */
sr[ESP_CMD] = ESPCMD_FLUSH;
DELAY(10);
sr[ESP_SELID] = target;
sr[ESP_FIFO] = MSG_IDENTIFY(lun, 0);
for (i=0; i<clen; i++)
sr[ESP_FIFO] = cbuf[i];
sr[ESP_CMD] = ESPCMD_SELATN;
sc->sc_state = SCSI_SELECTING;
while(sc->sc_state != SCSI_DONE) {
if (scsi_wait_for_intr()) /* maybe we'd better use real intrs ? */
return EIO;
if (sc->sc_state == SCSI_DMA)
{
/* registers are not valid on dma intr */
sc->sc_status = sc->sc_seqstep = sc->sc_intrstatus = 0;
DPRINTF(("scsiicmd: dma intr\n"));
} else {
/* scsi processing */
sc->sc_status = sr[ESP_STAT];
sc->sc_seqstep = sr[ESP_STEP];
sc->sc_intrstatus = sr[ESP_INTR];
DPRINTF(("scsiicmd: regs[intr=%x, stat=%x, step=%x]\n",
sc->sc_intrstatus, sc->sc_status, sc->sc_seqstep));
}
if (sc->sc_intrstatus & ESPINTR_SBR) {
scsierror("scsi bus reset");
return EIO;
}
if ((sc->sc_status & ESPSTAT_GE)
|| (sc->sc_intrstatus & ESPINTR_ILL)) {
scsierror("software error");
return EIO;
}
if (sc->sc_status & ESPSTAT_PE)
{
scsierror("parity error");
return EIO;
}
switch(sc->sc_state)
{
case SCSI_SELECTING:
if (sc->sc_intrstatus & ESPINTR_DIS)
{
sc->sc_state = SCSI_IDLE;
return EUNIT; /* device not present */
}
#define ESPINTR_DONE (ESPINTR_BS | ESPINTR_FC)
if ((sc->sc_intrstatus & ESPINTR_DONE) != ESPINTR_DONE)
{
scsierror("selection failed");
return EIO;
}
sc->sc_state = SCSI_HASBUS;
break;
case SCSI_HASBUS:
if (sc->sc_intrstatus & ESPINTR_DIS)
{
scsierror("target disconnected");
return EIO;
}
break;
case SCSI_DMA:
if (sc->sc_intrstatus & ESPINTR_DIS)
{
scsierror("target disconnected");
return EIO;
}
if (dma_done() != 0)
return EIO;
continue;
case SCSI_CLEANUP:
if (sc->sc_intrstatus & ESPINTR_DIS)
{
sc->sc_state = SCSI_DONE;
continue;
}
DPRINTF(("hmm ... no disconnect on cleanup?\n"));
sc->sc_state = SCSI_DONE; /* maybe ... */
break;
}
/* transfer information now */
switch(sc->sc_status & ESPSTAT_PHASE)
{
case DATA_IN_PHASE:
if (dma_start(addr, len) != 0)
return EIO;
break;
case DATA_OUT_PHASE:
scsierror("data out phase not implemented");
return EIO;
case STATUS_PHASE:
DPRINTF(("status phase: "));
sr[ESP_CMD] = ESPCMD_ICCS;
sc->sc_result = scsi_getbyte(sr);
DPRINTF(("status is 0x%x.\n", sc->sc_result));
break;
case MSG_IN_PHASE:
if (scsi_msgin() != 0)
return EIO;
break;
default:
DPRINTF(("phase not implemented: 0x%x.\n",
sc->sc_status & ESPSTAT_PHASE));
scsierror("bad phase");
return EIO;
}
}
sc->sc_state = SCSI_IDLE;
return -sc->sc_result;
}
int gboot_main()
{
int num;
#ifdef MMU_ON
mmu_init();
#endif
led_init();
button_init();
init_irq();
led_on();
uart_init();
dma_init();
dma_start();
/*
putc(0x0d);
putc(0x0a);
putc('H');
*/
//uart_send_string(buf);
//putc('A');
while(1)
{
//getc();
printf("\n\r***************************************\n\r");
printf("\n\r*****************GBOOT*****************\n\r");
printf("1:Download Linux Kernel from TFTP Server!\n\r");
printf("2:Boot Linux from RAM!\n\r");
printf("3:Boor Linux from Nand Flash!\n\r");
printf("\n Plese Select:");
scanf("%d",&num);
switch (num)
{
case 1:
//tftp_load();
break;
case 2:
//boot_linux_ram();
break;
case 3:
//boot_linux_nand();
break;
default:
printf("Error: wrong selection!\n\r");
break;
}
}
return 0;
}
/**
* Render the PWM DMA buffer from the user supplied LED arrays and start the DMA
* controller. This will update all LEDs on both PWM channels.
*
* @param ws2811 ws2811 instance pointer.
*
* @returns None
*/
int ws2811_render(ws2811_t *ws2811)
{
volatile uint8_t *pwm_raw = ws2811->device->pwm_raw;
int bitpos = 31;
int i, j, k, l, chan;
for (chan = 0; chan < RPI_PWM_CHANNELS; chan++) // Channel
{
ws2811_channel_t *channel = &ws2811->channel[chan];
int wordpos = chan;
int scale = (channel->brightness & 0xff) + 1;
for (i = 0; i < channel->count; i++) // Led
{
uint8_t color[] =
{
(((channel->leds[i] >> 8) & 0xff) * scale) >> 8, // green
(((channel->leds[i] >> 16) & 0xff) * scale) >> 8, // red
(((channel->leds[i] >> 0) & 0xff) * scale) >> 8, // blue
};
for (j = 0; j < (int) ARRAY_SIZE(color); j++) // Color
{
for (k = 7; k >= 0; k--) // Bit
{
uint8_t symbol = SYMBOL_LOW;
if (color[j] & (1 << k))
{
symbol = SYMBOL_HIGH;
}
if (channel->invert)
{
symbol = ~symbol & 0x7;
}
for (l = 2; l >= 0; l--) // Symbol
{
uint32_t *wordptr = &((uint32_t *)pwm_raw)[wordpos];
*wordptr &= ~(1 << bitpos);
if (symbol & (1 << l))
{
*wordptr |= (1 << bitpos);
}
bitpos--;
if (bitpos < 0)
{
// Every other word is on the same channel
wordpos += 2;
bitpos = 31;
}
}
}
}
}
}
// Wait for any previous DMA operation to complete.
if (ws2811_wait(ws2811))
{
return -1;
}
dma_start(ws2811);
return 0;
}
/**
* Render the PWM DMA buffer from the user supplied LED arrays and start the DMA
* controller. This will update all LEDs on both PWM channels.
*
* @param ws2811 ws2811 instance pointer.
*
* @returns None
*/
int ws2811_render(ws2811_t *ws2811)
{
volatile uint8_t *pwm_raw = ws2811->device->pwm_raw;
int bitpos = 31;
int i, k, l, chan;
unsigned j;
for (chan = 0; chan < RPI_PWM_CHANNELS; chan++) // Channel
{
ws2811_channel_t *channel = &ws2811->channel[chan];
int wordpos = chan;
int scale = (channel->brightness & 0xff) + 1;
int wshift = (channel->strip_type >> 24) & 0xff;
int rshift = (channel->strip_type >> 16) & 0xff;
int gshift = (channel->strip_type >> 8) & 0xff;
int bshift = (channel->strip_type >> 0) & 0xff;
//printf ("chan %d, wshift %d rshift %d gshift %d bshift %d \n",chan, wshift,rshift, gshift, bshift);
for (i = 0; i < channel->count; i++) // Led
{
uint8_t color[] =
{
(((channel->leds[i] >> rshift) & 0xff) * scale) >> 8, // red
(((channel->leds[i] >> gshift) & 0xff) * scale) >> 8, // green
(((channel->leds[i] >> bshift) & 0xff) * scale) >> 8, // blue
(((channel->leds[i] >> wshift) & 0xff) * scale) >> 8, // white
};
//if (i<10) printf ("i %3d red %02x green %02x blue %02x white %02x\n", i, color[0], color[1], color[2], color[3]);
int array_size = 3; // assume 3 for RGB
if (channel->strip_type == SK6812_STRIP_RGBW) {
array_size = 4; // this strip needs 4 - RGB + W
}
for (j = 0; j < array_size; j++) // Color
{
for (k = 7; k >= 0; k--) // Bit
{
uint8_t symbol = SYMBOL_LOW;
if (color[j] & (1 << k))
{
symbol = SYMBOL_HIGH;
}
for (l = 2; l >= 0; l--) // Symbol
{
uint32_t *wordptr = &((uint32_t *)pwm_raw)[wordpos];
*wordptr &= ~(1 << bitpos);
if (symbol & (1 << l))
{
*wordptr |= (1 << bitpos);
}
bitpos--;
if (bitpos < 0)
{
// Every other word is on the same channel
wordpos += 2;
bitpos = 31;
}
}
}
}
}
}
// Wait for any previous DMA operation to complete.
if (ws2811_wait(ws2811))
{
return -1;
}
dma_start(ws2811);
return 0;
}
int gboot_main()
{
int num;
//unsigned char buf[1024*4];
#ifdef MMU_ON
mmu_init();
#endif
uart_init();
led_init();
button_init();
init_irq();
led_off();
dma_init();
dma_start();
dm9000_init();
while(1)
{
printf("\n***************************************\n\r");
printf("\n****************MYBOOT*****************\n\r");
printf("1:Set Out a Arp Package to Get Host Ip and MAC!\n\r");
printf("2:Download Linux Kernel from TFTP Server!\n\r");
printf("3:Boot Linux from RAM!\n\r");
printf("\n Plese Select:");
scanf("%d",&num);
switch (num)
{
case 1:
arp_progress();
break;
case 2:
tftp_send_request("tftp.c");
while(FLAG_TFTP);
break;
case 3:
boot_linux();
//boot_linux_nand();
break;
default:
printf("Error: wrong selection!\n\r");
break;
}
}
return 0;
}
void dma_transfer(uint8_t *buf)
{
dma_start(buf, 2048);
//spi_write(CMD_FOO);
while (!(LPC_GPDMA->DMACIntTCStat & 0x01));
}
static void camera_interrupt(int irq, void *client_data,
struct pt_regs *regs)
{
#ifdef NO_CAM_DMA
static int nextIn;
#endif
u32 itstat;
ENTRY();
spin_lock(&camif_lock);
itstat = camera_regs->it_status;
if (itstat & V_UP) {
if (snapshot_active || streaming_active) {
camif_cleanfifo();
camif_mode_clear(EN_V_UP);
#ifdef NO_CAM_DMA
camif_mode_set(EN_NIRQ | EN_V_DOWN | EN_FIFO_FULL);
nextIn = 0;
#else
camif_mode_set(EN_DMA | EN_FIFO_FULL);
dma_start();
#endif
}
wake_up_interruptible(&vsync_wait);
}
if (itstat & DATA_XFER) {
#ifdef NO_CAM_DMA
if (snapshot_active || streaming_active) {
int i;
volatile u32* ptr = &((u32*)capture_buffer)[nextIn];
for (i=0;i<FIFO_TRIGGER_LVL;i++)
ptr[i] = camera_regs->camdata;
nextIn += FIFO_TRIGGER_LVL;
}
#endif
}
if (itstat & V_DOWN) {
#ifdef NO_CAM_DMA
snapshot_active = 0;
if (streaming_active)
nextIn = 0;
else
camif_mode_clear(EN_NIRQ | EN_V_DOWN | EN_FIFO_FULL);
spin_unlock(&camif_lock);
// callback to V4L2 layer
capture_callback(callback_data);
spin_lock(&camif_lock);
#endif
wake_up_interruptible(&vsync_wait);
}
if (itstat & H_UP) {
dbg("H_UP set\n");
}
if (itstat & H_DOWN) {
dbg("H_DOWN set\n");
}
if (itstat & FIFO_FULL) {
camif_cleanfifo();
dbg("FIFO_FULL set\n");
}
spin_unlock(&camif_lock);
EXIT();
}
