static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
{
struct combiner_chip_data *chip_data = irq_get_handler_data(irq);
struct irq_chip *chip = irq_get_chip(irq);
unsigned int cascade_irq, combiner_irq;
unsigned long status;
chained_irq_enter(chip, desc);
spin_lock(&irq_controller_lock);
status = __raw_readl(chip_data->base + COMBINER_INT_STATUS);
spin_unlock(&irq_controller_lock);
status &= chip_data->irq_mask;
if (status == 0) {
do_bad_IRQ(irq, desc);
goto out;
}
combiner_irq = __ffs(status);
cascade_irq = combiner_irq + (chip_data->irq_offset & ~31);
if (unlikely(cascade_irq >= NR_IRQS))
do_bad_IRQ(cascade_irq, desc);
else
generic_handle_irq(cascade_irq);
out:
chained_irq_exit(chip, desc);
}
static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
{
struct gic_chip_data *chip_data = get_irq_data(irq);
struct irq_chip *chip = get_irq_chip(irq);
unsigned int cascade_irq, gic_irq;
unsigned long status;
/* primary controller ack'ing */
chip->ack(irq);
spin_lock(&irq_controller_lock);
status = readl(chip_data->cpu_base + GIC_CPU_INTACK);
spin_unlock(&irq_controller_lock);
gic_irq = (status & 0x3ff);
if (gic_irq == 1023)
goto out;
cascade_irq = gic_irq + chip_data->irq_offset;
if (unlikely(gic_irq < 32 || gic_irq > 1020 || cascade_irq >= NR_IRQS))
do_bad_IRQ(cascade_irq, desc);
else
generic_handle_irq(cascade_irq);
out:
/* primary controller unmasking */
chip->unmask(irq);
}
static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
{
struct gic_chip_data *chip_data = irq_get_handler_data(irq);
struct irq_chip *chip = irq_get_chip(irq);
unsigned int cascade_irq, gic_irq;
unsigned long status;
chained_irq_enter(chip, desc);
raw_spin_lock(&irq_controller_lock);
status = readl_relaxed(chip_data->cpu_base + GIC_CPU_INTACK);
raw_spin_unlock(&irq_controller_lock);
gic_irq = (status & 0x3ff);
if (gic_irq == 1023)
goto out;
cascade_irq = gic_irq + chip_data->irq_offset;
if (unlikely(gic_irq < 32 || gic_irq > 1020 || cascade_irq >= NR_IRQS))
do_bad_IRQ(cascade_irq, desc);
else
generic_handle_irq(cascade_irq);
out:
chained_irq_exit(chip, desc);
}
static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
{
struct combiner_chip_data *chip_data = irq_get_handler_data(irq);
struct irq_chip *chip = irq_get_chip(irq);
unsigned int cascade_irq, combiner_irq;
unsigned long status;
chained_irq_enter(chip, desc);
spin_lock(&irq_controller_lock);
status = readl_relaxed(chip_data->base + COMBINER_INT_STATUS);
spin_unlock(&irq_controller_lock);
status &= chip_data->irq_mask;
if (status == 0)
goto out;
combiner_irq = chip_data->hwirq_offset + __ffs(status);
cascade_irq = irq_find_mapping(combiner_irq_domain, combiner_irq);
if (unlikely(!cascade_irq))
do_bad_IRQ(irq, desc);
else
generic_handle_irq(cascade_irq);
out:
chained_irq_exit(chip, desc);
}
static void s5p_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
{
u32 a16_23, a24_31;
a16_23 = s5p_irq_demux_eint(IRQ_EINT(16));
a24_31 = s5p_irq_demux_eint(IRQ_EINT(24));
if (!a16_23 && !a24_31)
do_bad_IRQ(irq, desc);
}
static void
isa_irq_handler(unsigned int irq, struct irq_desc *desc)
{
unsigned int isa_irq = *(unsigned char *)PCIIACK_BASE;
if (isa_irq < _ISA_IRQ(0) || isa_irq >= _ISA_IRQ(16)) {
do_bad_IRQ(isa_irq, desc);
return;
}
generic_handle_irq(isa_irq);
}
static void
isa_irq_handler(unsigned int irq, struct irqdesc *desc, struct pt_regs *regs)
{
unsigned int isa_irq = *(unsigned char *)PCIIACK_BASE;
if (isa_irq < _ISA_IRQ(0) || isa_irq >= _ISA_IRQ(16)) {
do_bad_IRQ(isa_irq, desc, regs);
return;
}
desc = irq_desc + isa_irq;
desc->handle(isa_irq, desc, regs);
}
static void exynos_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
{
struct irq_chip *chip = irq_get_chip(irq);
u32 a16_23, a24_31;
chained_irq_enter(chip, desc);
a16_23 = exynos_irq_demux_eint(IRQ_EINT(16));
a24_31 = exynos_irq_demux_eint(IRQ_EINT(24));
chained_irq_exit(chip, desc);
if (!a16_23 && !a24_31)
do_bad_IRQ(irq, desc);
}
static void fpga_irq_handle(unsigned int irq, struct irq_desc *desc)
{
struct fpga_irq_data *f = irq_desc_get_handler_data(desc);
u32 status = readl(f->base + IRQ_STATUS);
if (status == 0) {
do_bad_IRQ(irq, desc);
return;
}
do {
irq = ffs(status) - 1;
status &= ~(1 << irq);
generic_handle_irq(irq_find_mapping(f->domain, irq));
} while (status);
}
static void s5pv310_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
{
struct irq_chip *chip = get_irq_chip(irq);
u32 a16_23, a24_31;
if (chip->ack)
chip->ack(irq);
a16_23 = s5pv310_irq_demux_eint(irq, IRQ_EINT(16));
a24_31 = s5pv310_irq_demux_eint(irq, IRQ_EINT(24));
if (!a16_23 && !a24_31)
do_bad_IRQ(irq, desc);
chip->unmask(irq);
}
static void pmu_irq_handler(unsigned int irq, struct irq_desc *desc)
{
unsigned long cause = readl(PMU_INTERRUPT_CAUSE);
cause &= readl(PMU_INTERRUPT_MASK);
if (cause == 0) {
do_bad_IRQ(irq, desc);
return;
}
for (irq = 0; irq < NR_PMU_IRQS; irq++) {
if (!(cause & (1 << irq)))
continue;
irq = pmu_to_irq(irq);
generic_handle_irq(irq);
}
}
static void
sic_handle_irq(unsigned int irq, struct irq_desc *desc)
{
unsigned long status = readl(VA_SIC_BASE + SIC_IRQ_STATUS);
if (status == 0) {
do_bad_IRQ(irq, desc);
return;
}
do {
irq = ffs(status) - 1;
status &= ~(1 << irq);
irq += IRQ_SIC_START;
generic_handle_irq(irq);
} while (status);
}
static void s5pv310_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
{
u32 i;
struct irq_chip *chip = get_irq_chip(irq);
if (chip->ack)
chip->ack(irq);
for (i = 0; i <= 15; i++) {
if (irq == s5pv310_get_irq_nr(i)) {
generic_handle_irq(IRQ_EINT(i));
goto out;
}
}
do_bad_IRQ(irq, desc);
out:
chip->unmask(irq);
}
static void
sic_handle_irq(unsigned int irq, struct irqdesc *desc, struct pt_regs *regs)
{
unsigned long status = sic_readl(INTCP_VA_SIC_BASE + IRQ_STATUS);
if (status == 0) {
do_bad_IRQ(irq, desc, regs);
return;
}
do {
irq = ffs(status) - 1;
status &= ~(1 << irq);
irq += IRQ_SIC_START;
desc = irq_desc + irq;
desc->handle(irq, desc, regs);
} while (status);
}
/*
* Note that this 'irq' is the real repesentative irq for GPIO
*
* To reduce the register access, use the valid group cache.
* first check the valid groups. if failed, scan all groups fully.
*/
static void samsung_irq_gpio_handler(unsigned int irq, struct irq_desc *desc)
{
struct samsung_irq_gpio *gpio;
int group, n, offset;
int start, end, pend, mask, handled = 0, action = 0;
struct irq_chip *chip = get_irq_chip(irq);
gpio = get_irq_data(irq);
start = gpio->start;
end = gpio->nr_groups;
/* primary controller ack'ing */
if (chip->ack)
chip->ack(irq);
/* Check the valid group first */
for (group = 0; group <= end; group++) {
if (!test_bit(group, &gpio->valid_groups))
continue;
offset = REG_OFFSET(group); /* 4 bytes offset */
pend = __raw_readl(gpio->base + PEND_OFFSET + offset);
if (!pend)
continue;
mask = __raw_readl(gpio->base + MASK_OFFSET + offset);
pend &= ~mask;
if (!pend)
continue;
while (pend) {
n = fls(pend) - 1;
generic_handle_irq(IRQ_GPIO_GROUP(start + group) + n);
pend &= ~BIT(n);
++action;
}
handled = 1;
}
if (handled)
goto out;
/* Okay we can't find a proper handler. Scan fully */
for (group = 0; group <= end; group++) {
offset = REG_OFFSET(group); /* 4 bytes offset */
pend = __raw_readl(gpio->base + PEND_OFFSET + offset);
if (!pend)
continue;
mask = __raw_readl(gpio->base + MASK_OFFSET + offset);
pend &= ~mask;
while (pend) {
n = fls(pend) - 1;
generic_handle_irq(IRQ_GPIO_GROUP(start + group) + n);
pend &= ~BIT(n);
++action;
}
/* It found the valid group */
set_bit(group, &gpio->valid_groups);
}
out:
if (!action)
do_bad_IRQ(irq, desc);
/* primary controller unmasking */
chip->unmask(irq);
}
