phys_size_t initdram (int board_type) { volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; long int size9; upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint)); /* Refresh clock prescalar */ memctl->memc_mptpr = CONFIG_SYS_MPTPR ; memctl->memc_mar = 0x00000088; /* Map controller banks 1 to the SDRAM bank */ memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM; memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM; memctl->memc_mamr = CONFIG_SYS_MAMR_9COL & (~(MAMR_PTAE)); /* no refresh yet */ /*Disable Periodic timer A. */ udelay(200); /* perform SDRAM initializsation sequence */ memctl->memc_mcr = 0x80002236; /* SDRAM bank 0 - refresh twice */ udelay(1); memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */ /*Enable Periodic timer A */ udelay (1000); /* Check Bank 0 Memory Size * try 9 column mode */ size9 = dram_size (CONFIG_SYS_MAMR_9COL, SDRAM_BASE_PRELIM, SDRAM_MAX_SIZE); /* * Final mapping: */ memctl->memc_or1 = ((-size9) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM; udelay (1000); return (size9); }
phys_size_t initdram (int board_type) { volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; long int size10; upmconfig (UPMA, (uint *) sdram_table, sizeof (sdram_table) / sizeof (uint)); /* Refresh clock prescalar */ memctl->memc_mptpr = CONFIG_SYS_MPTPR; memctl->memc_mar = 0x00000000; /* Map controller banks 1 to the SDRAM bank */ memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM; memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM; memctl->memc_mamr = CONFIG_SYS_MAMR_10COL & (~(MAMR_PTAE)); /* no refresh yet */ udelay (200); /* perform SDRAM initializsation sequence */ memctl->memc_mcr = 0x80002230; /* SDRAM bank 0 - refresh twice */ udelay (1); memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */ udelay (1000); /* Check Bank 0 Memory Size * try 10 column mode */ size10 = dram_size (CONFIG_SYS_MAMR_10COL, SDRAM_BASE_PRELIM, SDRAM_MAX_SIZE); return (size10); }
int checkboard (void) { unsigned char *s, *e; unsigned char buf[64]; int i; i = getenv_r("serial#", buf, sizeof(buf)); s = (i>0) ? buf : NULL; #ifdef CONFIG_QS850 if (!s || strncmp(s, "QS850", 5)) { puts ("### No HW ID - assuming QS850"); #endif #ifdef CONFIG_QS823 if (!s || strncmp(s, "QS823", 5)) { puts ("### No HW ID - assuming QS823"); #endif } else { for (e=s; *e; ++e) { if (*e == ' ') break; } for ( ; s<e; ++s) { putc (*s); } } putc ('\n'); return (0); } /* ------------------------------------------------------------------------- */ /* SDRAM Mode Register Definitions */ /* Set SDRAM Burst Length to 4 (010) */ /* See Motorola MPC850 User Manual, Page 13-14 */ #define SDRAM_BURST_LENGTH (2) /* Set Wrap Type to Sequential (0) */ /* See Motorola MPC850 User Manual, Page 13-14 */ #define SDRAM_WRAP_TYPE (0 << 3) /* Set /CAS Latentcy to 2 clocks */ #define SDRAM_CAS_LATENTCY (2 << 4) /* The Mode Register value must be shifted left by 2, since it is */ /* placed on the address bus, and the 2 LSBs are ignored for 32-bit accesses */ #define SDRAM_MODE_REG ((SDRAM_BURST_LENGTH|SDRAM_WRAP_TYPE|SDRAM_CAS_LATENTCY) << 2) #define UPMA_RUN(loops,index) (0x80002000 + (loops<<8) + index) /* Please note a value of zero = 16 loops */ #define REFRESH_INIT_LOOPS (0) long int initdram (int board_type) { volatile immap_t *immap = (immap_t *)CFG_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; long int size; upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint)); /* * Prescaler for refresh */ memctl->memc_mptpr = CFG_MPTPR; /* * Map controller bank 1 to the SDRAM address */ memctl->memc_or1 = CFG_OR1; memctl->memc_br1 = CFG_BR1; udelay(1000); /* perform SDRAM initialization sequence */ memctl->memc_mamr = CFG_16M_MAMR; udelay(100); /* Program the SDRAM's Mode Register */ memctl->memc_mar = SDRAM_MODE_REG; /* Run the Prechard Pattern at 0x3C */ memctl->memc_mcr = UPMA_RUN(1,0x3c); udelay(1); /* Run the Refresh program residing at MAD index 0x30 */ /* This contains the CBR Refresh command with a loop */ /* The SDRAM must be refreshed at least 2 times */ /* Please note a value of zero = 16 loops */ memctl->memc_mcr = UPMA_RUN(REFRESH_INIT_LOOPS,0x30); udelay(1); /* Run the Exception program residing at MAD index 0x3E */ /* This contains the Write Mode Register command */ /* The Write Mode Register command uses the value written to MAR */ memctl->memc_mcr = UPMA_RUN(1,0x3e); udelay (1000); /* * Check for 32M SDRAM Memory Size */ size = dram_size(CFG_32M_MAMR|MAMR_PTAE, (ulong *)SDRAM_BASE, SDRAM_32M_MAX_SIZE); udelay (1000); /* * Check for 16M SDRAM Memory Size */ if (size != SDRAM_32M_MAX_SIZE) { size = dram_size(CFG_16M_MAMR|MAMR_PTAE, (ulong *)SDRAM_BASE, SDRAM_16M_MAX_SIZE); udelay (1000); } udelay(10000); return (size); } /* ------------------------------------------------------------------------- */ /* * Check memory range for valid RAM. A simple memory test determines * the actually available RAM size between addresses `base' and * `base + maxsize'. Some (not all) hardware errors are detected: * - short between address lines * - short between data lines */ static long int dram_size (long int mamr_value, long int *base, long int maxsize) { volatile immap_t *immap = (immap_t *)CFG_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; memctl->memc_mamr = mamr_value; return (get_ram_size(base, maxsize)); }
phys_size_t initdram (int board_type) { volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immr->im_memctl; /* volatile spc1920_pld_t *pld = (spc1920_pld_t *) CONFIG_SYS_SPC1920_PLD_BASE; */ long int size_b0; long int size8, size9; int i; /* * Configure UPMB for SDRAM */ upmconfig (UPMB, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint)); udelay(100); memctl->memc_mptpr = CONFIG_SYS_MPTPR; /* burst length=4, burst type=sequential, CAS latency=2 */ memctl->memc_mar = CONFIG_SYS_MAR; /* * Map controller bank 1 to the SDRAM bank at preliminary address. */ memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM; memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM; /* initialize memory address register */ memctl->memc_mbmr = CONFIG_SYS_MBMR_8COL; /* refresh not enabled yet */ /* mode initialization (offset 5) */ udelay (200); /* 0x80006105 */ memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS1 | MCR_MLCF (1) | MCR_MAD (0x05); /* run 2 refresh sequence with 4-beat refresh burst (offset 0x30) */ udelay (1); /* 0x80006130 */ memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS1 | MCR_MLCF (1) | MCR_MAD (0x30); udelay (1); /* 0x80006130 */ memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS1 | MCR_MLCF (1) | MCR_MAD (0x30); udelay (1); /* 0x80006106 */ memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS1 | MCR_MLCF (1) | MCR_MAD (0x06); memctl->memc_mbmr |= MBMR_PTBE; /* refresh enabled */ udelay (200); /* Need at least 10 DRAM accesses to stabilize */ for (i = 0; i < 10; ++i) { volatile unsigned long *addr = (volatile unsigned long *) CONFIG_SYS_SDRAM_BASE; unsigned long val; val = *(addr + i); *(addr + i) = val; } /* * Check Bank 0 Memory Size for re-configuration * * try 8 column mode */ size8 = dram_size (CONFIG_SYS_MBMR_8COL, (long *)CONFIG_SYS_SDRAM_BASE, SDRAM_MAX_SIZE); udelay (1000); /* * try 9 column mode */ size9 = dram_size (CONFIG_SYS_MBMR_9COL, (long *)CONFIG_SYS_SDRAM_BASE, SDRAM_MAX_SIZE); if (size8 < size9) { /* leave configuration at 9 columns */ size_b0 = size9; memctl->memc_mbmr = CONFIG_SYS_MBMR_9COL | MBMR_PTBE; udelay (500); } else { /* back to 8 columns */ size_b0 = size8; memctl->memc_mbmr = CONFIG_SYS_MBMR_8COL | MBMR_PTBE; udelay (500); } /* * Final mapping: */ memctl->memc_or1 = ((-size_b0) & 0xFFFF0000) | OR_CSNT_SAM | OR_G5LS | SDRAM_TIMING; memctl->memc_br1 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMB | BR_V; udelay (1000); /* initalize the DSP Host Port Interface */ hpi_init(); /* FRAM Setup */ memctl->memc_or4 = CONFIG_SYS_OR4; memctl->memc_br4 = CONFIG_SYS_BR4; udelay(1000); return (size_b0); }
phys_size_t initdram (int board_type) { volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; long int size8, size9; long int size_b0 = 0; unsigned long reg; upmconfig (UPMA, (uint *) sdram_table, sizeof (sdram_table) / sizeof (uint)); /* * Preliminary prescaler for refresh (depends on number of * banks): This value is selected for four cycles every 62.4 us * with two SDRAM banks or four cycles every 31.2 us with one * bank. It will be adjusted after memory sizing. */ memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_8K; memctl->memc_mar = 0x00000088; /* * Map controller bank 2 to the SDRAM bank at * preliminary address - these have to be modified after the * SDRAM size has been determined. */ memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM; memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM; memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */ udelay (200); /* perform SDRAM initializsation sequence */ memctl->memc_mcr = 0x80004105; /* SDRAM bank 0 */ udelay (200); memctl->memc_mcr = 0x80004230; /* SDRAM bank 0 - execute twice */ udelay (200); memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */ udelay (1000); /* * Check Bank 2 Memory Size for re-configuration * * try 8 column mode */ size8 = dram_size (CONFIG_SYS_MAMR_8COL, (long *) SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE); udelay (1000); /* * try 9 column mode */ size9 = dram_size (CONFIG_SYS_MAMR_9COL, (long *) SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE); if (size8 < size9) { /* leave configuration at 9 columns */ size_b0 = size9; /* debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20); */ } else { /* back to 8 columns */ size_b0 = size8; memctl->memc_mamr = CONFIG_SYS_MAMR_8COL; udelay (500); /* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */ } udelay (1000); /* * Adjust refresh rate depending on SDRAM type, both banks * For types > 128 MBit leave it at the current (fast) rate */ if ((size_b0 < 0x02000000)) { /* reduce to 15.6 us (62.4 us / quad) */ memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K; udelay (1000); } /* * Final mapping */ memctl->memc_or1 = ((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM; memctl->memc_br1 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; /* adjust refresh rate depending on SDRAM type, one bank */ reg = memctl->memc_mptpr; reg >>= 1; /* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */ memctl->memc_mptpr = reg; udelay (10000); #ifdef CONFIG_CAN_DRIVER /* Initialize OR3 / BR3 */ memctl->memc_or3 = CONFIG_SYS_OR3_CAN; /* switch GPLB_5 to GPLA_5 */ memctl->memc_br3 = CONFIG_SYS_BR3_CAN; /* Initialize MBMR */ memctl->memc_mbmr = MBMR_GPL_B4DIS; /* GPL_B4 works as UPWAITB */ /* Initialize UPMB for CAN: single read */ memctl->memc_mdr = 0xFFFFC004; memctl->memc_mcr = 0x0100 | UPMB; memctl->memc_mdr = 0x0FFFD004; memctl->memc_mcr = 0x0101 | UPMB; memctl->memc_mdr = 0x0FFFC000; memctl->memc_mcr = 0x0102 | UPMB; memctl->memc_mdr = 0x3FFFC004; memctl->memc_mcr = 0x0103 | UPMB; memctl->memc_mdr = 0xFFFFDC05; memctl->memc_mcr = 0x0104 | UPMB; /* Initialize UPMB for CAN: single write */ memctl->memc_mdr = 0xFFFCC004; memctl->memc_mcr = 0x0118 | UPMB; memctl->memc_mdr = 0xCFFCD004; memctl->memc_mcr = 0x0119 | UPMB; memctl->memc_mdr = 0x0FFCC000; memctl->memc_mcr = 0x011A | UPMB; memctl->memc_mdr = 0x7FFCC004; memctl->memc_mcr = 0x011B | UPMB; memctl->memc_mdr = 0xFFFDCC05; memctl->memc_mcr = 0x011C | UPMB; #endif return (size_b0); }
long int initdram (int board_type) { volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; long int size; ulong refresh_val; upmconfig (UPMA, (uint *) sdram_table, sizeof (sdram_table) / sizeof (uint)); /* * Preliminary prescaler for refresh */ if (ip860_get_clk_freq() == 50000000) { memctl->memc_mptpr = 0x0400; refresh_val = 0xC3000000; } else { memctl->memc_mptpr = 0x0200; refresh_val = 0x9C000000; } memctl->memc_mar = 0x00000088; /* * Map controller banks 2 to the SDRAM address */ memctl->memc_or2 = CFG_OR2; memctl->memc_br2 = CFG_BR2; /* IP860 boards have only one bank SDRAM */ udelay (200); /* perform SDRAM initializsation sequence */ memctl->memc_mamr = 0x00804114 | refresh_val; memctl->memc_mcr = 0x80004105; /* run precharge pattern from loc 5 */ udelay(1); memctl->memc_mamr = 0x00804118 | refresh_val; memctl->memc_mcr = 0x80004130; /* run refresh pattern 8 times */ udelay (1000); /* * Check SDRAM Memory Size */ if (ip860_get_dram_size() == 16) size = dram_size (refresh_val | 0x00804114, SDRAM_BASE, SDRAM_MAX_SIZE); else size = dram_size (refresh_val | 0x00906114, SDRAM_BASE, SDRAM_MAX_SIZE); udelay (1000); memctl->memc_or2 = ((-size) & 0xFFFF0000) | SDRAM_TIMING; memctl->memc_br2 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; udelay (10000); /* * Also, map other memory to correct position */ #if (defined(CFG_OR1) && defined(CFG_BR1_PRELIM)) memctl->memc_or1 = CFG_OR1; memctl->memc_br1 = CFG_BR1; #endif #if defined(CFG_OR3) && defined(CFG_BR3) memctl->memc_or3 = CFG_OR3; memctl->memc_br3 = CFG_BR3; #endif #if defined(CFG_OR4) && defined(CFG_BR4) memctl->memc_or4 = CFG_OR4; memctl->memc_br4 = CFG_BR4; #endif #if defined(CFG_OR5) && defined(CFG_BR5) memctl->memc_or5 = CFG_OR5; memctl->memc_br5 = CFG_BR5; #endif #if defined(CFG_OR6) && defined(CFG_BR6) memctl->memc_or6 = CFG_OR6; memctl->memc_br6 = CFG_BR6; #endif #if defined(CFG_OR7) && defined(CFG_BR7) memctl->memc_or7 = CFG_OR7; memctl->memc_br7 = CFG_BR7; #endif return (size); }
phys_size_t initdram (int board_type) { volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immr->im_memctl; long int size_b0, reg; int i; /* * Configure UPMA for SDRAM */ upmconfig (UPMA, (uint *) sdram_table, sizeof (sdram_table) / sizeof (uint)); memctl->memc_mptpr = CONFIG_SYS_MPTPR; /* burst length=4, burst type=sequential, CAS latency=2 */ memctl->memc_mar = 0x00000088; /* * Map controller bank 2 to the SDRAM bank at preliminary address. */ #if PCU_E_WITH_SWAPPED_CS /* XXX */ memctl->memc_or5 = CONFIG_SYS_OR5_PRELIM; memctl->memc_br5 = CONFIG_SYS_BR5_PRELIM; #else /* XXX */ memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM; memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM; #endif /* XXX */ /* initialize memory address register */ memctl->memc_mamr = CONFIG_SYS_MAMR; /* refresh not enabled yet */ /* mode initialization (offset 5) */ #if PCU_E_WITH_SWAPPED_CS /* XXX */ udelay (200); /* 0x8000A105 */ memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS5 | MCR_MLCF (1) | MCR_MAD (0x05); #else /* XXX */ udelay (200); /* 0x80004105 */ memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS2 | MCR_MLCF (1) | MCR_MAD (0x05); #endif /* XXX */ /* run 2 refresh sequence with 4-beat refresh burst (offset 0x30) */ #if PCU_E_WITH_SWAPPED_CS /* XXX */ udelay (1); /* 0x8000A830 */ memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS5 | MCR_MLCF (8) | MCR_MAD (0x30); #else /* XXX */ udelay (1); /* 0x80004830 */ memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS2 | MCR_MLCF (8) | MCR_MAD (0x30); #endif /* XXX */ #if PCU_E_WITH_SWAPPED_CS /* XXX */ udelay (1); /* 0x8000A106 */ memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS5 | MCR_MLCF (1) | MCR_MAD (0x06); #else /* XXX */ udelay (1); /* 0x80004106 */ memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS2 | MCR_MLCF (1) | MCR_MAD (0x06); #endif /* XXX */ reg = memctl->memc_mamr; reg &= ~MAMR_TLFA_MSK; /* switch timer loop ... */ reg |= MAMR_TLFA_4X; /* ... to 4x */ reg |= MAMR_PTAE; /* enable refresh */ memctl->memc_mamr = reg; udelay (200); /* Need at least 10 DRAM accesses to stabilize */ for (i = 0; i < 10; ++i) { #if PCU_E_WITH_SWAPPED_CS /* XXX */ volatile unsigned long *addr = (volatile unsigned long *) SDRAM_BASE5_PRELIM; #else /* XXX */ volatile unsigned long *addr = (volatile unsigned long *) SDRAM_BASE2_PRELIM; #endif /* XXX */ unsigned long val; val = *(addr + i); *(addr + i) = val; } /* * Check Bank 0 Memory Size for re-configuration */ #if PCU_E_WITH_SWAPPED_CS /* XXX */ size_b0 = dram_size (CONFIG_SYS_MAMR, (long *) SDRAM_BASE5_PRELIM, SDRAM_MAX_SIZE); #else /* XXX */ size_b0 = dram_size (CONFIG_SYS_MAMR, (long *) SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE); #endif /* XXX */ memctl->memc_mamr = CONFIG_SYS_MAMR | MAMR_PTAE; /* * Final mapping: */ #if PCU_E_WITH_SWAPPED_CS /* XXX */ memctl->memc_or5 = ((-size_b0) & 0xFFFF0000) | SDRAM_TIMING; memctl->memc_br5 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; #else /* XXX */ memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | SDRAM_TIMING; memctl->memc_br2 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; #endif /* XXX */ udelay (1000); /* * Configure UPMB for PUMA */ upmconfig (UPMB, (uint *) puma_table, sizeof (puma_table) / sizeof (uint)); return (size_b0); }
phys_size_t initdram (int board_type) { volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; long int size; upmconfig(UPMB, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint)); /* * Prescaler for refresh */ memctl->memc_mptpr = 0x0400; /* * Map controller bank 2 to the SDRAM address */ memctl->memc_or2 = CONFIG_SYS_OR2; memctl->memc_br2 = CONFIG_SYS_BR2; udelay(200); /* perform SDRAM initialization sequence */ memctl->memc_mbmr = CONFIG_SYS_16M_MBMR; udelay(100); memctl->memc_mar = 0x00000088; memctl->memc_mcr = 0x80804105; /* run precharge pattern */ udelay(1); /* Run two refresh cycles on SDRAM */ memctl->memc_mbmr = 0x18802118; memctl->memc_mcr = 0x80804130; memctl->memc_mbmr = 0x18802114; memctl->memc_mcr = 0x80804106; udelay (1000); #if 0 /* * Check for 64M SDRAM Memory Size */ size = dram_size (CONFIG_SYS_64M_MBMR, (ulong *)SDRAM_BASE, SDRAM_64M_MAX_SIZE); udelay (1000); /* * Check for 16M SDRAM Memory Size */ if (size != SDRAM_64M_MAX_SIZE) { #endif size = dram_size (CONFIG_SYS_16M_MBMR, (long *)SDRAM_BASE, SDRAM_16M_MAX_SIZE); udelay (1000); #if 0 } memctl->memc_or2 = ((-size) & 0xFFFF0000) | SDRAM_TIMING; #endif udelay(10000); #if 0 /* * Also, map other memory to correct position */ /* * Map the 8M Intel Flash device to chip select 1 */ memctl->memc_or1 = CONFIG_SYS_OR1; memctl->memc_br1 = CONFIG_SYS_BR1; /* * Map 64K NVRAM, Sipex Device, NAND Ctl Reg, and LED Ctl Reg * to chip select 3 */ memctl->memc_or3 = CONFIG_SYS_OR3; memctl->memc_br3 = CONFIG_SYS_BR3; /* * Map chip selects 4, 5, 6, & 7 for external expansion connector */ memctl->memc_or4 = CONFIG_SYS_OR4; memctl->memc_br4 = CONFIG_SYS_BR4; memctl->memc_or5 = CONFIG_SYS_OR5; memctl->memc_br5 = CONFIG_SYS_BR5; memctl->memc_or6 = CONFIG_SYS_OR6; memctl->memc_br6 = CONFIG_SYS_BR6; memctl->memc_or7 = CONFIG_SYS_OR7; memctl->memc_br7 = CONFIG_SYS_BR7; #endif return (size); }
phys_size_t initdram (int board_type) { volatile immap_t *immr = (immap_t *) CFG_IMMR; volatile memctl8xx_t *memctl = &immr->im_memctl; long int size_b0; /* enable SDRAM clock ("switch on" SDRAM) */ immr->im_cpm.cp_pbpar &= ~(CFG_PB_SDRAM_CLKE); /* GPIO */ immr->im_cpm.cp_pbodr &= ~(CFG_PB_SDRAM_CLKE); /* active output */ immr->im_cpm.cp_pbdir |= CFG_PB_SDRAM_CLKE; /* output */ immr->im_cpm.cp_pbdat |= CFG_PB_SDRAM_CLKE; /* assert SDRAM CLKE */ udelay (1); /* * Map controller bank 1 for ELIC SACCO */ memctl->memc_or1 = CFG_OR1; memctl->memc_br1 = CFG_BR1; /* * Map controller bank 2 for ELIC EPIC */ memctl->memc_or2 = CFG_OR2; memctl->memc_br2 = CFG_BR2; /* * Configure UPMA for SHARC */ upmconfig (UPMA, (uint *) sharc_table, sizeof (sharc_table) / sizeof (uint)); #if defined(CONFIG_IVML24) /* * Map controller bank 4 for HDLC Address space */ memctl->memc_or4 = CFG_OR4; memctl->memc_br4 = CFG_BR4; #endif /* * Map controller bank 5 for SHARC */ memctl->memc_or5 = CFG_OR5; memctl->memc_br5 = CFG_BR5; memctl->memc_mamr = 0x00001000; /* * Configure UPMB for SDRAM */ upmconfig (UPMB, (uint *) sdram_table, sizeof (sdram_table) / sizeof (uint)); memctl->memc_mptpr = CFG_MPTPR_1BK_8K; memctl->memc_mar = 0x00000088; /* * Map controller bank 3 to the SDRAM bank at preliminary address. */ memctl->memc_or3 = CFG_OR3_PRELIM; memctl->memc_br3 = CFG_BR3_PRELIM; memctl->memc_mbmr = CFG_MBMR_8COL; /* refresh not enabled yet */ udelay (200); memctl->memc_mcr = 0x80806105; /* precharge */ udelay (1); memctl->memc_mcr = 0x80806106; /* load mode register */ udelay (1); memctl->memc_mcr = 0x80806130; /* autorefresh */ udelay (1); memctl->memc_mcr = 0x80806130; /* autorefresh */ udelay (1); memctl->memc_mcr = 0x80806130; /* autorefresh */ udelay (1); memctl->memc_mcr = 0x80806130; /* autorefresh */ udelay (1); memctl->memc_mcr = 0x80806130; /* autorefresh */ udelay (1); memctl->memc_mcr = 0x80806130; /* autorefresh */ udelay (1); memctl->memc_mcr = 0x80806130; /* autorefresh */ udelay (1); memctl->memc_mcr = 0x80806130; /* autorefresh */ memctl->memc_mbmr |= MBMR_PTBE; /* refresh enabled */ /* * Check Bank 0 Memory Size for re-configuration */ size_b0 = dram_size (CFG_MBMR_8COL, (long *) SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE); memctl->memc_mbmr = CFG_MBMR_8COL | MBMR_PTBE; return (size_b0); }
phys_size_t initdram (int board_type) { return dram_size (board_type); }
phys_size_t initdram (int board_type) { volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; long int size_b0; #if 0 /* * Map controller bank 2 to the SRAM bank at preliminary address. */ memctl->memc_or2 = CONFIG_SYS_OR2; memctl->memc_br2 = CONFIG_SYS_BR2; #endif /* * Map controller bank 4 to the PER8 bank. */ memctl->memc_or4 = CONFIG_SYS_OR4; memctl->memc_br4 = CONFIG_SYS_BR4; #if 0 /* Configure SHARC at UMA */ upmconfig (UPMA, (uint *) sharc_table, sizeof (sharc_table) / sizeof (uint)); /* Map controller bank 5 to the SHARC */ memctl->memc_or5 = CONFIG_SYS_OR5; memctl->memc_br5 = CONFIG_SYS_BR5; #endif memctl->memc_mamr = 0x00001000; /* Configure SDRAM at UMB */ upmconfig (UPMB, (uint *) sdram_table, sizeof (sdram_table) / sizeof (uint)); memctl->memc_mptpr = CONFIG_SYS_MPTPR_1BK_8K; memctl->memc_mar = 0x00000088; /* * Map controller bank 3 to the SDRAM bank at preliminary address. */ memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM; memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM; memctl->memc_mbmr = CONFIG_SYS_MBMR_8COL; /* refresh not enabled yet */ udelay (200); memctl->memc_mcr = 0x80806105; udelay (1); memctl->memc_mcr = 0x80806130; udelay (1); memctl->memc_mcr = 0x80806130; udelay (1); memctl->memc_mcr = 0x80806106; memctl->memc_mbmr |= MBMR_PTBE; /* refresh enabled */ /* * Check Bank 0 Memory Size for re-configuration */ size_b0 = dram_size (CONFIG_SYS_MBMR_8COL, SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE); memctl->memc_mbmr = CONFIG_SYS_MBMR_8COL | MBMR_PTBE; return (size_b0); }
phys_size_t initdram (int board_type) { volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; long int size_b0, size_b1, size8, size9; upmconfig (UPMA, (uint *) sdram_table, sizeof (sdram_table) / sizeof (uint)); /* * Preliminary prescaler for refresh (depends on number of * banks): This value is selected for four cycles every 62.4 us * with two SDRAM banks or four cycles every 31.2 us with one * bank. It will be adjusted after memory sizing. */ memctl->memc_mptpr = CONFIG_SYS_MPTPR_1BK_4K; /* MPTPR_PTP_DIV32 0x0200 */ /* A3(SDRAM)=0 => Bursttype = Sequential * A2-A0(SDRAM)=010 => Burst length = 4 * A4-A6(SDRAM)=010 => CasLat=2 */ memctl->memc_mar = 0x00000088; /* * Map controller banks 2 and 3 to the SDRAM banks 2 and 3 at * preliminary addresses - these have to be modified after the * SDRAM size has been determined. */ memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM; memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM; if (board_type == 0) { /* "L" type boards have only one bank SDRAM */ memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM; memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM; } memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */ udelay (200); /* perform SDRAM initializsation sequence */ memctl->memc_mcr = 0x80004128; /* SDRAM bank 0 (CS2) - Init Part 1 */ memctl->memc_mcr = 0x80004734; /* SDRAM bank 0 (CS2) - Init Part 2 */ udelay (1); if (board_type == 0) { /* "L" type boards have only one bank SDRAM */ memctl->memc_mcr = 0x80006128; /* SDRAM bank 1 (CS3) - Init Part 1 */ memctl->memc_mcr = 0x80006734; /* SDRAM bank 1 (CS3) - Init Part 2 */ udelay (1); } memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */ udelay (1000); /* * Check Bank 0 Memory Size for re-configuration * * try 8 column mode */ size8 = dram_size (CONFIG_SYS_MAMR_8COL, (long *) SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE); udelay (1000); /* * try 9 column mode */ size9 = dram_size (CONFIG_SYS_MAMR_9COL, (long *) SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE); if (size8 < size9) { /* leave configuration at 9 columns */ size_b0 = size9; /* debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20); */ } else { /* back to 8 columns */ size_b0 = size8; memctl->memc_mamr = CONFIG_SYS_MAMR_8COL; udelay (500); /* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */ } if (board_type == 0) { /* "L" type boards have only one bank SDRAM */ /* * Check Bank 1 Memory Size * use current column settings * [9 column SDRAM may also be used in 8 column mode, * but then only half the real size will be used.] */ size_b1 = dram_size (memctl->memc_mamr, (long *) SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE); /* debug ("SDRAM Bank 1: %ld MB\n", size8 >> 20); */ } else { size_b1 = 0; } udelay (1000); /* * Adjust refresh rate depending on SDRAM type, both banks * For types > 128 MBit leave it at the current (fast) rate */ if ((size_b0 < 0x02000000) && (size_b1 < 0x02000000)) { /* reduce to 15.6 us (62.4 us / quad) */ memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K; /*DIV16 */ udelay (1000); } /* * Final mapping: map bigger bank first */ if (size_b1 > size_b0) { /* SDRAM Bank 1 is bigger - map first */ memctl->memc_or3 = ((-size_b1) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM; memctl->memc_br3 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; if (size_b0 > 0) { /* * Position Bank 0 immediately above Bank 1 */ memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM; memctl->memc_br2 = ((CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V) + size_b1; } else { unsigned long reg; /* * No bank 0 * * invalidate bank */ memctl->memc_br2 = 0; /* adjust refresh rate depending on SDRAM type, one bank */ reg = memctl->memc_mptpr; reg >>= 1; /* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */ memctl->memc_mptpr = reg; } } else { /* SDRAM Bank 0 is bigger - map first */
phys_size_t initdram (int board_type) { volatile immap_t *im = (immap_t *) CFG_IMMR; volatile memctl8xx_t *memctl = &im->im_memctl; long int size_b0, size_b1, size8; /* Enable SDRAM */ /* Configuring PA7 for general purpouse output pin */ im->im_ioport.iop_papar &= ~CFG_PA7; /* 0 = general purpouse */ im->im_ioport.iop_padir |= CFG_PA7; /* 1 = output */ /* Enable SDRAM - PA7 = 1 */ im->im_ioport.iop_padat |= CFG_PA7; /* value of PA7 */ /* * Preliminary prescaler for refresh (depends on number of * banks): This value is selected for four cycles every 62.4 us * with two SDRAM banks or four cycles every 31.2 us with one * bank. It will be adjusted after memory sizing. */ memctl->memc_mptpr = CFG_MPTPR_2BK_4K; memctl->memc_mbmr = CFG_MBMR_8COL; upmconfig (UPMB, (uint *) sdram_table, sizeof (sdram_table) / sizeof (uint)); /* * Map controller banks 1 and 2 to the SDRAM banks 1 and 2 at * preliminary addresses - these have to be modified after the * SDRAM size has been determined. */ memctl->memc_or1 = 0xF0000000 | CFG_OR_TIMING_SDRAM; memctl->memc_br1 = ((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_V); memctl->memc_or2 = 0xF0000000 | CFG_OR_TIMING_SDRAM; memctl->memc_br2 = ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_V); /* perform SDRAM initialization sequence */ memctl->memc_mar = 0x00000088; memctl->memc_mcr = 0x80802105; /* SDRAM bank 0 */ memctl->memc_mcr = 0x80804105; /* SDRAM bank 1 */ /* Execute refresh 8 times */ memctl->memc_mbmr = (CFG_MBMR_8COL & ~MBMR_TLFB_MSK) | MBMR_TLFB_8X; memctl->memc_mcr = 0x80802130; /* SDRAM bank 0 - execute twice */ memctl->memc_mcr = 0x80804130; /* SDRAM bank 1 - execute twice */ /* Execute refresh 4 times */ memctl->memc_mbmr = CFG_MBMR_8COL; /* * Check Bank 0 Memory Size for re-configuration * * try 8 column mode */ #if 0 PrintState (); #endif /* printf ("\nChecking bank1..."); */ size8 = dram_size (CFG_MBMR_8COL, (long *) SDRAM_BASE1_PRELIM, SDRAM_MAX_SIZE); size_b0 = size8; /* printf ("\nChecking bank2..."); */ size_b1 = dram_size (memctl->memc_mbmr, (long *) SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE); /* * Final mapping: map bigger bank first */ memctl->memc_or1 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM; memctl->memc_br1 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMB | BR_V; if (size_b1 > 0) { /* * Position Bank 1 immediately above Bank 0 */ memctl->memc_or2 = ((-size_b1) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM; memctl->memc_br2 = ((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMB | BR_V) + (size_b0 & BR_BA_MSK); } else { /* * No bank 1 * * invalidate bank */ memctl->memc_br2 = 0; /* adjust refresh rate depending on SDRAM type, one bank */ memctl->memc_mptpr = CFG_MPTPR_1BK_4K; } /* If no memory detected, disable SDRAM */ if ((size_b0 + size_b1) == 0) { printf ("disabling SDRAM!\n"); /* Disable SDRAM - PA7 = 1 */ im->im_ioport.iop_padat &= ~CFG_PA7; /* value of PA7 */ } /* else */ /* printf("done! (%08lx)\n", size_b0 + size_b1); */ #if 0 PrintState (); #endif return (size_b0 + size_b1); }
long int initdram (int board_type) { volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; unsigned long reg; long int size8, size9; long int size = 0; upmconfig (UPMA, (uint *)sdram_table, sizeof(sdram_table) / sizeof(uint)); /* * Preliminary prescaler for refresh (depends on number of * banks): This value is selected for four cycles every 62.4 us * with two SDRAM banks or four cycles every 31.2 us with one * bank. It will be adjusted after memory sizing. */ memctl->memc_mptpr = CFG_MPTPR_2BK_8K; memctl->memc_mar = 0x00000088; /* * Map controller bank 1 the SDRAM bank 2 at physical address 0. */ memctl->memc_or1 = CFG_OR2_PRELIM; memctl->memc_br1 = CFG_BR2_PRELIM; memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */ udelay (200); /* perform SDRAM initializsation sequence */ memctl->memc_mcr = 0x80002105; /* SDRAM bank 0 */ udelay (1); memctl->memc_mcr = 0x80002230; /* SDRAM bank 0 - execute twice */ udelay (1); memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */ udelay (1000); /* * Check Bank 0 Memory Size * * try 8 column mode */ size8 = dram_size (CFG_MAMR_8COL, (ulong *)SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE); udelay (1000); /* * try 9 column mode */ size9 = dram_size (CFG_MAMR_9COL, (ulong *) SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE); if (size8 < size9) { /* leave configuration at 9 columns */ size = size9; /* debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20); */ } else { /* back to 8 columns */ size = size8; memctl->memc_mamr = CFG_MAMR_8COL; udelay (500); /* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */ } udelay (1000); /* * Adjust refresh rate depending on SDRAM type * For types > 128 MBit leave it at the current (fast) rate */ if (size < 0x02000000) { /* reduce to 15.6 us (62.4 us / quad) */ memctl->memc_mptpr = CFG_MPTPR_2BK_4K; udelay (1000); } /* * Final mapping */ memctl->memc_or1 = ((-size) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM; memctl->memc_br1 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; /* * No bank 1 * * invalidate bank */ memctl->memc_br3 = 0; /* adjust refresh rate depending on SDRAM type, one bank */ reg = memctl->memc_mptpr; reg >>= 1; /* reduce to CFG_MPTPR_1BK_8K / _4K */ memctl->memc_mptpr = reg; udelay (10000); return (size); }
long int initdram (int board_type) { volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; volatile iop8xx_t *iop = &immap->im_ioport; volatile fec_t *fecp = &immap->im_cpm.cp_fec; long int size; upmconfig (UPMA, (uint *) sdram_table, sizeof (sdram_table) / sizeof (uint)); /* * Preliminary prescaler for refresh (depends on number of * banks): This value is selected for four cycles every 62.4 us * with two SDRAM banks or four cycles every 31.2 us with one * bank. It will be adjusted after memory sizing. */ memctl->memc_mptpr = CFG_MPTPR; memctl->memc_mar = 0x00000088; /* * Map controller banks 2 and 3 to the SDRAM banks 2 and 3 at * preliminary addresses - these have to be modified after the * SDRAM size has been determined. */ memctl->memc_or2 = CFG_OR2_PRELIM; memctl->memc_br2 = CFG_BR2_PRELIM; memctl->memc_mamr = CFG_MAMR & (~(MAMR_PTAE)); /* no refresh yet */ udelay (200); /* perform SDRAM initializsation sequence */ memctl->memc_mcr = 0x80004105; /* SDRAM bank 0 */ udelay (1); memctl->memc_mcr = 0x80004230; /* SDRAM bank 0 - execute twice */ udelay (1); memctl->memc_mcr = 0x80004105; /* SDRAM precharge */ udelay (1); memctl->memc_mcr = 0x80004030; /* SDRAM 16x autorefresh */ udelay (1); memctl->memc_mcr = 0x80004138; /* SDRAM upload parameters */ udelay (1); memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */ udelay (1000); /* * Check Bank 0 Memory Size for re-configuration * */ size = dram_size (CFG_MAMR, (ulong *) SDRAM_BASE_PRELIM, SDRAM_MAX_SIZE); udelay (1000); memctl->memc_mamr = CFG_MAMR; udelay (1000); /* * Final mapping */ memctl->memc_or2 = ((-size) & 0xFFFF0000) | CFG_OR2_PRELIM; memctl->memc_br2 = ((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V); udelay (10000); /* prepare pin multiplexing for fast ethernet */ atmLoad (); fecp->fec_ecntrl = 0x00000004; /* rev D3 pinmux SET */ iop->iop_pdpar |= 0x0080; /* set pin as MII_clock */ return (size); }
phys_size_t initdram (int board_type) { volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; long int size; upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint)); /* * Prescaler for refresh */ memctl->memc_mptpr = CONFIG_SYS_MPTPR; /* * Map controller bank 1 to the SDRAM address */ memctl->memc_or1 = CONFIG_SYS_OR1; memctl->memc_br1 = CONFIG_SYS_BR1; udelay(1000); /* perform SDRAM initialization sequence */ memctl->memc_mamr = CONFIG_SYS_16M_MAMR; udelay(100); /* Program the SDRAM's Mode Register */ memctl->memc_mar = SDRAM_MODE_REG; /* Run the Prechard Pattern at 0x3C */ memctl->memc_mcr = UPMA_RUN(1,0x3c); udelay(1); /* Run the Refresh program residing at MAD index 0x30 */ /* This contains the CBR Refresh command with a loop */ /* The SDRAM must be refreshed at least 2 times */ /* Please note a value of zero = 16 loops */ memctl->memc_mcr = UPMA_RUN(REFRESH_INIT_LOOPS,0x30); udelay(1); /* Run the Exception program residing at MAD index 0x3E */ /* This contains the Write Mode Register command */ /* The Write Mode Register command uses the value written to MAR */ memctl->memc_mcr = UPMA_RUN(1,0x3e); udelay (1000); /* * Check for 32M SDRAM Memory Size */ size = dram_size(CONFIG_SYS_32M_MAMR|MAMR_PTAE, (long *)SDRAM_BASE, SDRAM_32M_MAX_SIZE); udelay (1000); /* * Check for 16M SDRAM Memory Size */ if (size != SDRAM_32M_MAX_SIZE) { size = dram_size(CONFIG_SYS_16M_MAMR|MAMR_PTAE, (long *)SDRAM_BASE, SDRAM_16M_MAX_SIZE); udelay (1000); } udelay(10000); return (size); }
long int initdram (int board_type) { volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; long int size8, size9; long int size_b0 = 0; /* * This sequence initializes SDRAM chips on ELPT860 board */ upmconfig (UPMA, (uint *) init_sdram_table, sizeof (init_sdram_table) / sizeof (uint)); memctl->memc_mptpr = 0x0200; memctl->memc_mamr = 0x18002111; memctl->memc_mar = 0x00000088; memctl->memc_mcr = 0x80002000; /* CS1: SDRAM bank 0 */ upmconfig (UPMA, (uint *) sdram_table, sizeof (sdram_table) / sizeof (uint)); /* * Preliminary prescaler for refresh (depends on number of * banks): This value is selected for four cycles every 62.4 us * with two SDRAM banks or four cycles every 31.2 us with one * bank. It will be adjusted after memory sizing. */ memctl->memc_mptpr = CFG_MPTPR_2BK_8K; /* * The following value is used as an address (i.e. opcode) for * the LOAD MODE REGISTER COMMAND during SDRAM initialisation. If * the port size is 32bit the SDRAM does NOT "see" the lower two * address lines, i.e. mar=0x00000088 -> opcode=0x00000022 for * MICRON SDRAMs: * -> 0 00 010 0 010 * | | | | +- Burst Length = 4 * | | | +----- Burst Type = Sequential * | | +------- CAS Latency = 2 * | +----------- Operating Mode = Standard * +-------------- Write Burst Mode = Programmed Burst Length */ memctl->memc_mar = 0x00000088; /* * Map controller banks 2 and 3 to the SDRAM banks 2 and 3 at * preliminary addresses - these have to be modified after the * SDRAM size has been determined. */ memctl->memc_or1 = CFG_OR1_PRELIM; memctl->memc_br1 = CFG_BR1_PRELIM; memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */ udelay (200); /* perform SDRAM initializsation sequence */ memctl->memc_mcr = 0x80002105; /* CS1: SDRAM bank 0 */ udelay (1); memctl->memc_mcr = 0x80002230; /* CS1: SDRAM bank 0 - execute twice */ udelay (1); memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */ udelay (1000); /* * Check Bank 0 Memory Size for re-configuration * * try 8 column mode */ size8 = dram_size (CFG_MAMR_8COL, (ulong *) SDRAM_BASE1_PRELIM, SDRAM_MAX_SIZE); udelay (1000); /* * try 9 column mode */ size9 = dram_size (CFG_MAMR_9COL, (ulong *) SDRAM_BASE1_PRELIM, SDRAM_MAX_SIZE); if (size8 < size9) { /* leave configuration at 9 columns */ size_b0 = size9; /* debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20); */ } else { /* back to 8 columns */ size_b0 = size8; memctl->memc_mamr = CFG_MAMR_8COL; udelay (500); /* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */ } udelay (1000); /* * Adjust refresh rate depending on SDRAM type, both banks * For types > 128 MBit leave it at the current (fast) rate */ if (size_b0 < 0x02000000) { /* reduce to 15.6 us (62.4 us / quad) */ memctl->memc_mptpr = CFG_MPTPR_2BK_4K; udelay (1000); } /* * Final mapping: map bigger bank first */ memctl->memc_or1 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM; memctl->memc_br1 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; { unsigned long reg; /* adjust refresh rate depending on SDRAM type, one bank */ reg = memctl->memc_mptpr; reg >>= 1; /* reduce to CFG_MPTPR_1BK_8K / _4K */ memctl->memc_mptpr = reg; } udelay (10000); return (size_b0); }
long int initdram (int board_type) { return dram_size (board_type); }
long int initdram (int board_type) { volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; long int size_b0, size8, size9; upmconfig (UPMA, (uint *) sdram_table, sizeof (sdram_table) / sizeof (uint)); /* * 1 Bank of 64Mbit x 2 devices */ memctl->memc_mptpr = CFG_MPTPR_1BK_4K; memctl->memc_mar = 0x00000088; /* * Map controller SDRAM bank 0 */ memctl->memc_or4 = CFG_OR4_PRELIM; memctl->memc_br4 = CFG_BR4_PRELIM; memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */ udelay (200); /* * Perform SDRAM initializsation sequence */ memctl->memc_mcr = 0x80008105; /* SDRAM bank 0 */ udelay (1); memctl->memc_mamr = (CFG_MAMR_8COL & ~(MAMR_TLFA_MSK)) | MAMR_TLFA_8X; udelay (200); memctl->memc_mcr = 0x80008130; /* SDRAM bank 0 - execute twice */ udelay (1); memctl->memc_mamr = (CFG_MAMR_8COL & ~(MAMR_TLFA_MSK)) | MAMR_TLFA_4X; udelay (200); memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */ udelay (1000); /* * Preliminary prescaler for refresh (depends on number of * banks): This value is selected for four cycles every 62.4 us * with two SDRAM banks or four cycles every 31.2 us with one * bank. It will be adjusted after memory sizing. */ memctl->memc_mptpr = CFG_MPTPR_2BK_4K; /* 16: but should be: CFG_MPTPR_1BK_4K */ /* * Check Bank 0 Memory Size for re-configuration * * try 8 column mode */ size8 = dram_size (CFG_MAMR_8COL, (ulong *) SDRAM_BASE4_PRELIM, SDRAM_MAX_SIZE); udelay (1000); /* * try 9 column mode */ size9 = dram_size (CFG_MAMR_9COL, (ulong *) SDRAM_BASE4_PRELIM, SDRAM_MAX_SIZE); if (size8 < size9) { /* leave configuration at 9 columns */ size_b0 = size9; /* debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20); */ } else { /* back to 8 columns */ size_b0 = size8; memctl->memc_mamr = CFG_MAMR_8COL; udelay (500); /* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */ } udelay (1000); /* * Adjust refresh rate depending on SDRAM type, both banks * For types > 128 MBit leave it at the current (fast) rate */ if ((size_b0 < 0x02000000)) { /* reduce to 15.6 us (62.4 us / quad) */ memctl->memc_mptpr = CFG_MPTPR_2BK_4K; udelay (1000); } /* SDRAM Bank 0 is bigger - map first */ memctl->memc_or4 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM; memctl->memc_br4 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; udelay (10000); return (size_b0); }
phys_size_t initdram (int board_type) { volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; long int size_b0, size_b1, size8, size9; upmconfig (UPMA, (uint *) sdram_table, sizeof (sdram_table) / sizeof (uint)); /* * Up to 2 Banks of 64Mbit x 2 devices * Initial builds only have 1 */ memctl->memc_mptpr = CONFIG_SYS_MPTPR_1BK_4K; memctl->memc_mar = 0x00000088; /* * Map controller SDRAM bank 0 */ memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM; memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM; memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */ udelay (200); /* * Map controller SDRAM bank 1 */ memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM; memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM; /* * Perform SDRAM initializsation sequence */ memctl->memc_mcr = 0x80002105; /* SDRAM bank 0 */ udelay (1); memctl->memc_mcr = 0x80002230; /* SDRAM bank 0 - execute twice */ udelay (1); memctl->memc_mcr = 0x80004105; /* SDRAM bank 1 */ udelay (1); memctl->memc_mcr = 0x80004230; /* SDRAM bank 1 - execute twice */ udelay (1); memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */ udelay (1000); /* * Preliminary prescaler for refresh (depends on number of * banks): This value is selected for four cycles every 62.4 us * with two SDRAM banks or four cycles every 31.2 us with one * bank. It will be adjusted after memory sizing. */ memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_8K; memctl->memc_mar = 0x00000088; /* * Check Bank 0 Memory Size for re-configuration * * try 8 column mode */ size8 = dram_size (CONFIG_SYS_MAMR_8COL, (long *) SDRAM_BASE1_PRELIM, SDRAM_MAX_SIZE); udelay (1000); /* * try 9 column mode */ size9 = dram_size (CONFIG_SYS_MAMR_9COL, (long *) SDRAM_BASE1_PRELIM, SDRAM_MAX_SIZE); if (size8 < size9) { /* leave configuration at 9 columns */ size_b0 = size9; /* debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20); */ } else { /* back to 8 columns */ size_b0 = size8; memctl->memc_mamr = CONFIG_SYS_MAMR_8COL; udelay (500); /* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */ } /* * Check Bank 1 Memory Size * use current column settings * [9 column SDRAM may also be used in 8 column mode, * but then only half the real size will be used.] */ size_b1 = dram_size (memctl->memc_mamr, (long *) SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE); /* debug ("SDRAM Bank 1: %ld MB\n", size8 >> 20); */ udelay (1000); /* * Adjust refresh rate depending on SDRAM type, both banks * For types > 128 MBit leave it at the current (fast) rate */ if ((size_b0 < 0x02000000) && (size_b1 < 0x02000000)) { /* reduce to 15.6 us (62.4 us / quad) */ memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K; udelay (1000); } /* * Final mapping: map bigger bank first */ if (size_b1 > size_b0) { /* SDRAM Bank 1 is bigger - map first */ memctl->memc_or2 = ((-size_b1) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM; memctl->memc_br2 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; if (size_b0 > 0) { /* * Position Bank 0 immediately above Bank 1 */ memctl->memc_or1 = ((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM; memctl->memc_br1 = ((CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V) + size_b1; } else { unsigned long reg; /* * No bank 0 * * invalidate bank */ memctl->memc_br1 = 0; /* adjust refresh rate depending on SDRAM type, one bank */ reg = memctl->memc_mptpr; reg >>= 1; /* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */ memctl->memc_mptpr = reg; } } else { /* SDRAM Bank 0 is bigger - map first */