/* This is the only way buffers get added to the validate list.
*/
void
intel_batchbuffer_emit_reloc(struct intel_batchbuffer *batch,
drm_intel_bo *buffer, uint32_t delta,
uint32_t read_domains, uint32_t write_domain,
int fenced)
{
int ret;
if (batch->ptr - batch->buffer > BATCH_SZ)
printf("bad relocation ptr %p map %p offset %d size %d\n",
batch->ptr, batch->buffer,
(int)(batch->ptr - batch->buffer),
BATCH_SZ);
if (fenced)
ret = drm_intel_bo_emit_reloc_fence(batch->bo, batch->ptr - batch->buffer,
buffer, delta,
read_domains, write_domain);
else
ret = drm_intel_bo_emit_reloc(batch->bo, batch->ptr - batch->buffer,
buffer, delta,
read_domains, write_domain);
intel_batchbuffer_emit_dword(batch, buffer->offset + delta);
assert(ret == 0);
}
int
intel_bo_add_reloc(struct intel_bo *bo, uint32_t offset,
struct intel_bo *target_bo, uint32_t target_offset,
uint32_t flags, uint64_t *presumed_offset)
{
uint32_t read_domains, write_domain;
int err;
if (flags & INTEL_RELOC_WRITE) {
/*
* Because of the translation to domains, INTEL_RELOC_GGTT should only
* be set on GEN6 when the bo is written by MI_* or PIPE_CONTROL. The
* kernel will translate it back to INTEL_RELOC_GGTT.
*/
write_domain = (flags & INTEL_RELOC_GGTT) ?
I915_GEM_DOMAIN_INSTRUCTION : I915_GEM_DOMAIN_RENDER;
read_domains = write_domain;
} else {
write_domain = 0;
read_domains = I915_GEM_DOMAIN_RENDER |
I915_GEM_DOMAIN_SAMPLER |
I915_GEM_DOMAIN_INSTRUCTION |
I915_GEM_DOMAIN_VERTEX;
}
if (flags & INTEL_RELOC_FENCE) {
err = drm_intel_bo_emit_reloc_fence(gem_bo(bo), offset,
gem_bo(target_bo), target_offset,
read_domains, write_domain);
} else {
err = drm_intel_bo_emit_reloc(gem_bo(bo), offset,
gem_bo(target_bo), target_offset,
read_domains, write_domain);
}
*presumed_offset = gem_bo(target_bo)->offset64 + target_offset;
return err;
}
