int main(int argc, char *argv[])
{
uint32_t leaf, counter;
uint32_t eax, ebx, ecx, edx;
openconsole(&dev_null_r, &dev_stdcon_w);
if (argc < 2 || argc > 4) {
printf("Usage: %s leaf [counter]\n", argv[0]);
exit(1);
}
leaf = strtoul(argv[1], NULL, 0);
counter = (argv > 2) ? strtoul(argv[2], NULL, 0) : 0;
if (!cpu_has_eflag(EFLAGS_ID)) {
printf("The CPUID instruction is not supported\n");
exit(1);
}
cpuid_count(leaf, counter, &eax, &ebx, &ecx, &edx);
dump_reg("eax", eax);
dump_reg("ebx", ebx);
dump_reg("ecx", ecx);
dump_reg("edx", edx);
return 0;
}
void test_dump_reg(){
int i=0;
for(i=0; i<32; i++){
BREG[i]=i;
}
dump_reg('d');
printf("\n");
dump_reg('h');
return;
}
void
dump_regs(union fpregs *fr1, union fpregs *fr2, union fpregs *fr3)
{
printf("BEFORE ASM\n");
dump_reg(fr1);
printf("AFTER ASM\n");
dump_reg(fr2);
printf("MANUAL\n");
dump_reg(fr3);
}
void test_run(){
PC = 0;
MEM[0]=0x21100002;//addi $s0, $t0, 10
MEM[1]=0x21100004;//addi $s0, $t0, 10
MEM[2]=0x21100006;//addi $s0, $t0, 10
MEM[3]=0x21100008;//addi $s0, $t0, 10
printf("BEFORE RUN!\n");
dump_reg('d');
run();
printf("AFTER RUN!\n");
dump_reg('d');
return;
}
static int internal_dump_operand(struct STREAM *stream, struct INSTRUCTION *instr, int op_index)
{
struct OPERAND *op;
if (op_index > 3 || op_index < 0)
return -1;
op = instr ->ops + op_index;
if (op ->flags & OPERAND_FLAG_PRESENT)
{
switch (op ->flags & OPERAND_TYPE_MASK)
{
case OPERAND_TYPE_REG:
dump_reg(stream, op ->value.reg.type, op ->value.reg.code, op ->size);
break;
case OPERAND_TYPE_MEM:
dump_addr(stream, instr, op);
break;
case OPERAND_TYPE_IMM:
dump_imm(stream, op);
break;
case OPERAND_TYPE_DIR:
dump_dir(stream, op);
break;
default:
safe_unistrncpy(stream, _UT("internal error"));
break;
}
}
return stream ->reallen;
}
static void
dump_dstreg(struct sh_dstreg dstreg,
struct sh_srcreg *indreg,
const struct dump_info *di)
{
union {
struct sh_reg reg;
struct sh_dstreg dstreg;
} u;
memset(&u, 0, sizeof(u));
assert( (dstreg.modifier & (SVGA3DDSTMOD_SATURATE | SVGA3DDSTMOD_PARTIALPRECISION)) == dstreg.modifier );
if (dstreg.modifier & SVGA3DDSTMOD_SATURATE)
_debug_printf( "_sat" );
if (dstreg.modifier & SVGA3DDSTMOD_PARTIALPRECISION)
_debug_printf( "_pp" );
switch (dstreg.shift_scale) {
case 0:
break;
case 1:
_debug_printf( "_x2" );
break;
case 2:
_debug_printf( "_x4" );
break;
case 3:
_debug_printf( "_x8" );
break;
case 13:
_debug_printf( "_d8" );
break;
case 14:
_debug_printf( "_d4" );
break;
case 15:
_debug_printf( "_d2" );
break;
default:
assert( 0 );
}
_debug_printf( " " );
u.dstreg = dstreg;
dump_reg( u.reg, indreg, di);
if (dstreg.write_mask != SVGA3DWRITEMASK_ALL) {
_debug_printf( "." );
if (dstreg.write_mask & SVGA3DWRITEMASK_0)
_debug_printf( "x" );
if (dstreg.write_mask & SVGA3DWRITEMASK_1)
_debug_printf( "y" );
if (dstreg.write_mask & SVGA3DWRITEMASK_2)
_debug_printf( "z" );
if (dstreg.write_mask & SVGA3DWRITEMASK_3)
_debug_printf( "w" );
}
}
static int tvp5150_detect_client(struct i2c_adapter *adapter,
int address, int kind)
{
struct i2c_client *c;
struct tvp5150 *core;
int rv;
if (debug)
printk( KERN_INFO
"tvp5150.c: detecting tvp5150 client on address 0x%x\n",
address << 1);
client_template.adapter = adapter;
client_template.addr = address;
/* Check if the adapter supports the needed features */
if (!i2c_check_functionality
(adapter,
I2C_FUNC_SMBUS_READ_BYTE | I2C_FUNC_SMBUS_WRITE_BYTE_DATA))
return 0;
c = kmalloc(sizeof(struct i2c_client), GFP_KERNEL);
if (!c)
return -ENOMEM;
memcpy(c, &client_template, sizeof(struct i2c_client));
core = kzalloc(sizeof(struct tvp5150), GFP_KERNEL);
if (!core) {
kfree(c);
return -ENOMEM;
}
i2c_set_clientdata(c, core);
rv = i2c_attach_client(c);
core->norm = V4L2_STD_ALL; /* Default is autodetect */
core->route.input = TVP5150_COMPOSITE1;
core->enable = 1;
core->bright = 128;
core->contrast = 128;
core->hue = 0;
core->sat = 128;
if (rv) {
kfree(c);
kfree(core);
return rv;
}
if (debug > 1)
dump_reg(c);
return 0;
}
static void dump_dstreg( struct sh_dstreg dstreg, const struct dump_info *di )
{
union {
struct sh_reg reg;
struct sh_dstreg dstreg;
} u;
assert( (dstreg.modifier & (SVGA3DDSTMOD_SATURATE | SVGA3DDSTMOD_PARTIALPRECISION)) == dstreg.modifier );
if (dstreg.modifier & SVGA3DDSTMOD_SATURATE)
debug_printf( "_sat" );
if (dstreg.modifier & SVGA3DDSTMOD_PARTIALPRECISION)
debug_printf( "_pp" );
switch (dstreg.shift_scale) {
case 0:
break;
case 1:
debug_printf( "_x2" );
break;
case 2:
debug_printf( "_x4" );
break;
case 3:
debug_printf( "_x8" );
break;
case 13:
debug_printf( "_d8" );
break;
case 14:
debug_printf( "_d4" );
break;
case 15:
debug_printf( "_d2" );
break;
default:
assert( 0 );
}
debug_printf( " " );
u.dstreg = dstreg;
dump_reg( u.reg, NULL, di );
if (dstreg.write_mask != SVGA3DWRITEMASK_ALL) {
debug_printf( "." );
if (dstreg.write_mask & SVGA3DWRITEMASK_0)
debug_printf( "x" );
if (dstreg.write_mask & SVGA3DWRITEMASK_1)
debug_printf( "y" );
if (dstreg.write_mask & SVGA3DWRITEMASK_2)
debug_printf( "z" );
if (dstreg.write_mask & SVGA3DWRITEMASK_3)
debug_printf( "w" );
}
}
void MII_dump_0_to_5(
ushort regvals[6],
uchar reglo,
uchar reghi)
{
ulong i;
for (i = 0; i < 6; i++) {
if ((reglo <= i) && (i <= reghi))
dump_reg(regvals[i], ®_0_5_desc_tbl[i],
&desc_and_len_tbl[i]);
}
}
void test_step(){
PC = 0;
MEM[0]=0x2110000a;//addi $s0, $t0, 10
//00100001000100000000000000001010
BREG[s0]=0;
BREG[t0]=15;
BREG[t2]=20;
printf("BEFORE STEP!\n");
printf("PC = %d\n", PC);
printf("RI = %d\n", RI);
dump_reg('d');
printf("funct %x\nshamt %x\nk16 %x\nrd %x\nrt %x\nrs %x\nk26 %x\nopcode %x\n\n", funct, shamnt, k16, rd, rt, rs, k26, opcode);
step();
printf("AFTER STEP!\n");
printf("PC = %d\n", PC);
printf("RI = %d\n", RI);
dump_reg('d');
printf("funct %x\nshamt %x\nk16 %x\nrd %x\nrt %x\nrs %x\nk26 %x\nopcode %x\n\n", funct, shamnt, k16, rd, rt, rs, k26, opcode);
return;
}
/**
* fsl_ssi_trigger: start and stop the DMA transfer.
*
* This function is called by ALSA to start, stop, pause, and resume the DMA
* transfer of data.
*
* The DMA channel is in external master start and pause mode, which
* means the SSI completely controls the flow of data.
*/
static int fsl_ssi_trigger(struct snd_pcm_substream *substream, int cmd,
struct snd_soc_dai *dai)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(rtd->cpu_dai);
struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
unsigned long flags;
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_RESUME:
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
write_ssi_mask(&ssi->scr, 0,
CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_TE);
write_ssi_mask(&ssi->sier, 0, CCSR_SSI_SIER_TDMAE);
} else {
write_ssi_mask(&ssi->scr, 0,
CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_RE);
write_ssi_mask(&ssi->sier, 0, CCSR_SSI_SIER_RDMAE);
}
dump_reg(ssi);
break;
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_SUSPEND:
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_TE, 0);
write_ssi_mask(&ssi->sier, CCSR_SSI_SIER_TDMAE, 0);
} else {
write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_RE, 0);
write_ssi_mask(&ssi->sier, CCSR_SSI_SIER_RDMAE, 0);
}
if ((read_ssi(&ssi->scr) & (CCSR_SSI_SCR_TE | CCSR_SSI_SCR_RE)) == 0) {
write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_SSIEN, 0);
spin_lock_irqsave(&ssi_private->baudclk_lock, flags);
ssi_private->baudclk_locked = false;
spin_unlock_irqrestore(&ssi_private->baudclk_lock, flags);
}
break;
default:
return -EINVAL;
}
return 0;
}
system_trap()
{
int o0, o1, o2; /* user out register values */
int syscallno;
extern long lseek();
if ( Traptrace )
{
printf("**System call %d\n", Reg[2]);
dump_reg();
}
/* if (Reg[1] == 0)
/* { /* SYS_indir */
/* syscallno = Reg[8]; /* out reg 0 */
/* o0 = Reg[9];
/* o1 = Reg[10];
/* o2 = Reg[11];
/* }
/* else /* */
{
syscallno = Reg[2];
o0 = Reg[4];
o1 = Reg[5];
o2 = Reg[6];
}
switch (syscallno)
{
case SYS_exit: /*1*/
printstatistics();
fflush(stdout);
exit(0);
break;
case SYS_read: /*3*/
Reg[1] =
read(u_to_int_fd(o0), u_to_int_addr(o1), o2);
break;
case SYS_write: /*4*/
Reg[1] =
write(u_to_int_fd(o0), u_to_int_addr(o1), o2);
break;
case SYS_open: /*5*/
Reg[1] = open(u_to_int_addr(o0), o1, o2); /* */
break;
case SYS_close: /*6*/
Reg[1] = 0; /* hack */
break;
case 17: /* 17 */
/* old sbreak. where did it go? */
Reg[1] = ((o0 / 8192) + 1) * 8192;
break;
case SYS_lseek: /*19*/
Reg[1] = (int) lseek(u_to_int_fd(o0), (long) o1, o2);
break;
case SYS_ioctl:/* 54 */
{ /* copied from sas -- I don't understand yet. */
/* see dave weaver */
#define IOCPARM_MASK 0x7f /* parameters must be < 128 bytes */
int size = (o1 >> 16) & IOCPARM_MASK;
char ioctl_group = (o1 >> 8) & 0x00ff;
if ((ioctl_group == 't') && (size == 8))
{
size = 6;
o1 = (o1 & ~((IOCPARM_MASK << 16)))
| (size << 16);
}
}
Reg[1] = ioctl(u_to_int_fd(o0),o1,u_to_int_addr(o2));
Reg[1] = 0; /* hack */
break;
case SYS_fstat: /* 62 */
Reg[1] = fstat(o1, o2);
break;
case SYS_getpagesize: /* 64 */
Reg[1] = getpagesize();
break;
default:
printf("Unknown System call %d\n", syscallno);
if ( ! Traptrace )
dump_reg();
exit(2);
break;
}
if ( Traptrace )
{
printf("**Afterwards:\n");
dump_reg();
}
}
static int
inst_INV(struct OPCodeDesc *op, struct machine *m)
{ NYI; dump_op(op); dump_reg(m); assert(0); return 0;}
/****************************************************************************
I2C Command
****************************************************************************/
static int tvp5150_command(struct i2c_client *client,
unsigned int cmd, void *arg)
{
struct tvp5150 *decoder = i2c_get_clientdata(client);
switch (cmd) {
case 0:
case DECODER_INIT:
tvp5150_reset(client);
break;
case DECODER_DUMP:
dump_reg(client);
break;
case DECODER_GET_CAPABILITIES:
{
struct video_decoder_capability *cap = arg;
cap->flags = VIDEO_DECODER_PAL |
VIDEO_DECODER_NTSC |
VIDEO_DECODER_SECAM |
VIDEO_DECODER_AUTO | VIDEO_DECODER_CCIR;
cap->inputs = 3;
cap->outputs = 1;
break;
}
case DECODER_GET_STATUS:
{
break;
}
case DECODER_SET_GPIO:
break;
case DECODER_SET_VBI_BYPASS:
break;
case DECODER_SET_NORM:
{
int *iarg = arg;
switch (*iarg) {
case VIDEO_MODE_NTSC:
break;
case VIDEO_MODE_PAL:
break;
case VIDEO_MODE_SECAM:
break;
case VIDEO_MODE_AUTO:
break;
default:
return -EINVAL;
}
decoder->norm = *iarg;
break;
}
case DECODER_SET_INPUT:
{
int *iarg = arg;
if (*iarg < 0 || *iarg > 3) {
return -EINVAL;
}
decoder->input = *iarg;
tvp5150_selmux(client, decoder->input);
break;
}
case DECODER_SET_OUTPUT:
{
int *iarg = arg;
/* not much choice of outputs */
if (*iarg != 0) {
return -EINVAL;
}
break;
}
case DECODER_ENABLE_OUTPUT:
{
int *iarg = arg;
decoder->enable = (*iarg != 0);
tvp5150_selmux(client, decoder->input);
break;
}
case VIDIOC_QUERYCTRL:
{
struct v4l2_queryctrl *qc = arg;
u8 i, n;
dprintk(1, KERN_DEBUG "VIDIOC_QUERYCTRL");
n = sizeof(tvp5150_qctrl) / sizeof(tvp5150_qctrl[0]);
for (i = 0; i < n; i++)
if (qc->id && qc->id == tvp5150_qctrl[i].id) {
memcpy(qc, &(tvp5150_qctrl[i]),
sizeof(*qc));
return 0;
}
return -EINVAL;
}
case VIDIOC_G_CTRL:
{
struct v4l2_control *ctrl = arg;
dprintk(1, KERN_DEBUG "VIDIOC_G_CTRL");
return tvp5150_get_ctrl(client, ctrl);
}
case VIDIOC_S_CTRL_OLD: /* ??? */
case VIDIOC_S_CTRL:
{
struct v4l2_control *ctrl = arg;
u8 i, n;
dprintk(1, KERN_DEBUG "VIDIOC_S_CTRL");
n = sizeof(tvp5150_qctrl) / sizeof(tvp5150_qctrl[0]);
for (i = 0; i < n; i++)
if (ctrl->id == tvp5150_qctrl[i].id) {
if (ctrl->value <
tvp5150_qctrl[i].minimum
|| ctrl->value >
tvp5150_qctrl[i].maximum)
return -ERANGE;
dprintk(1,
KERN_DEBUG
"VIDIOC_S_CTRL: id=%d, value=%d",
ctrl->id, ctrl->value);
return tvp5150_set_ctrl(client, ctrl);
}
return -EINVAL;
}
case DECODER_SET_PICTURE:
{
struct video_picture *pic = arg;
if (decoder->bright != pic->brightness) {
/* We want 0 to 255 we get 0-65535 */
decoder->bright = pic->brightness;
tvp5150_write(client, TVP5150_BRIGHT_CTL,
decoder->bright >> 8);
}
if (decoder->contrast != pic->contrast) {
/* We want 0 to 255 we get 0-65535 */
decoder->contrast = pic->contrast;
tvp5150_write(client, TVP5150_CONTRAST_CTL,
decoder->contrast >> 8);
}
if (decoder->sat != pic->colour) {
/* We want 0 to 255 we get 0-65535 */
decoder->sat = pic->colour;
tvp5150_write(client, TVP5150_SATURATION_CTL,
decoder->contrast >> 8);
}
/****************************************************************************
I2C Command
****************************************************************************/
static int tvp5150_command(struct i2c_client *c,
unsigned int cmd, void *arg)
{
struct tvp5150 *decoder = i2c_get_clientdata(c);
switch (cmd) {
case 0:
case VIDIOC_INT_RESET:
tvp5150_reset(c);
break;
case VIDIOC_INT_G_VIDEO_ROUTING:
{
struct v4l2_routing *route = arg;
*route = decoder->route;
break;
}
case VIDIOC_INT_S_VIDEO_ROUTING:
{
struct v4l2_routing *route = arg;
decoder->route = *route;
tvp5150_selmux(c);
break;
}
case VIDIOC_S_STD:
if (decoder->norm == *(v4l2_std_id *)arg)
break;
return tvp5150_set_std(c, *(v4l2_std_id *)arg);
case VIDIOC_G_STD:
*(v4l2_std_id *)arg = decoder->norm;
break;
case VIDIOC_G_SLICED_VBI_CAP:
{
struct v4l2_sliced_vbi_cap *cap = arg;
tvp5150_dbg(1, "VIDIOC_G_SLICED_VBI_CAP\n");
tvp5150_vbi_get_cap(vbi_ram_default, cap);
break;
}
case VIDIOC_S_FMT:
{
struct v4l2_format *fmt;
struct v4l2_sliced_vbi_format *svbi;
int i;
fmt = arg;
if (fmt->type != V4L2_BUF_TYPE_SLICED_VBI_CAPTURE)
return -EINVAL;
svbi = &fmt->fmt.sliced;
if (svbi->service_set != 0) {
for (i = 0; i <= 23; i++) {
svbi->service_lines[1][i] = 0;
svbi->service_lines[0][i]=tvp5150_set_vbi(c,
vbi_ram_default,
svbi->service_lines[0][i],0xf0,i,3);
}
/* Enables FIFO */
tvp5150_write(c, TVP5150_FIFO_OUT_CTRL,1);
} else {
/* Disables FIFO*/
tvp5150_write(c, TVP5150_FIFO_OUT_CTRL,0);
/* Disable Full Field */
tvp5150_write(c, TVP5150_FULL_FIELD_ENA, 0);
/* Disable Line modes */
for (i=TVP5150_LINE_MODE_INI; i<=TVP5150_LINE_MODE_END; i++)
tvp5150_write(c, i, 0xff);
}
break;
}
case VIDIOC_G_FMT:
{
struct v4l2_format *fmt;
struct v4l2_sliced_vbi_format *svbi;
int i, mask=0;
fmt = arg;
if (fmt->type != V4L2_BUF_TYPE_SLICED_VBI_CAPTURE)
return -EINVAL;
svbi = &fmt->fmt.sliced;
memset(svbi, 0, sizeof(*svbi));
for (i = 0; i <= 23; i++) {
svbi->service_lines[0][i]=tvp5150_get_vbi(c,
vbi_ram_default,i);
mask|=svbi->service_lines[0][i];
}
svbi->service_set=mask;
break;
}
#ifdef CONFIG_VIDEO_ADV_DEBUG
case VIDIOC_DBG_G_REGISTER:
case VIDIOC_DBG_S_REGISTER:
{
struct v4l2_register *reg = arg;
if (!v4l2_chip_match_i2c_client(c, reg->match_type, reg->match_chip))
return -EINVAL;
if (!capable(CAP_SYS_ADMIN))
return -EPERM;
if (cmd == VIDIOC_DBG_G_REGISTER)
reg->val = tvp5150_read(c, reg->reg & 0xff);
else
tvp5150_write(c, reg->reg & 0xff, reg->val & 0xff);
break;
}
#endif
case VIDIOC_LOG_STATUS:
dump_reg(c);
break;
case VIDIOC_G_TUNER:
{
struct v4l2_tuner *vt = arg;
int status = tvp5150_read(c, 0x88);
vt->signal = ((status & 0x04) && (status & 0x02)) ? 0xffff : 0x0;
break;
}
case VIDIOC_QUERYCTRL:
{
struct v4l2_queryctrl *qc = arg;
int i;
tvp5150_dbg(1, "VIDIOC_QUERYCTRL called\n");
for (i = 0; i < ARRAY_SIZE(tvp5150_qctrl); i++)
if (qc->id && qc->id == tvp5150_qctrl[i].id) {
memcpy(qc, &(tvp5150_qctrl[i]),
sizeof(*qc));
return 0;
}
return -EINVAL;
}
case VIDIOC_G_CTRL:
{
struct v4l2_control *ctrl = arg;
tvp5150_dbg(1, "VIDIOC_G_CTRL called\n");
return tvp5150_get_ctrl(c, ctrl);
}
case VIDIOC_S_CTRL:
{
struct v4l2_control *ctrl = arg;
u8 i, n;
n = ARRAY_SIZE(tvp5150_qctrl);
for (i = 0; i < n; i++)
if (ctrl->id == tvp5150_qctrl[i].id) {
if (ctrl->value <
tvp5150_qctrl[i].minimum
|| ctrl->value >
tvp5150_qctrl[i].maximum)
return -ERANGE;
tvp5150_dbg(1,
"VIDIOC_S_CTRL: id=%d, value=%d\n",
ctrl->id, ctrl->value);
return tvp5150_set_ctrl(c, ctrl);
}
return -EINVAL;
}
default:
return -EINVAL;
}
return 0;
}
void
svga_shader_dump(
const unsigned *assem,
unsigned dwords,
unsigned do_binary )
{
const unsigned *start = assem;
boolean finished = FALSE;
struct dump_info di;
unsigned i;
if (do_binary) {
for (i = 0; i < dwords; i++)
debug_printf(" 0x%08x,\n", assem[i]);
debug_printf("\n\n");
}
di.version.value = *assem++;
di.is_ps = (di.version.type == SVGA3D_PS_TYPE);
debug_printf(
"%s_%u_%u\n",
di.is_ps ? "ps" : "vs",
di.version.major,
di.version.minor );
while (!finished) {
struct sh_op op = *(struct sh_op *) assem;
if (assem - start >= dwords) {
debug_printf("... ran off end of buffer\n");
assert(0);
return;
}
switch (op.opcode) {
case SVGA3DOP_DCL:
{
struct sh_dcl dcl = *(struct sh_dcl *) assem;
debug_printf( "dcl" );
if (sh_dstreg_type( dcl.reg ) == SVGA3DREG_SAMPLER)
dump_sampleinfo( dcl.u.ps.sampleinfo );
else if (di.is_ps) {
if (di.version.major == 3 &&
sh_dstreg_type( dcl.reg ) != SVGA3DREG_MISCTYPE)
dump_usageinfo( dcl.u.vs.semantic );
}
else
dump_usageinfo( dcl.u.vs.semantic );
dump_dstreg( dcl.reg, &di );
debug_printf( "\n" );
assem += sizeof( struct sh_dcl ) / sizeof( unsigned );
}
break;
case SVGA3DOP_DEFB:
{
struct sh_defb defb = *(struct sh_defb *) assem;
debug_printf( "defb " );
dump_reg( defb.reg, NULL, &di );
debug_printf( ", " );
dump_bdata( defb.data );
debug_printf( "\n" );
assem += sizeof( struct sh_defb ) / sizeof( unsigned );
}
break;
case SVGA3DOP_DEFI:
{
struct sh_defi defi = *(struct sh_defi *) assem;
debug_printf( "defi " );
dump_reg( defi.reg, NULL, &di );
debug_printf( ", " );
dump_idata( defi.idata );
debug_printf( "\n" );
assem += sizeof( struct sh_defi ) / sizeof( unsigned );
}
break;
case SVGA3DOP_TEXCOORD:
assert( di.is_ps );
dump_op( op, "texcoord" );
if (0) {
struct sh_dstop dstop = *(struct sh_dstop *) assem;
dump_dstreg( dstop.dst, &di );
assem += sizeof( struct sh_dstop ) / sizeof( unsigned );
}
else {
struct sh_unaryop unaryop = *(struct sh_unaryop *) assem;
dump_dstreg( unaryop.dst, &di );
debug_printf( ", " );
dump_srcreg( unaryop.src, NULL, &di );
assem += sizeof( struct sh_unaryop ) / sizeof( unsigned );
}
debug_printf( "\n" );
break;
case SVGA3DOP_TEX:
assert( di.is_ps );
if (0) {
dump_op( op, "tex" );
if (0) {
struct sh_dstop dstop = *(struct sh_dstop *) assem;
dump_dstreg( dstop.dst, &di );
assem += sizeof( struct sh_dstop ) / sizeof( unsigned );
}
else {
struct sh_unaryop unaryop = *(struct sh_unaryop *) assem;
dump_dstreg( unaryop.dst, &di );
debug_printf( ", " );
dump_srcreg( unaryop.src, NULL, &di );
assem += sizeof( struct sh_unaryop ) / sizeof( unsigned );
}
}
else {
struct sh_binaryop binaryop = *(struct sh_binaryop *) assem;
dump_op( op, "texld" );
dump_dstreg( binaryop.dst, &di );
debug_printf( ", " );
dump_srcreg( binaryop.src0, NULL, &di );
debug_printf( ", " );
dump_srcreg( binaryop.src1, NULL, &di );
assem += sizeof( struct sh_binaryop ) / sizeof( unsigned );
}
debug_printf( "\n" );
break;
case SVGA3DOP_DEF:
{
struct sh_def def = *(struct sh_def *) assem;
debug_printf( "def " );
dump_reg( def.reg, NULL, &di );
debug_printf( ", " );
dump_cdata( def.cdata );
debug_printf( "\n" );
assem += sizeof( struct sh_def ) / sizeof( unsigned );
}
break;
case SVGA3DOP_PHASE:
debug_printf( "phase\n" );
assem += sizeof( struct sh_op ) / sizeof( unsigned );
break;
case SVGA3DOP_COMMENT:
{
struct sh_comment comment = *(struct sh_comment *)assem;
/* Ignore comment contents. */
assem += sizeof(struct sh_comment) / sizeof(unsigned) + comment.size;
}
break;
case SVGA3DOP_RET:
debug_printf( "ret\n" );
assem += sizeof( struct sh_op ) / sizeof( unsigned );
break;
case SVGA3DOP_END:
debug_printf( "end\n" );
finished = TRUE;
break;
default:
{
const struct sh_opcode_info *info = svga_opcode_info( op.opcode );
uint i;
uint num_src = info->num_src + op.predicated;
boolean not_first_arg = FALSE;
assert( info->num_dst <= 1 );
if (op.opcode == SVGA3DOP_SINCOS && di.version.major < 3)
num_src += 2;
dump_comp_op( op, info->mnemonic );
assem += sizeof( struct sh_op ) / sizeof( unsigned );
if (info->num_dst > 0) {
struct sh_dstreg dstreg = *(struct sh_dstreg *) assem;
dump_dstreg( dstreg, &di );
assem += sizeof( struct sh_dstreg ) / sizeof( unsigned );
not_first_arg = TRUE;
}
for (i = 0; i < num_src; i++) {
struct sh_srcreg srcreg;
struct sh_srcreg indreg;
srcreg = *(struct sh_srcreg *) assem;
assem += sizeof( struct sh_srcreg ) / sizeof( unsigned );
if (srcreg.relative && !di.is_ps && di.version.major >= 2) {
indreg = *(struct sh_srcreg *) assem;
assem += sizeof( struct sh_srcreg ) / sizeof( unsigned );
}
if (not_first_arg)
debug_printf( ", " );
else
debug_printf( " " );
dump_srcreg( srcreg, &indreg, &di );
not_first_arg = TRUE;
}
debug_printf( "\n" );
}
}
}
}
static void dump_srcreg( struct sh_srcreg srcreg, struct sh_srcreg *indreg, const struct dump_info *di )
{
switch (srcreg.modifier) {
case SVGA3DSRCMOD_NEG:
case SVGA3DSRCMOD_BIASNEG:
case SVGA3DSRCMOD_SIGNNEG:
case SVGA3DSRCMOD_X2NEG:
case SVGA3DSRCMOD_ABSNEG:
_debug_printf( "-" );
break;
case SVGA3DSRCMOD_COMP:
_debug_printf( "1-" );
break;
case SVGA3DSRCMOD_NOT:
_debug_printf( "!" );
}
dump_reg( *(struct sh_reg *) &srcreg, indreg, di );
switch (srcreg.modifier) {
case SVGA3DSRCMOD_NONE:
case SVGA3DSRCMOD_NEG:
case SVGA3DSRCMOD_COMP:
case SVGA3DSRCMOD_NOT:
break;
case SVGA3DSRCMOD_BIAS:
case SVGA3DSRCMOD_BIASNEG:
_debug_printf( "_bias" );
break;
case SVGA3DSRCMOD_SIGN:
case SVGA3DSRCMOD_SIGNNEG:
_debug_printf( "_bx2" );
break;
case SVGA3DSRCMOD_X2:
case SVGA3DSRCMOD_X2NEG:
_debug_printf( "_x2" );
break;
case SVGA3DSRCMOD_DZ:
_debug_printf( "_dz" );
break;
case SVGA3DSRCMOD_DW:
_debug_printf( "_dw" );
break;
case SVGA3DSRCMOD_ABS:
case SVGA3DSRCMOD_ABSNEG:
_debug_printf("_abs");
break;
default:
assert( 0 );
}
if (srcreg.swizzle_x != 0 || srcreg.swizzle_y != 1 || srcreg.swizzle_z != 2 || srcreg.swizzle_w != 3) {
_debug_printf( "." );
if (srcreg.swizzle_x == srcreg.swizzle_y && srcreg.swizzle_y == srcreg.swizzle_z && srcreg.swizzle_z == srcreg.swizzle_w) {
_debug_printf( "%c", "xyzw"[srcreg.swizzle_x] );
}
else {
_debug_printf( "%c", "xyzw"[srcreg.swizzle_x] );
_debug_printf( "%c", "xyzw"[srcreg.swizzle_y] );
_debug_printf( "%c", "xyzw"[srcreg.swizzle_z] );
_debug_printf( "%c", "xyzw"[srcreg.swizzle_w] );
}
}
}
int RegReadMain(void)
{
dump_reg();
return 0;
}
void
svga_shader_dump(
const unsigned *assem,
unsigned dwords,
unsigned do_binary )
{
boolean finished = FALSE;
struct dump_info di;
di.version = *assem++;
di.is_ps = (di.version & 0xFFFF0000) == 0xFFFF0000;
di.indent = 0;
_debug_printf(
"%s_%u_%u\n",
di.is_ps ? "ps" : "vs",
(di.version >> 8) & 0xff,
di.version & 0xff );
while (!finished) {
struct sh_op op = *(struct sh_op *) assem;
switch (op.opcode) {
case SVGA3DOP_DCL:
{
struct sh_dcl dcl = *(struct sh_dcl *) assem;
_debug_printf( "dcl" );
switch (sh_dstreg_type(dcl.reg)) {
case SVGA3DREG_INPUT:
if ((di.is_ps && di.version >= SVGA3D_PS_30) ||
(!di.is_ps && di.version >= SVGA3D_VS_30)) {
dump_semantic(dcl.u.semantic.usage,
dcl.u.semantic.usage_index);
}
break;
case SVGA3DREG_TEXCRDOUT:
if (!di.is_ps && di.version >= SVGA3D_VS_30) {
dump_semantic(dcl.u.semantic.usage,
dcl.u.semantic.usage_index);
}
break;
case SVGA3DREG_SAMPLER:
dump_sampleinfo( dcl.u.sampleinfo );
break;
}
dump_dstreg(dcl.reg, NULL, &di);
_debug_printf( "\n" );
assem += sizeof( struct sh_dcl ) / sizeof( unsigned );
}
break;
case SVGA3DOP_DEFB:
{
struct sh_defb defb = *(struct sh_defb *) assem;
_debug_printf( "defb " );
dump_reg( defb.reg, NULL, &di );
_debug_printf( ", " );
dump_bdata( defb.data );
_debug_printf( "\n" );
assem += sizeof( struct sh_defb ) / sizeof( unsigned );
}
break;
case SVGA3DOP_DEFI:
{
struct sh_defi defi = *(struct sh_defi *) assem;
_debug_printf( "defi " );
dump_reg( defi.reg, NULL, &di );
_debug_printf( ", " );
dump_idata( defi.idata );
_debug_printf( "\n" );
assem += sizeof( struct sh_defi ) / sizeof( unsigned );
}
break;
case SVGA3DOP_TEXCOORD:
{
struct sh_opcode_info info = *svga_opcode_info(op.opcode);
assert(di.is_ps);
if (di.version > SVGA3D_PS_13) {
assert(info.num_src == 0);
info.num_src = 1;
}
dump_inst(&di, &assem, op, &info);
}
break;
case SVGA3DOP_TEX:
{
struct sh_opcode_info info = *svga_opcode_info(op.opcode);
assert(di.is_ps);
if (di.version > SVGA3D_PS_13) {
assert(info.num_src == 0);
if (di.version > SVGA3D_PS_14) {
info.num_src = 2;
info.mnemonic = "texld";
} else {
info.num_src = 1;
}
}
dump_inst(&di, &assem, op, &info);
}
break;
case SVGA3DOP_DEF:
{
struct sh_def def = *(struct sh_def *) assem;
_debug_printf( "def " );
dump_reg( def.reg, NULL, &di );
_debug_printf( ", " );
dump_cdata( def.cdata );
_debug_printf( "\n" );
assem += sizeof( struct sh_def ) / sizeof( unsigned );
}
break;
case SVGA3DOP_SINCOS:
{
struct sh_opcode_info info = *svga_opcode_info(op.opcode);
if ((di.is_ps && di.version >= SVGA3D_PS_30) ||
(!di.is_ps && di.version >= SVGA3D_VS_30)) {
assert(info.num_src == 3);
info.num_src = 1;
}
dump_inst(&di, &assem, op, &info);
}
break;
case SVGA3DOP_PHASE:
_debug_printf( "phase\n" );
assem += sizeof( struct sh_op ) / sizeof( unsigned );
break;
case SVGA3DOP_COMMENT:
{
struct sh_comment comment = *(struct sh_comment *)assem;
/* Ignore comment contents. */
assem += sizeof(struct sh_comment) / sizeof(unsigned) + comment.size;
}
break;
case SVGA3DOP_END:
finished = TRUE;
break;
default:
{
const struct sh_opcode_info *info = svga_opcode_info(op.opcode);
dump_inst(&di, &assem, op, info);
}
}
}
}
int main(int argc, char **argv)
{
I830Rec i830;
I830Ptr pI830 = &i830;
uint32_t dword;
int i;
do_self_tests();
intel_i830rec_init(pI830);
/* printf("%-18s %8s %s\n\n", "register name", "raw value", "description"); */
#if 0 /* enable HDMI audio bits */
dump_reg(SDVOB, "Digital Display Port B Control Register");
dword |= SDVO_ENABLE;
dword |= SDVO_BORDER_ENABLE;
dword |= SDVO_AUDIO_ENABLE;
dword |= SDVO_NULL_PACKETS_DURING_VSYNC;
OUTREG(SDVOB, dword);
dump_reg(PORT_HOTPLUG_EN, "Hot Plug Detect Enable");
OUTREG(PORT_HOTPLUG_EN, dword | AUDIO_HOTPLUG_EN);
dump_reg(VIDEO_DIP_CTL, "Video DIP Control");
dword &= ~(VIDEO_DIP_ENABLE_AVI |
VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
OUTREG(VIDEO_DIP_CTL, dword);
dword |= VIDEO_DIP_ENABLE;
OUTREG(VIDEO_DIP_CTL, dword);
#endif
#if 0 /* disable HDMI audio bits */
dump_reg(SDVOB, "Digital Display Port B Control Register");
dword &= ~SDVO_AUDIO_ENABLE;
dword &= ~SDVO_NULL_PACKETS_DURING_VSYNC;
OUTREG(SDVOB, dword);
#endif
dump_reg(VIDEO_DIP_CTL, "Video DIP Control");
dump_reg(SDVOB, "Digital Display Port B Control Register");
dump_reg(SDVOC, "Digital Display Port C Control Register");
dump_reg(PORT_HOTPLUG_EN, "Hot Plug Detect Enable");
dump_reg(AUD_CONFIG, "Audio Configuration");
dump_reg(AUD_DEBUG, "Audio Debug");
dump_reg(AUD_VID_DID, "Audio Vendor ID / Device ID");
dump_reg(AUD_RID, "Audio Revision ID");
dump_reg(AUD_SUBN_CNT, "Audio Subordinate Node Count");
dump_reg(AUD_FUNC_GRP, "Audio Function Group Type");
dump_reg(AUD_SUBN_CNT2, "Audio Subordinate Node Count");
dump_reg(AUD_GRP_CAP, "Audio Function Group Capabilities");
dump_reg(AUD_PWRST, "Audio Power State");
dump_reg(AUD_SUPPWR, "Audio Supported Power States");
dump_reg(AUD_SID, "Audio Root Node Subsystem ID");
dump_reg(AUD_OUT_CWCAP, "Audio Output Converter Widget Capabilities");
dump_reg(AUD_OUT_PCMSIZE, "Audio PCM Size and Rates");
dump_reg(AUD_OUT_STR, "Audio Stream Formats");
dump_reg(AUD_OUT_DIG_CNVT, "Audio Digital Converter");
dump_reg(AUD_OUT_CH_STR, "Audio Channel ID and Stream ID");
dump_reg(AUD_OUT_STR_DESC, "Audio Stream Descriptor Format");
dump_reg(AUD_PINW_CAP, "Audio Pin Complex Widget Capabilities");
dump_reg(AUD_PIN_CAP, "Audio Pin Capabilities");
dump_reg(AUD_PINW_CONNLNG, "Audio Connection List Length");
dump_reg(AUD_PINW_CONNLST, "Audio Connection List Entry");
dump_reg(AUD_PINW_CNTR, "Audio Pin Widget Control");
dump_reg(AUD_PINW_UNSOLRESP, "Audio Unsolicited Response Enable");
dump_reg(AUD_CNTL_ST, "Audio Control State Register");
dump_reg(AUD_PINW_CONFIG, "Audio Configuration Default");
dump_reg(AUD_HDMIW_STATUS, "Audio HDMI Status");
dump_reg(AUD_HDMIW_HDMIEDID, "Audio HDMI Data EDID Block");
dump_reg(AUD_HDMIW_INFOFR, "Audio HDMI Widget Data Island Packet");
dump_reg(AUD_CONV_CHCNT, "Audio Converter Channel Count");
dump_reg(AUD_CTS_ENABLE, "Audio CTS Programming Enable");
printf("\nDetails:\n\n");
dword = INREG(AUD_VID_DID);
printf("AUD_VID_DID vendor id\t\t\t0x%x\n", dword >> 16);
printf("AUD_VID_DID device id\t\t\t0x%x\n", dword & 0xffff);
dword = INREG(AUD_RID);
printf("AUD_RID major revision\t\t\t0x%lx\n", BITS(dword, 23, 20));
printf("AUD_RID minor revision\t\t\t0x%lx\n", BITS(dword, 19, 16));
printf("AUD_RID revision id\t\t\t0x%lx\n", BITS(dword, 15, 8));
printf("AUD_RID stepping id\t\t\t0x%lx\n", BITS(dword, 7, 0));
dword = INREG(SDVOB);
printf("SDVOB enable\t\t\t\t%u\n", !!(dword & SDVO_ENABLE));
printf("SDVOB HDMI encoding\t\t\t%u\n", !!(dword & SDVO_ENCODING_HDMI));
printf("SDVOB SDVO encoding\t\t\t%u\n", !!(dword & SDVO_ENCODING_SDVO));
printf("SDVOB null packets\t\t\t%u\n",
!!(dword & SDVO_NULL_PACKETS_DURING_VSYNC));
printf("SDVOB audio enabled\t\t\t%u\n", !!(dword & SDVO_AUDIO_ENABLE));
dword = INREG(SDVOC);
printf("SDVOC enable\t\t\t\t%u\n", !!(dword & SDVO_ENABLE));
printf("SDVOC HDMI encoding\t\t\t%u\n", !!(dword & SDVO_ENCODING_HDMI));
printf("SDVOC SDVO encoding\t\t\t%u\n", !!(dword & SDVO_ENCODING_SDVO));
printf("SDVOC null packets\t\t\t%u\n",
!!(dword & SDVO_NULL_PACKETS_DURING_VSYNC));
printf("SDVOC audio enabled\t\t\t%u\n", !!(dword & SDVO_AUDIO_ENABLE));
dword = INREG(PORT_HOTPLUG_EN);
printf("PORT_HOTPLUG_EN DisplayPort/HDMI port B\t%ld\n",
BIT(dword, 29)),
printf("PORT_HOTPLUG_EN DisplayPort/HDMI port C\t%ld\n",
BIT(dword, 28)),
printf("PORT_HOTPLUG_EN DisplayPort port D\t%ld\n", BIT(dword, 27)),
printf("PORT_HOTPLUG_EN SDVOB\t\t\t%ld\n", BIT(dword, 26)),
printf("PORT_HOTPLUG_EN SDVOC\t\t\t%ld\n", BIT(dword, 25)),
printf("PORT_HOTPLUG_EN audio\t\t\t%ld\n", BIT(dword, 24)),
printf("PORT_HOTPLUG_EN TV\t\t\t%ld\n", BIT(dword, 23)),
printf("PORT_HOTPLUG_EN CRT\t\t\t%ld\n", BIT(dword, 9)), dword =
INREG(VIDEO_DIP_CTL);
printf("VIDEO_DIP_CTL enable graphics DIP\t%ld\n", BIT(dword, 31)),
printf("VIDEO_DIP_CTL port select\t\t[0x%lx] %s\n",
BITS(dword, 30, 29), dip_port[BITS(dword, 30, 29)]);
printf("VIDEO_DIP_CTL DIP buffer trans active\t%lu\n", BIT(dword, 28));
printf("VIDEO_DIP_CTL AVI DIP enabled\t\t%lu\n", BIT(dword, 21));
printf("VIDEO_DIP_CTL vendor DIP enabled\t%lu\n", BIT(dword, 22));
printf("VIDEO_DIP_CTL SPD DIP enabled\t\t%lu\n", BIT(dword, 24));
printf("VIDEO_DIP_CTL DIP buffer index\t\t[0x%lx] %s\n",
BITS(dword, 20, 19), video_dip_index[BITS(dword, 20, 19)]);
printf("VIDEO_DIP_CTL DIP trans freq\t\t[0x%lx] %s\n",
BITS(dword, 17, 16), video_dip_trans[BITS(dword, 17, 16)]);
printf("VIDEO_DIP_CTL DIP buffer size\t\t%lu\n", BITS(dword, 11, 8));
printf("VIDEO_DIP_CTL DIP address\t\t%lu\n", BITS(dword, 3, 0));
dword = INREG(AUD_CONFIG);
printf("AUD_CONFIG pixel clock\t\t\t[0x%lx] %s\n", BITS(dword, 19, 16),
OPNAME(pixel_clock, BITS(dword, 19, 16)));
printf("AUD_CONFIG fabrication enabled\t\t%lu\n", BITS(dword, 2, 2));
printf("AUD_CONFIG professional use allowed\t%lu\n", BIT(dword, 1));
printf("AUD_CONFIG fuse enabled\t\t\t%lu\n", BIT(dword, 0));
dword = INREG(AUD_DEBUG);
printf("AUD_DEBUG function reset\t\t%lu\n", BIT(dword, 0));
dword = INREG(AUD_SUBN_CNT);
printf("AUD_SUBN_CNT starting node number\t0x%lx\n",
BITS(dword, 23, 16));
printf("AUD_SUBN_CNT total number of nodes\t0x%lx\n",
BITS(dword, 7, 0));
dword = INREG(AUD_SUBN_CNT2);
printf("AUD_SUBN_CNT2 starting node number\t0x%lx\n",
BITS(dword, 24, 16));
printf("AUD_SUBN_CNT2 total number of nodes\t0x%lx\n",
BITS(dword, 7, 0));
dword = INREG(AUD_FUNC_GRP);
printf("AUD_FUNC_GRP unsol capable\t\t%lu\n", BIT(dword, 8));
printf("AUD_FUNC_GRP node type\t\t\t0x%lx\n", BITS(dword, 7, 0));
dword = INREG(AUD_GRP_CAP);
printf("AUD_GRP_CAP beep 0\t\t\t%lu\n", BIT(dword, 16));
printf("AUD_GRP_CAP input delay\t\t\t%lu\n", BITS(dword, 11, 8));
printf("AUD_GRP_CAP output delay\t\t%lu\n", BITS(dword, 3, 0));
dword = INREG(AUD_PWRST);
printf("AUD_PWRST device power state\t\t%s\n",
power_state[BITS(dword, 5, 4)]);
printf("AUD_PWRST device power state setting\t%s\n",
power_state[BITS(dword, 1, 0)]);
dword = INREG(AUD_SUPPWR);
printf("AUD_SUPPWR support D0\t\t\t%lu\n", BIT(dword, 0));
printf("AUD_SUPPWR support D1\t\t\t%lu\n", BIT(dword, 1));
printf("AUD_SUPPWR support D2\t\t\t%lu\n", BIT(dword, 2));
printf("AUD_SUPPWR support D3\t\t\t%lu\n", BIT(dword, 3));
dword = INREG(AUD_OUT_CWCAP);
printf("AUD_OUT_CWCAP widget type\t\t0x%lx\n", BITS(dword, 23, 20));
printf("AUD_OUT_CWCAP sample delay\t\t0x%lx\n", BITS(dword, 19, 16));
printf("AUD_OUT_CWCAP channel count\t\t%lu\n",
BITS(dword, 15, 13) * 2 + BIT(dword, 0) + 1);
printf("AUD_OUT_CWCAP L-R swap\t\t\t%lu\n", BIT(dword, 11));
printf("AUD_OUT_CWCAP power control\t\t%lu\n", BIT(dword, 10));
printf("AUD_OUT_CWCAP digital\t\t\t%lu\n", BIT(dword, 9));
printf("AUD_OUT_CWCAP conn list\t\t\t%lu\n", BIT(dword, 8));
printf("AUD_OUT_CWCAP unsol\t\t\t%lu\n", BIT(dword, 7));
printf("AUD_OUT_CWCAP mute\t\t\t%lu\n", BIT(dword, 5));
printf("AUD_OUT_CWCAP format override\t\t%lu\n", BIT(dword, 4));
printf("AUD_OUT_CWCAP amp param override\t%lu\n", BIT(dword, 3));
printf("AUD_OUT_CWCAP out amp present\t\t%lu\n", BIT(dword, 2));
printf("AUD_OUT_CWCAP in amp present\t\t%lu\n", BIT(dword, 1));
dword = INREG(AUD_OUT_DIG_CNVT);
printf("AUD_OUT_DIG_CNVT SPDIF category\t\t0x%lx\n",
BITS(dword, 14, 8));
printf("AUD_OUT_DIG_CNVT SPDIF level\t\t%lu\n", BIT(dword, 7));
printf("AUD_OUT_DIG_CNVT professional\t\t%lu\n", BIT(dword, 6));
printf("AUD_OUT_DIG_CNVT non PCM\t\t%lu\n", BIT(dword, 5));
printf("AUD_OUT_DIG_CNVT copyright asserted\t%lu\n", BIT(dword, 4));
printf("AUD_OUT_DIG_CNVT filter preemphasis\t%lu\n", BIT(dword, 3));
printf("AUD_OUT_DIG_CNVT validity config\t%lu\n", BIT(dword, 2));
printf("AUD_OUT_DIG_CNVT validity flag\t\t%lu\n", BIT(dword, 1));
printf("AUD_OUT_DIG_CNVT digital enable\t\t%lu\n", BIT(dword, 0));
dword = INREG(AUD_OUT_CH_STR);
printf("AUD_OUT_CH_STR stream id\t\t0x%lx\n", BITS(dword, 7, 4));
printf("AUD_OUT_CH_STR lowest channel\t\t0x%lx\n", BITS(dword, 3, 0));
dword = INREG(AUD_OUT_STR_DESC);
printf("AUD_OUT_STR_DESC stream channels\t0x%lx\n", BITS(dword, 3, 0));
dword = INREG(AUD_PINW_CAP);
printf("AUD_PINW_CAP widget type\t\t0x%lx\n", BITS(dword, 23, 20));
printf("AUD_PINW_CAP sample delay\t\t0x%lx\n", BITS(dword, 19, 16));
printf("AUD_PINW_CAP channel count\t\t0x%lx\n",
BITS(dword, 15, 13) * 2 + BIT(dword, 0));
printf("AUD_PINW_CAP HDCP\t\t\t%lu\n", BIT(dword, 12));
printf("AUD_PINW_CAP L-R swap\t\t\t%lu\n", BIT(dword, 11));
printf("AUD_PINW_CAP power control\t\t%lu\n", BIT(dword, 10));
printf("AUD_PINW_CAP digital\t\t\t%lu\n", BIT(dword, 9));
printf("AUD_PINW_CAP conn list\t\t\t%lu\n", BIT(dword, 8));
printf("AUD_PINW_CAP unsol\t\t\t%lu\n", BIT(dword, 7));
printf("AUD_PINW_CAP mute\t\t\t%lu\n", BIT(dword, 5));
printf("AUD_PINW_CAP format override\t\t%lu\n", BIT(dword, 4));
printf("AUD_PINW_CAP amp param override\t\t%lu\n", BIT(dword, 3));
printf("AUD_PINW_CAP out amp present\t\t%lu\n", BIT(dword, 2));
printf("AUD_PINW_CAP in amp present\t\t%lu\n", BIT(dword, 1));
dword = INREG(AUD_PIN_CAP);
printf("AUD_PIN_CAP EAPD\t\t\t%lu\n", BIT(dword, 16));
printf("AUD_PIN_CAP HDMI\t\t\t%lu\n", BIT(dword, 7));
printf("AUD_PIN_CAP output\t\t\t%lu\n", BIT(dword, 4));
printf("AUD_PIN_CAP presence detect\t\t%lu\n", BIT(dword, 2));
dword = INREG(AUD_PINW_CNTR);
printf("AUD_PINW_CNTR mute status\t\t%lu\n", BIT(dword, 8));
printf("AUD_PINW_CNTR out enable\t\t%lu\n", BIT(dword, 6));
printf("AUD_PINW_CNTR amp mute status\t\t%lu\n", BIT(dword, 8));
printf("AUD_PINW_CNTR amp mute status\t\t%lu\n", BIT(dword, 8));
printf("AUD_PINW_CNTR stream type\t\t[0x%lx] %s\n",
BITS(dword, 2, 0), OPNAME(stream_type, BITS(dword, 2, 0)));
dword = INREG(AUD_PINW_UNSOLRESP);
printf("AUD_PINW_UNSOLRESP enable unsol resp\t%lu\n", BIT(dword, 31));
dword = INREG(AUD_CNTL_ST);
printf("AUD_CNTL_ST DIP audio enabled\t\t%lu\n", BIT(dword, 21));
printf("AUD_CNTL_ST DIP ACP enabled\t\t%lu\n", BIT(dword, 22));
printf("AUD_CNTL_ST DIP ISRCx enabled\t\t%lu\n", BIT(dword, 23));
printf("AUD_CNTL_ST DIP port select\t\t[0x%lx] %s\n",
BITS(dword, 30, 29), dip_port[BITS(dword, 30, 29)]);
printf("AUD_CNTL_ST DIP buffer index\t\t[0x%lx] %s\n",
BITS(dword, 20, 18), OPNAME(dip_index, BITS(dword, 20, 18)));
printf("AUD_CNTL_ST DIP trans freq\t\t[0x%lx] %s\n",
BITS(dword, 17, 16), dip_trans[BITS(dword, 17, 16)]);
printf("AUD_CNTL_ST DIP address\t\t\t%lu\n", BITS(dword, 3, 0));
printf("AUD_CNTL_ST CP ready\t\t\t%lu\n", BIT(dword, 15));
printf("AUD_CNTL_ST ELD valid\t\t\t%lu\n", BIT(dword, 14));
printf("AUD_CNTL_ST ELD ack\t\t\t%lu\n", BIT(dword, 4));
printf("AUD_CNTL_ST ELD bufsize\t\t\t%lu\n", BITS(dword, 13, 9));
printf("AUD_CNTL_ST ELD address\t\t\t%lu\n", BITS(dword, 8, 5));
dword = INREG(AUD_HDMIW_STATUS);
printf("AUD_HDMIW_STATUS CDCLK/DOTCLK underrun\t%lu\n", BIT(dword, 31));
printf("AUD_HDMIW_STATUS CDCLK/DOTCLK overrun\t%lu\n", BIT(dword, 30));
printf("AUD_HDMIW_STATUS BCLK/CDCLK underrun\t%lu\n", BIT(dword, 29));
printf("AUD_HDMIW_STATUS BCLK/CDCLK overrun\t%lu\n", BIT(dword, 28));
dword = INREG(AUD_CONV_CHCNT);
printf("AUD_CONV_CHCNT HDMI HBR enabled\t\t%lu\n", BITS(dword, 15, 14));
printf("AUD_CONV_CHCNT HDMI channel count\t%lu\n",
BITS(dword, 11, 8) + 1);
printf("AUD_CONV_CHCNT HDMI channel mapping:\n");
for (i = 0; i < 8; i++) {
OUTREG(AUD_CONV_CHCNT, i);
dword = INREG(AUD_CONV_CHCNT);
printf("\t\t\t\t\t[0x%x] %u => %lu \n", dword, i,
BITS(dword, 7, 4));
}
return 0;
}
