static byte siimage_ratemask (ide_drive_t *drive)
{
ide_hwif_t *hwif = HWIF(drive);
u8 mode = 0, scsc = 0;
unsigned long base = (unsigned long) hwif->hwif_data;
if (hwif->mmio)
scsc = hwif->INB(base + 0x4A);
else
pci_read_config_byte(hwif->pci_dev, 0x8A, &scsc);
if(is_sata(hwif))
{
if(strstr(drive->id->model, "Maxtor"))
return 3;
return 4;
}
if ((scsc & 0x30) == 0x10) /* 133 */
mode = 4;
else if ((scsc & 0x30) == 0x20) /* 2xPCI */
mode = 4;
else if ((scsc & 0x30) == 0x00) /* 100 */
mode = 3;
else /* Disabled ? */
BUG();
if (!eighty_ninty_three(drive))
mode = min(mode, (u8)1);
return mode;
}
static u8 aec62xx_ratemask (ide_drive_t *drive)
{
ide_hwif_t *hwif = HWIF(drive);
u8 mode;
switch(hwif->pci_dev->device) {
case PCI_DEVICE_ID_ARTOP_ATP865:
case PCI_DEVICE_ID_ARTOP_ATP865R:
#if 0
mode = (hwif->INB(hwif->dma_master) & 0x10) ? 4 : 3;
#else
mode = (hwif->INB(((hwif->channel) ?
hwif->mate->dma_status :
hwif->dma_status)) & 0x10) ? 4 : 3;
#endif
break;
case PCI_DEVICE_ID_ARTOP_ATP860:
case PCI_DEVICE_ID_ARTOP_ATP860R:
mode = 2;
break;
case PCI_DEVICE_ID_ARTOP_ATP850UF:
default:
return 1;
}
if (!eighty_ninty_three(drive))
mode = min(mode, (u8)1);
return mode;
}
static byte siimage_ratemask (ide_drive_t *drive)
{
ide_hwif_t *hwif = HWIF(drive);
u8 mode = 0, scsc = 0;
if (hwif->mmio)
scsc = hwif->INB(HWIFADDR(0x4A));
else
pci_read_config_byte(hwif->pci_dev, 0x8A, &scsc);
switch(hwif->pci_dev->device) {
case PCI_DEVICE_ID_SII_3112:
return 4;
case PCI_DEVICE_ID_SII_680:
if ((scsc & 0x30) == 0x10) /* 133 */
mode = 4;
else if ((scsc & 0x30) == 0x20) /* 2xPCI */
mode = 4;
else if ((scsc & 0x30) == 0x00) /* 100 */
mode = 3;
else /* Disabled ? */
BUG();
break;
default: return 0;
}
if (!eighty_ninty_three(drive))
mode = min(mode, (u8)1);
return mode;
}
static u8 slc90e66_ratemask (ide_drive_t *drive)
{
u8 mode = 2;
if (!eighty_ninty_three(drive))
mode = min(mode, (u8)1);
return mode;
}
static u8 pdcnew_ratemask(ide_drive_t *drive)
{
u8 mode = max_dma_rate(HWIF(drive)->pci_dev);
if (!eighty_ninty_three(drive))
mode = min_t(u8, mode, 1);
return mode;
}
static u8 piix_ratemask (ide_drive_t *drive)
{
struct pci_dev *dev = HWIF(drive)->pci_dev;
u8 mode;
switch(dev->device) {
case PCI_DEVICE_ID_INTEL_82801EB_1:
mode = 3;
break;
/* UDMA 100 capable */
case PCI_DEVICE_ID_INTEL_82801BA_8:
case PCI_DEVICE_ID_INTEL_82801BA_9:
case PCI_DEVICE_ID_INTEL_82801CA_10:
case PCI_DEVICE_ID_INTEL_82801CA_11:
case PCI_DEVICE_ID_INTEL_82801E_11:
case PCI_DEVICE_ID_INTEL_82801DB_1:
case PCI_DEVICE_ID_INTEL_82801DB_10:
case PCI_DEVICE_ID_INTEL_82801DB_11:
case PCI_DEVICE_ID_INTEL_82801EB_11:
case PCI_DEVICE_ID_INTEL_ESB_2:
case PCI_DEVICE_ID_INTEL_ICH6_19:
case PCI_DEVICE_ID_INTEL_ICH7_21:
case PCI_DEVICE_ID_INTEL_ESB2_18:
case PCI_DEVICE_ID_INTEL_ICH8_6:
mode = 3;
break;
/* UDMA 66 capable */
case PCI_DEVICE_ID_INTEL_82801AA_1:
case PCI_DEVICE_ID_INTEL_82372FB_1:
mode = 2;
break;
/* UDMA 33 capable */
case PCI_DEVICE_ID_INTEL_82371AB:
case PCI_DEVICE_ID_INTEL_82443MX_1:
case PCI_DEVICE_ID_INTEL_82451NX:
case PCI_DEVICE_ID_INTEL_82801AB_1:
return 1;
/* Non UDMA capable (MWDMA2) */
case PCI_DEVICE_ID_INTEL_82371SB_1:
case PCI_DEVICE_ID_INTEL_82371FB_1:
case PCI_DEVICE_ID_INTEL_82371FB_0:
case PCI_DEVICE_ID_INTEL_82371MX:
default:
return 0;
}
/*
* If we are UDMA66 capable fall back to UDMA33
* if the drive cannot see an 80pin cable.
*/
if (!eighty_ninty_three(drive))
mode = min(mode, (u8)1);
return mode;
}
static int config_chipset_for_dma (ide_drive_t *drive, byte ultra)
{
struct hd_driveid *id = drive->id;
ide_hwif_t *hwif = HWIF(drive);
struct pci_dev *dev = hwif->pci_dev;
unsigned long high_16 = pci_resource_start(dev, 4);
unsigned long dma_base = hwif->dma_base;
byte unit = (drive->select.b.unit & 0x01);
unsigned int drive_conf;
byte drive_pci;
byte test1, test2, speed = -1;
byte AP;
unsigned short EP;
byte CLKSPD = IN_BYTE(high_16 + 0x11);
byte udma_33 = ultra ? (inb(high_16 + 0x001f) & 1) : 0;
byte udma_66 = ((eighty_ninty_three(drive)) && udma_33) ? 1 : 0;
byte udma_100 = (((dev->device == PCI_DEVICE_ID_PROMISE_20265) || (dev->device == PCI_DEVICE_ID_PROMISE_20267)) && udma_66) ? 1 : 0;
/*
* Set the control register to use the 66Mhz system
* clock for UDMA 3/4 mode operation. If one drive on
* a channel is U66 capable but the other isn't we
* fall back to U33 mode. The BIOS INT 13 hooks turn
* the clock on then off for each read/write issued. I don't
* do that here because it would require modifying the
* kernel, seperating the fop routines from the kernel or
* somehow hooking the fops calls. It may also be possible to
* leave the 66Mhz clock on and readjust the timing
* parameters.
*/
byte mask = hwif->channel ? 0x08 : 0x02;
unsigned short c_mask = hwif->channel ? (1<<11) : (1<<10);
byte ultra_66 = ((id->dma_ultra & 0x0010) ||
(id->dma_ultra & 0x0008)) ? 1 : 0;
byte ultra_100 = ((id->dma_ultra & 0x0020) ||
(id->dma_ultra & 0x0010) ||
(id->dma_ultra & 0x0008)) ? 1 : 0;
pci_read_config_word(dev, 0x50, &EP);
if (((ultra_66) || (ultra_100)) && (EP & c_mask)) {
#ifdef DEBUG
printk("ULTRA66: %s channel of Ultra 66 requires an 80-pin cable for Ultra66 operation.\n", hwif->channel ? "Secondary", "Primary");
printk(" Switching to Ultra33 mode.\n");
#endif /* DEBUG */
/* Primary : zero out second bit */
/* Secondary : zero out fourth bit */
OUT_BYTE(CLKSPD & ~mask, (high_16 + 0x11));
} else {
int ide_ata66_check (ide_drive_t *drive, ide_task_t *args)
{
if ((args->tfRegister[IDE_COMMAND_OFFSET] == WIN_SETFEATURES) &&
(args->tfRegister[IDE_SECTOR_OFFSET] > XFER_UDMA_2) &&
(args->tfRegister[IDE_FEATURE_OFFSET] == SETFEATURES_XFER)) {
if (eighty_ninty_three(drive) == 0) {
printk(KERN_WARNING "%s: UDMA speeds >UDMA33 cannot "
"be set\n", drive->name);
return 1;
}
}
return 0;
}
static u8 cmd64x_ratemask (ide_drive_t *drive)
{
struct pci_dev *dev = HWIF(drive)->pci_dev;
u8 mode = 0;
switch(dev->device) {
case PCI_DEVICE_ID_CMD_649:
mode = 3;
break;
case PCI_DEVICE_ID_CMD_648:
mode = 2;
break;
case PCI_DEVICE_ID_CMD_643:
return 0;
case PCI_DEVICE_ID_CMD_646:
{
unsigned int class_rev = 0;
pci_read_config_dword(dev,
PCI_CLASS_REVISION, &class_rev);
class_rev &= 0xff;
/*
* UltraDMA only supported on PCI646U and PCI646U2, which
* correspond to revisions 0x03, 0x05 and 0x07 respectively.
* Actually, although the CMD tech support people won't
* tell me the details, the 0x03 revision cannot support
* UDMA correctly without hardware modifications, and even
* then it only works with Quantum disks due to some
* hold time assumptions in the 646U part which are fixed
* in the 646U2.
*
* So we only do UltraDMA on revision 0x05 and 0x07 chipsets.
*/
switch(class_rev) {
case 0x07:
case 0x05:
return 1;
case 0x03:
case 0x01:
default:
return 0;
}
}
}
if (!eighty_ninty_three(drive))
mode = min(mode, (u8)1);
return mode;
}
static u8 svwks_ratemask (ide_drive_t *drive)
{
struct pci_dev *dev = HWIF(drive)->pci_dev;
u8 mode;
if (!svwks_revision)
pci_read_config_byte(dev, PCI_REVISION_ID, &svwks_revision);
if (dev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) {
u32 reg = 0;
if (isa_dev)
pci_read_config_dword(isa_dev, 0x64, ®);
/*
* Don't enable UDMA on disk devices for the moment
*/
if(drive->media == ide_disk)
return 0;
/* Check the OSB4 DMA33 enable bit */
return ((reg & 0x00004000) == 0x00004000) ? 1 : 0;
}
else if (dev->device == PCI_DEVICE_ID_SERVERWORKS_BCM7038) {
return 3; /* tht Takes 3=UDMA5 */
} else if (svwks_revision < SVWKS_CSB5_REVISION_NEW) {
return 1;
} else if (svwks_revision >= SVWKS_CSB5_REVISION_NEW) {
u8 btr = 0;
pci_read_config_byte(dev, 0x5A, &btr);
mode = btr & 0x3;
if (!eighty_ninty_three(drive))
mode = min(mode, (u8)1);
/* If someone decides to do UDMA133 on CSB5 the same
issue will bite so be inclusive */
if (mode > 2 && check_in_drive_lists(drive, svwks_bad_ata100))
mode = 2;
}
if (((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
(dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) &&
(!(PCI_FUNC(dev->devfn) & 1)))
mode = 2;
return mode;
}
static u8 pdcnew_ratemask (ide_drive_t *drive)
{
u8 mode;
switch(HWIF(drive)->pci_dev->device) {
case PCI_DEVICE_ID_PROMISE_20277:
case PCI_DEVICE_ID_PROMISE_20276:
case PCI_DEVICE_ID_PROMISE_20275:
case PCI_DEVICE_ID_PROMISE_20271:
case PCI_DEVICE_ID_PROMISE_20269:
mode = 4;
break;
case PCI_DEVICE_ID_PROMISE_20270:
case PCI_DEVICE_ID_PROMISE_20268:
mode = 3;
break;
default:
return 0;
}
if (!eighty_ninty_three(drive))
mode = min(mode, (u8)1);
return mode;
}
int ide_cmd_ioctl (ide_drive_t *drive, unsigned int cmd, unsigned long arg)
{
u8 *buf = NULL;
int bufsize = 0, err = 0;
u8 args[4], xfer_rate = 0;
ide_task_t tfargs;
struct ide_taskfile *tf = &tfargs.tf;
struct hd_driveid *id = drive->id;
if (NULL == (void *) arg) {
struct request rq;
ide_init_drive_cmd(&rq);
rq.cmd_type = REQ_TYPE_ATA_TASKFILE;
return ide_do_drive_cmd(drive, &rq, ide_wait);
}
if (copy_from_user(args, (void __user *)arg, 4))
return -EFAULT;
memset(&tfargs, 0, sizeof(ide_task_t));
tf->feature = args[2];
if (args[0] == WIN_SMART) {
tf->nsect = args[3];
tf->lbal = args[1];
tf->lbam = 0x4f;
tf->lbah = 0xc2;
tfargs.tf_flags = IDE_TFLAG_OUT_TF | IDE_TFLAG_IN_NSECT;
} else {
tf->nsect = args[1];
tfargs.tf_flags = IDE_TFLAG_OUT_FEATURE |
IDE_TFLAG_OUT_NSECT | IDE_TFLAG_IN_NSECT;
}
tf->command = args[0];
tfargs.data_phase = args[3] ? TASKFILE_IN : TASKFILE_NO_DATA;
if (args[3]) {
tfargs.tf_flags |= IDE_TFLAG_IO_16BIT;
bufsize = SECTOR_WORDS * 4 * args[3];
buf = kzalloc(bufsize, GFP_KERNEL);
if (buf == NULL)
return -ENOMEM;
}
if (tf->command == WIN_SETFEATURES &&
tf->feature == SETFEATURES_XFER &&
tf->nsect >= XFER_SW_DMA_0 &&
(id->dma_ultra || id->dma_mword || id->dma_1word)) {
xfer_rate = args[1];
if (tf->nsect > XFER_UDMA_2 && !eighty_ninty_three(drive)) {
printk(KERN_WARNING "%s: UDMA speeds >UDMA33 cannot "
"be set\n", drive->name);
goto abort;
}
}
err = ide_raw_taskfile(drive, &tfargs, buf, args[3]);
args[0] = tf->status;
args[1] = tf->error;
args[2] = tf->nsect;
if (!err && xfer_rate) {
/* active-retuning-calls future */
ide_set_xfer_rate(drive, xfer_rate);
ide_driveid_update(drive);
}
abort:
if (copy_to_user((void __user *)arg, &args, 4))
err = -EFAULT;
if (buf) {
if (copy_to_user((void __user *)(arg + 4), buf, bufsize))
err = -EFAULT;
kfree(buf);
}
return err;
}
static inline u8 tc86c001_ratemask(ide_drive_t *drive)
{
return eighty_ninty_three(drive) ? 2 : 1;
}
static u8 palm_bk3710_ratemask(ide_drive_t *drive)
{
if (!eighty_ninty_three(drive))
return 1;
return HWIF(drive)->ultra_mask & 0x20 ? 3 : 2;
}
