/**
* Emit a typed surface read opcode. \p dims determines the number of
* components of the address and \p size the number of components of the
* returned value.
*/
fs_reg
emit_typed_read(const fs_builder &bld, const fs_reg &surface,
const fs_reg &addr, unsigned dims, unsigned size)
{
return emit_send(bld, SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL,
addr, fs_reg(), surface, dims, size, size);
}
/**
* Emit a typed surface atomic opcode. \p dims determines the number of
* components of the address and \p rsize the number of components of
* the returned value (either zero or one).
*/
src_reg
emit_typed_atomic(const vec4_builder &bld,
const src_reg &surface, const src_reg &addr,
const src_reg &src0, const src_reg &src1,
unsigned dims, unsigned rsize, unsigned op,
brw_predicate pred)
{
const bool has_simd4x2 = (bld.shader->devinfo->gen >= 8 ||
bld.shader->devinfo->is_haswell);
/* Zip the components of both sources, they are represented as the X
* and Y components of the same vector.
*/
const unsigned size = (src0.file != BAD_FILE) + (src1.file != BAD_FILE);
const dst_reg srcs = bld.vgrf(BRW_REGISTER_TYPE_UD);
if (size >= 1)
bld.MOV(writemask(srcs, WRITEMASK_X), src0);
if (size >= 2)
bld.MOV(writemask(srcs, WRITEMASK_Y), src1);
return emit_send(bld, SHADER_OPCODE_TYPED_ATOMIC,
emit_typed_message_header(bld),
emit_insert(bld, addr, dims, has_simd4x2),
has_simd4x2 ? 1 : dims,
emit_insert(bld, src_reg(srcs), size, has_simd4x2),
has_simd4x2 ? 1 : size,
surface, op, rsize, pred);
}
/**
* Emit a typed surface write opcode. \p dims determines the number of
* components of the address and \p size the number of components of the
* argument.
*/
void
emit_typed_write(const fs_builder &bld, const fs_reg &surface,
const fs_reg &addr, const fs_reg &src,
unsigned dims, unsigned size)
{
emit_send(bld, SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL,
addr, src, surface, dims, size, 0);
}
/**
* Emit an untyped surface write opcode. \p dims determines the number
* of components of the address and \p size the number of components of
* the argument.
*/
void
emit_untyped_write(const fs_builder &bld, const fs_reg &surface,
const fs_reg &addr, const fs_reg &src,
unsigned dims, unsigned size,
brw_predicate pred)
{
emit_send(bld, SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL,
addr, src, surface, dims, size, 0, pred);
}
/**
* Emit an untyped surface read opcode. \p dims determines the number
* of components of the address and \p size the number of components of
* the returned value.
*/
src_reg
emit_untyped_read(const vec4_builder &bld,
const src_reg &surface, const src_reg &addr,
unsigned dims, unsigned size,
brw_predicate pred)
{
return emit_send(bld, SHADER_OPCODE_UNTYPED_SURFACE_READ, src_reg(),
emit_insert(bld, addr, dims, true), 1,
src_reg(), 0,
surface, size, 1, pred);
}
/**
* Emit a typed surface write opcode. \p dims determines the number of
* components of the address and \p size the number of components of the
* argument.
*/
void
emit_typed_write(const vec4_builder &bld, const src_reg &surface,
const src_reg &addr, const src_reg &src,
unsigned dims, unsigned size)
{
const bool has_simd4x2 = (bld.shader->devinfo->gen >= 8 ||
bld.shader->devinfo->is_haswell);
emit_send(bld, SHADER_OPCODE_TYPED_SURFACE_WRITE,
emit_typed_message_header(bld),
emit_insert(bld, addr, dims, has_simd4x2),
has_simd4x2 ? 1 : dims,
emit_insert(bld, src, size, has_simd4x2),
has_simd4x2 ? 1 : size,
surface, size, 0);
}
/**
* Emit an untyped surface write opcode. \p dims determines the number
* of components of the address and \p size the number of components of
* the argument.
*/
void
emit_untyped_write(const vec4_builder &bld, const src_reg &surface,
const src_reg &addr, const src_reg &src,
unsigned dims, unsigned size,
brw_predicate pred)
{
const bool has_simd4x2 = (bld.shader->devinfo->gen >= 8 ||
bld.shader->devinfo->is_haswell);
emit_send(bld, SHADER_OPCODE_UNTYPED_SURFACE_WRITE, src_reg(),
emit_insert(bld, addr, dims, has_simd4x2),
has_simd4x2 ? 1 : dims,
emit_insert(bld, src, size, has_simd4x2),
has_simd4x2 ? 1 : size,
surface, size, 0, pred);
}
/**
* Emit a typed surface read opcode. \p dims determines the number of
* components of the address and \p size the number of components of the
* returned value.
*/
src_reg
emit_typed_read(const vec4_builder &bld, const src_reg &surface,
const src_reg &addr, unsigned dims, unsigned size)
{
const bool has_simd4x2 = (bld.shader->devinfo->gen >= 8 ||
bld.shader->devinfo->is_haswell);
const src_reg tmp =
emit_send(bld, SHADER_OPCODE_TYPED_SURFACE_READ,
emit_typed_message_header(bld),
emit_insert(bld, addr, dims, has_simd4x2),
has_simd4x2 ? 1 : dims,
src_reg(), 0,
surface, size,
has_simd4x2 ? 1 : size);
return emit_extract(bld, tmp, size, has_simd4x2);
}
/**
* Emit an untyped surface atomic opcode. \p dims determines the number
* of components of the address and \p rsize the number of components of
* the returned value (either zero or one).
*/
fs_reg
emit_untyped_atomic(const fs_builder &bld,
const fs_reg &surface, const fs_reg &addr,
const fs_reg &src0, const fs_reg &src1,
unsigned dims, unsigned rsize, unsigned op,
brw_predicate pred)
{
/* FINISHME: Factor out this frequently recurring pattern into a
* helper function.
*/
const unsigned n = (src0.file != BAD_FILE) + (src1.file != BAD_FILE);
const fs_reg srcs[] = { src0, src1 };
const fs_reg tmp = bld.vgrf(BRW_REGISTER_TYPE_UD, n);
bld.LOAD_PAYLOAD(tmp, srcs, n, 0);
return emit_send(bld, SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL,
addr, tmp, surface, dims, op, rsize, pred);
}
