static inline void pwm_pwclk_stop(int ch)
{
if (ch == EMXX_PWM_CH0)
emxx_close_clockgate(EMXX_CLK_PWM0);
else if (ch == EMXX_PWM_CH1)
emxx_close_clockgate(EMXX_CLK_PWM1);
}
int emxx_timer_stop(unsigned int timer)
{
int ret = 0;
unsigned int tm_delay;
unsigned long flags;
struct timer_reg_t *reg;
ret = check_validity_channel(timer);
if (ret != 0)
return ret;
/* delay value set */
tm_delay = TIMER_DELAY(TIMER_CLOCK_TICK_RATE_PLL3);
reg = tm_reg[TIMER_TG0 + timer].reg;
spin_lock_irqsave(&timer_spinlock, flags);
/* Timer stop */
reg->tm_op = TSTOP;
udelay(tm_delay);
emxx_close_clockgate(tm_reg[TIMER_TG0 + timer].clkdev);
tg_tm_op[timer] = 0;
spin_unlock_irqrestore(&timer_spinlock, flags);
return 0;
}
/*
* take a local timer down
*/
void local_timer_stop(void)
{
struct timer_reg_t *reg = tm_reg[TIMER_SYSTEM2].reg;
reg->tm_op = TSTOP;
udelay(TIMER_DELAY(TIMER_CLOCK_TICK_RATE_PLL3));
emxx_close_clockgate(tm_reg[TIMER_SYSTEM2].clkdev);
}
void emxx_pm_idle(void)
{
local_irq_disable();
local_fiq_disable();
if (need_resched()) {
local_fiq_enable();
local_irq_enable();
return;
}
pm_idle_count++;
if (sleep_while_idle_enable && !suspend_disable) {
#ifdef CONFIG_SMP
if ((0 == hard_smp_processor_id()) &&
!(inl(SMU_CLKSTOPSIG_ST) & PWSTATE_PD_NE1)) {
/* cpu1 wfi */
emxx_close_clockgate(EMXX_CLK_TI1);
#endif
if (emxx_can_sleep()) {
emxx_sleep_while_idle = 1;
if (0 == emxx_pm_suspend(PM_SUSPEND_STANDBY)) {
emxx_add_neigh_timer();
emxx_add_timer_writeback();
emxx_add_workqueue_timer();
emxx_sleep_while_idle = 0;
sleep_while_idle_count++;
#ifdef CONFIG_SMP
emxx_open_clockgate(EMXX_CLK_TI1);
#endif
set_need_resched();
local_fiq_enable();
local_irq_enable();
return;
}
emxx_add_neigh_timer();
emxx_add_timer_writeback();
emxx_add_workqueue_timer();
emxx_sleep_while_idle = 0;
}
#ifdef CONFIG_SMP
emxx_open_clockgate(EMXX_CLK_TI1);
}
#endif
}
arch_idle();
local_fiq_enable();
local_irq_enable();
}
static void _emxx_hc_stop(struct usb_hcd *hcd)
{
_ahb_pci_bridge_exit();
/* Reset State ON */
emxx_reset_device(EMXX_RST_USB0);
#ifdef CONFIG_MACH_EMGR
emxx_reset_device(EMXX_RST_USB1);
#endif
/* Stop Clock */
#ifdef CONFIG_MACH_EMEV
emxx_close_clockgate(EMXX_CLK_USB0 | EMXX_CLK_USB_PCI);
#elif defined(CONFIG_MACH_EMGR)
emxx_close_clockgate(EMXX_CLK_USB0 | EMXX_CLK_USB1 | EMXX_CLK_USB_PCI);
#endif
#ifdef CONFIG_MACH_EMGR
writel(0, SMU_USBPHY_HOST_FUNC_SEL);
writel(readl(SMU_OSC1CTRL1) | 0x1, SMU_OSC1CTRL1);
#endif
}
/*
* DeInit CFI module
*/
static void emxx_cfi_disable(void)
{
emxx_reset_device(EMXX_RST_CFI);
emxx_close_clockgate(EMXX_CLK_CFI | EMXX_CLK_CFI_H);
#ifdef CONFIG_MACH_EMEV
if ((system_rev & EMXX_REV_MASK) != EMXX_REV_ES1) {
#endif /* CONFIG_MACH_EMEV */
/* card power off */
pwc_reg_write(DA9052_LDO8_REG, 0x00);
mdelay(2);
#ifdef CONFIG_MACH_EMEV
}
#endif /* CONFIG_MACH_EMEV */
}
static ssize_t sleep_while_idle_store(struct kobject *kobj,
struct kobj_attribute *attr, const char *buf, size_t n)
{
int value;
if (sscanf(buf, "%d", &value) != 1 ||
(value != 0 && value != 1)) {
printk(KERN_ERR "idle_sleep_store: Invalid value\n");
return -EINVAL;
}
if (value)
emxx_open_clockgate(EMXX_CLK_TI2);
else
emxx_close_clockgate(EMXX_CLK_TI2);
sleep_while_idle_enable = value;
return n;
}
int emxx_timer_set_period(unsigned int timer, unsigned int usecs)
{
int ret = 0, regval = 0;
unsigned long flags;
unsigned int tm_delay;
struct timer_reg_t *reg;
ret = check_validity_channel(timer);
if (ret != 0)
return ret;
if ((usecs < TIMER_MIN_USECS) || (TIMER_MAX_USECS < usecs))
return -EINVAL;
/* 4clk x2 wait value */
tm_delay = TIMER_DELAY(TIMER_CLOCK_TICK_RATE_PLL3) * 2;
reg = tm_reg[TIMER_TG0 + timer].reg;
spin_lock_irqsave(&timer_spinlock, flags);
if (reg->tm_op & TSTART) {
spin_unlock_irqrestore(&timer_spinlock, flags);
return -EBUSY;
}
emxx_open_clockgate(tm_reg[TIMER_TG0 + timer].clkdev);
udelay(tm_delay);
tm_param[TIMER_TG0 + timer].usecs = usecs;
/* set counter */
regval = get_count_value(timer, usecs);
reg->tm_set = regval;
emxx_close_clockgate(tm_reg[TIMER_TG0 + timer].clkdev);
spin_unlock_irqrestore(&timer_spinlock, flags);
return 0;
}
/*
* Init CFI module
*/
static void emxx_cfi_enable(void)
{
u32 val;
#ifdef CONFIG_MACH_EMEV
if ((system_rev & EMXX_REV_MASK) != EMXX_REV_ES1) {
#endif /* CONFIG_MACH_EMEV */
emxx_reset_device(EMXX_RST_CFI);
emxx_close_clockgate(EMXX_CLK_CFI | EMXX_CLK_CFI_H);
/* card power on */
pwc_reg_write(DA9052_LDO8_REG, 0x6A);
udelay(300);
#ifdef CONFIG_MACH_EMEV
}
#endif /* CONFIG_MACH_EMEV */
emxx_open_clockgate(EMXX_CLK_CFI | EMXX_CLK_CFI_H);
emxx_unreset_device(EMXX_RST_CFI);
/* config the CFI work in the PIO mode, hardware reset, 16 bit data */
writel(CFI_CONTROL_0_IDE, EMXX_CFI_CONTROL_0);
/* hardware reset release in CFI module */
val = readl(EMXX_CFI_CONTROL_0) | CFI_CONTROL_0_HRST;
writel(val, EMXX_CFI_CONTROL_0);
/* disable all the interrupts */
writel(0x00000000, EMXX_CFI_CONTROL_1);
/* clear all the interrupt */
writel(0xffffffff, EMXX_CFI_INTERRUPT);
/* PIO mode access timing confige */
writel(0x00001319, EMXX_CFI_TIMING_1);
/* setting for PIO */
val = readl(EMXX_CFI_BUSIF_CTRL) & 0xFFFFFF00;
writel(val | 0x00000062 | emxx_cfi_burst_mode, EMXX_CFI_BUSIF_CTRL);
}
void timer_set_clock(unsigned int mode)
{
int i;
unsigned int count;
unsigned int tm_delay;
struct timer_reg_t *reg;
static unsigned int timer_pmu_flag;
/* delay value set */
tm_delay = TIMER_DELAY(TIMER_CLOCK_TICK_RATE_32K);
switch (mode) {
case TIMER_SUSPEND:
/* close clockgate */
emxx_close_clockgate(tm_reg[TIMER_SYSTEM].clkdev);
emxx_close_clockgate(tm_reg[TIMER_WDT].clkdev);
emxx_close_clockgate(tm_reg[TIMER_DSP].clkdev);
timer_pmu_flag = emxx_get_clockgate(tm_reg[TIMER_PMU].clkdev);
if (timer_pmu_flag)
emxx_close_clockgate(tm_reg[TIMER_PMU].clkdev);
for (i = 0; i < TIMER_TG_MAX_NUM; i++) {
if (tg_tm_op[i] == 1)
emxx_close_clockgate(
tm_reg[TIMER_TG0 + i].clkdev);
}
break;
case TIMER_RESUME:
emxx_open_clockgate(tm_reg[TIMER_SYSTEM].clkdev);
emxx_open_clockgate(tm_reg[TIMER_WDT].clkdev);
emxx_open_clockgate(tm_reg[TIMER_DSP].clkdev);
if (timer_pmu_flag)
emxx_open_clockgate(tm_reg[TIMER_PMU].clkdev);
for (i = 0; i < TIMER_TG_MAX_NUM; i++) {
if (tg_tm_op[i] == 1)
emxx_open_clockgate(
tm_reg[TIMER_TG0 + i].clkdev);
}
break;
case TIMER_INIT:
emxx_open_clockgate(EMXX_CLK_TIM_P);
emxx_open_clockgate(tm_reg[TIMER_SYSTEM].clkdev);
emxx_open_clockgate(tm_reg[TIMER_DSP].clkdev);
emxx_open_clockgate(tm_reg[TIMER_PMU].clkdev);
emxx_unreset_device(tm_reg[TIMER_SYSTEM].rstdev);
emxx_unreset_device(tm_reg[TIMER_DSP].rstdev);
emxx_unreset_device(tm_reg[TIMER_PMU].rstdev);
for (i = 0; i < TIMER_TG_MAX_NUM; i++)
emxx_unreset_device(tm_reg[TIMER_TG0 + i].rstdev);
reg = tm_reg[TIMER_SYSTEM].reg;
reg->tm_op = TSTOP;
reg->tm_clr = TCR_CLR;
reg = tm_reg[TIMER_WDT].reg;
reg->tm_op = TSTOP;
reg->tm_clr = TCR_CLR;
reg = tm_reg[TIMER_DSP].reg;
reg->tm_op = TSTOP;
reg->tm_clr = TCR_CLR;
reg->tm_set = TIMER_INTERVAL_DSP;
reg = tm_reg[TIMER_PMU].reg;
reg->tm_op = TSTOP;
reg->tm_clr = TCR_CLR;
emxx_close_clockgate(tm_reg[TIMER_PMU].clkdev);
/* select TIN clock */
writel(TINTIN_SEL_PLL3 | TWNTIN_SEL_32K, SMU_TWI0TIN_SEL);
writel(TINTIN_SEL_PLL3 | TWNTIN_SEL_PLL3, SMU_TWI1TIN_SEL);
writel(TINTIN_SEL_32K | TWNTIN_SEL_PLL3, SMU_TWI2TIN_SEL);
writel(TINTIN_SEL_32K | TWNTIN_SEL_PLL3, SMU_TWI3TIN_SEL);
writel(TINTIN_SEL_32K, SMU_TW4TIN_SEL);
writel(TGNTIN_SEL_PLL3, SMU_TGNTIN_SEL);
/* DIVTIMTIN Register set */
writel(SMU_PLLSEL_PLL3 | SMU_DIV(40), SMU_TIMCLKDIV);
for (i = 0; i < TIMER_TG_MAX_NUM; i++) {
count = get_count_value(i,
tm_param[TIMER_TG0 + i].usecs);
reg = tm_reg[TIMER_TG0 + i].reg;
reg->tm_set = count;
}
break;
default:
printk(KERN_INFO "%s(): set clock error mode = %d.\n",
__func__, mode);
break;
}
}
static inline void pwm_clock_stop(void)
{
emxx_close_clockgate(EMXX_CLK_PWM1);
emxx_close_clockgate(EMXX_CLK_PWM0);
emxx_close_clockgate(EMXX_CLK_PWM_P);
}
