void
printcpuinfo(void)
{
u_int regs[4], i;
char *brand;
cpu_class = i386_cpus[cpu].cpu_class;
kprintf("CPU: ");
strncpy(cpu_model, i386_cpus[cpu].cpu_name, sizeof (cpu_model));
/* Check for extended CPUID information and a processor name. */
init_exthigh();
if (cpu_exthigh >= 0x80000004) {
brand = cpu_brand;
for (i = 0x80000002; i < 0x80000005; i++) {
do_cpuid(i, regs);
memcpy(brand, regs, sizeof(regs));
brand += sizeof(regs);
}
}
if (cpu_vendor_id == CPU_VENDOR_INTEL) {
if ((cpu_id & 0xf00) > 0x300) {
u_int brand_index;
cpu_model[0] = '\0';
switch (cpu_id & 0x3000) {
case 0x1000:
strcpy(cpu_model, "Overdrive ");
break;
case 0x2000:
strcpy(cpu_model, "Dual ");
break;
}
switch (cpu_id & 0xf00) {
case 0x400:
strcat(cpu_model, "i486 ");
/* Check the particular flavor of 486 */
switch (cpu_id & 0xf0) {
case 0x00:
case 0x10:
strcat(cpu_model, "DX");
break;
case 0x20:
strcat(cpu_model, "SX");
break;
case 0x30:
strcat(cpu_model, "DX2");
break;
case 0x40:
strcat(cpu_model, "SL");
break;
case 0x50:
strcat(cpu_model, "SX2");
break;
case 0x70:
strcat(cpu_model,
"DX2 Write-Back Enhanced");
break;
case 0x80:
strcat(cpu_model, "DX4");
break;
}
break;
case 0x500:
/* Check the particular flavor of 586 */
strcat(cpu_model, "Pentium");
switch (cpu_id & 0xf0) {
case 0x00:
strcat(cpu_model, " A-step");
break;
case 0x10:
strcat(cpu_model, "/P5");
break;
case 0x20:
strcat(cpu_model, "/P54C");
break;
case 0x30:
strcat(cpu_model, "/P24T");
break;
case 0x40:
strcat(cpu_model, "/P55C");
break;
case 0x70:
strcat(cpu_model, "/P54C");
break;
case 0x80:
strcat(cpu_model, "/P55C (quarter-micron)");
break;
default:
/* nothing */
break;
}
#if defined(I586_CPU) && !defined(NO_F00F_HACK)
/*
* XXX - If/when Intel fixes the bug, this
* should also check the version of the
* CPU, not just that it's a Pentium.
*/
has_f00f_bug = 1;
#endif
break;
case 0x600:
/* Check the particular flavor of 686 */
switch (cpu_id & 0xf0) {
case 0x00:
strcat(cpu_model, "Pentium Pro A-step");
break;
case 0x10:
strcat(cpu_model, "Pentium Pro");
break;
case 0x30:
case 0x50:
case 0x60:
strcat(cpu_model,
"Pentium II/Pentium II Xeon/Celeron");
cpu = CPU_PII;
break;
case 0x70:
case 0x80:
case 0xa0:
case 0xb0:
strcat(cpu_model,
"Pentium III/Pentium III Xeon/Celeron");
cpu = CPU_PIII;
break;
default:
strcat(cpu_model, "Unknown 80686");
break;
}
break;
case 0xf00:
strcat(cpu_model, "Pentium 4");
cpu = CPU_P4;
break;
default:
strcat(cpu_model, "unknown");
break;
}
/*
* If we didn't get a brand name from the extended
* CPUID, try to look it up in the brand table.
*/
if (cpu_high > 0 && *cpu_brand == '\0') {
brand_index = cpu_procinfo & CPUID_BRAND_INDEX;
if (brand_index <= MAX_BRAND_INDEX &&
cpu_brandtable[brand_index] != NULL)
strcpy(cpu_brand,
cpu_brandtable[brand_index]);
}
}
} else if (cpu_vendor_id == CPU_VENDOR_AMD) {
/*
* Values taken from AMD Processor Recognition
* http://www.amd.com/K6/k6docs/pdf/20734g.pdf
* (also describes ``Features'' encodings.
*/
strcpy(cpu_model, "AMD ");
switch (cpu_id & 0xFF0) {
case 0x410:
strcat(cpu_model, "Standard Am486DX");
break;
case 0x430:
strcat(cpu_model, "Enhanced Am486DX2 Write-Through");
break;
case 0x470:
strcat(cpu_model, "Enhanced Am486DX2 Write-Back");
break;
case 0x480:
strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Through");
break;
case 0x490:
strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Back");
break;
case 0x4E0:
strcat(cpu_model, "Am5x86 Write-Through");
break;
case 0x4F0:
strcat(cpu_model, "Am5x86 Write-Back");
break;
case 0x500:
strcat(cpu_model, "K5 model 0");
tsc_is_broken = 1;
break;
case 0x510:
strcat(cpu_model, "K5 model 1");
break;
case 0x520:
strcat(cpu_model, "K5 PR166 (model 2)");
break;
case 0x530:
strcat(cpu_model, "K5 PR200 (model 3)");
break;
case 0x560:
strcat(cpu_model, "K6");
break;
case 0x570:
strcat(cpu_model, "K6 266 (model 1)");
break;
case 0x580:
strcat(cpu_model, "K6-2");
break;
case 0x590:
strcat(cpu_model, "K6-III");
break;
case 0x5a0:
strcat(cpu_model, "Geode LX");
/*
* Make sure the TSC runs through suspension,
* otherwise we can't use it as timecounter
*/
wrmsr(0x1900, rdmsr(0x1900) | 0x20ULL);
break;
default:
strcat(cpu_model, "Unknown");
break;
}
#if defined(I586_CPU) && defined(CPU_WT_ALLOC)
if ((cpu_id & 0xf00) == 0x500) {
if (((cpu_id & 0x0f0) > 0)
&& ((cpu_id & 0x0f0) < 0x60)
&& ((cpu_id & 0x00f) > 3))
enable_K5_wt_alloc();
else if (((cpu_id & 0x0f0) > 0x80)
|| (((cpu_id & 0x0f0) == 0x80)
&& (cpu_id & 0x00f) > 0x07))
enable_K6_2_wt_alloc();
else if ((cpu_id & 0x0f0) > 0x50)
enable_K6_wt_alloc();
}
#endif
} else if (cpu_vendor_id == CPU_VENDOR_RISE) {
strcpy(cpu_model, "Rise ");
switch (cpu_id & 0xff0) {
case 0x500:
strcat(cpu_model, "mP6");
break;
default:
strcat(cpu_model, "Unknown");
}
} else if (cpu_vendor_id == CPU_VENDOR_CENTAUR) {
switch (cpu_id & 0xff0) {
case 0x540:
strcpy(cpu_model, "IDT WinChip C6");
tsc_is_broken = 1;
break;
case 0x580:
strcpy(cpu_model, "IDT WinChip 2");
break;
case 0x660:
strcpy(cpu_model, "VIA C3 Samuel");
break;
case 0x670:
if (cpu_id & 0x8)
strcpy(cpu_model, "VIA C3 Ezra");
else
strcpy(cpu_model, "VIA C3 Samuel 2");
break;
case 0x680:
strcpy(cpu_model, "VIA C3 Ezra-T");
break;
case 0x690:
strcpy(cpu_model, "VIA C3 Nehemiah");
break;
case 0x6a0:
case 0x6d0:
strcpy(cpu_model, "VIA C7 Esther");
break;
case 0x6f0:
strcpy(cpu_model, "VIA Nano");
break;
default:
strcpy(cpu_model, "VIA/IDT Unknown");
}
} else if (cpu_vendor_id == CPU_VENDOR_IBM) {
strcpy(cpu_model, "Blue Lightning CPU");
} else if (cpu_vendor_id == CPU_VENDOR_NSC) {
switch (cpu_id & 0xfff) {
case 0x540:
strcpy(cpu_model, "Geode SC1100");
cpu = CPU_GEODE1100;
tsc_is_broken = 1;
break;
default:
strcpy(cpu_model, "Geode/NSC unknown");
break;
}
}
/*
* Replace cpu_model with cpu_brand minus leading spaces if
* we have one.
*/
brand = cpu_brand;
while (*brand == ' ')
++brand;
if (*brand != '\0')
strcpy(cpu_model, brand);
kprintf("%s (", cpu_model);
switch(cpu_class) {
case CPUCLASS_286:
kprintf("286");
break;
case CPUCLASS_386:
kprintf("386");
break;
#if defined(I486_CPU)
case CPUCLASS_486:
kprintf("486");
break;
#endif
#if defined(I586_CPU)
case CPUCLASS_586:
hw_clockrate = (tsc_frequency + 5000) / 1000000;
kprintf("%jd.%02d-MHz ",
(intmax_t)(tsc_frequency + 4999) / 1000000,
(u_int)((tsc_frequency + 4999) / 10000) % 100);
kprintf("586");
break;
#endif
#if defined(I686_CPU)
case CPUCLASS_686:
hw_clockrate = (tsc_frequency + 5000) / 1000000;
kprintf("%jd.%02d-MHz ",
(intmax_t)(tsc_frequency + 4999) / 1000000,
(u_int)((tsc_frequency + 4999) / 10000) % 100);
kprintf("686");
break;
#endif
default:
kprintf("Unknown"); /* will panic below... */
}
kprintf("-class CPU)\n");
if(*cpu_vendor)
kprintf(" Origin = \"%s\"",cpu_vendor);
if(cpu_id)
kprintf(" Id = 0x%x", cpu_id);
if (cpu_vendor_id == CPU_VENDOR_INTEL ||
cpu_vendor_id == CPU_VENDOR_AMD ||
cpu_vendor_id == CPU_VENDOR_TRANSMETA ||
cpu_vendor_id == CPU_VENDOR_RISE ||
cpu_vendor_id == CPU_VENDOR_CENTAUR ||
cpu_vendor_id == CPU_VENDOR_NSC) {
kprintf(" Stepping = %u", cpu_id & 0xf);
if (cpu_high > 0) {
#if 0
u_int cmp = 1, htt = 1;
#endif
/*
* Here we should probably set up flags indicating
* whether or not various features are available.
* The interesting ones are probably VME, PSE, PAE,
* and PGE. The code already assumes without bothering
* to check that all CPUs >= Pentium have a TSC and
* MSRs.
*/
kprintf("\n Features=0x%b", cpu_feature,
"\020"
"\001FPU" /* Integral FPU */
"\002VME" /* Extended VM86 mode support */
"\003DE" /* Debugging Extensions (CR4.DE) */
"\004PSE" /* 4MByte page tables */
"\005TSC" /* Timestamp counter */
"\006MSR" /* Machine specific registers */
"\007PAE" /* Physical address extension */
"\010MCE" /* Machine Check support */
"\011CX8" /* CMPEXCH8 instruction */
"\012APIC" /* SMP local APIC */
"\013oldMTRR" /* Previous implementation of MTRR */
"\014SEP" /* Fast System Call */
"\015MTRR" /* Memory Type Range Registers */
"\016PGE" /* PG_G (global bit) support */
"\017MCA" /* Machine Check Architecture */
"\020CMOV" /* CMOV instruction */
"\021PAT" /* Page attributes table */
"\022PSE36" /* 36 bit address space support */
"\023PN" /* Processor Serial number */
"\024CLFLUSH" /* Has the CLFLUSH instruction */
"\025<b20>"
"\026DTS" /* Debug Trace Store */
"\027ACPI" /* ACPI support */
"\030MMX" /* MMX instructions */
"\031FXSR" /* FXSAVE/FXRSTOR */
"\032SSE" /* Streaming SIMD Extensions */
"\033SSE2" /* Streaming SIMD Extensions #2 */
"\034SS" /* Self snoop */
"\035HTT" /* Hyperthreading (see EBX bit 16-23) */
"\036TM" /* Thermal Monitor clock slowdown */
"\037IA64" /* CPU can execute IA64 instructions */
"\040PBE" /* Pending Break Enable */
);
if (cpu_feature2 != 0) {
kprintf("\n Features2=0x%b", cpu_feature2,
"\020"
"\001SSE3" /* SSE3 */
"\002PCLMULQDQ" /* Carry-Less Mul Quadword */
"\003DTES64" /* 64-bit Debug Trace */
"\004MON" /* MONITOR/MWAIT Instructions */
"\005DS_CPL" /* CPL Qualified Debug Store */
"\006VMX" /* Virtual Machine Extensions */
"\007SMX" /* Safer Mode Extensions */
"\010EST" /* Enhanced SpeedStep */
"\011TM2" /* Thermal Monitor 2 */
"\012SSSE3" /* SSSE3 */
"\013CNXT-ID" /* L1 context ID available */
"\014<b11>"
"\015FMA" /* Fused Multiply Add */
"\016CX16" /* CMPXCHG16B Instruction */
"\017xTPR" /* Send Task Priority Messages */
"\020PDCM" /* Perf/Debug Capability MSR */
"\021<b16>"
"\022PCID" /* Process-context Identifiers */
"\023DCA" /* Direct Cache Access */
"\024SSE4.1" /* SSE 4.1 */
"\025SSE4.2" /* SSE 4.2 */
"\026x2APIC" /* xAPIC Extensions */
"\027MOVBE" /* MOVBE Instruction */
"\030POPCNT" /* POPCNT Instruction */
"\031TSCDLT" /* TSC-Deadline Timer */
"\032AESNI" /* AES Crypto */
"\033XSAVE" /* XSAVE/XRSTOR States */
"\034OSXSAVE" /* OS-Enabled State Management */
"\035AVX" /* Advanced Vector Extensions */
"\036F16C" /* Half-precision conversions */
"\037RDRND" /* RDRAND RNG function */
"\040VMM" /* Running on a hypervisor */
);
}
/*
* AMD64 Architecture Programmer's Manual Volume 3:
* General-Purpose and System Instructions
* http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/24594.pdf
*
* IA-32 Intel Architecture Software Developer's Manual,
* Volume 2A: Instruction Set Reference, A-M
* ftp://download.intel.com/design/Pentium4/manuals/25366617.pdf
*/
if (amd_feature != 0) {
kprintf("\n AMD Features=0x%b", amd_feature,
"\020" /* in hex */
"\001<s0>" /* Same */
"\002<s1>" /* Same */
"\003<s2>" /* Same */
"\004<s3>" /* Same */
"\005<s4>" /* Same */
"\006<s5>" /* Same */
"\007<s6>" /* Same */
"\010<s7>" /* Same */
"\011<s8>" /* Same */
"\012<s9>" /* Same */
"\013<b10>" /* Undefined */
"\014SYSCALL" /* Have SYSCALL/SYSRET */
"\015<s12>" /* Same */
"\016<s13>" /* Same */
"\017<s14>" /* Same */
"\020<s15>" /* Same */
"\021<s16>" /* Same */
"\022<s17>" /* Same */
"\023<b18>" /* Reserved, unknown */
"\024MP" /* Multiprocessor Capable */
"\025NX" /* Has EFER.NXE, NX */
"\026<b21>" /* Undefined */
"\027MMX+" /* AMD MMX Extensions */
"\030<s23>" /* Same */
"\031<s24>" /* Same */
"\032FFXSR" /* Fast FXSAVE/FXRSTOR */
"\033Page1GB" /* 1-GB large page support */
"\034RDTSCP" /* RDTSCP */
"\035<b28>" /* Undefined */
"\036LM" /* 64 bit long mode */
"\0373DNow!+" /* AMD 3DNow! Extensions */
"\0403DNow!" /* AMD 3DNow! */
);
}
if (amd_feature2 != 0) {
kprintf("\n AMD Features2=0x%b", amd_feature2,
"\020"
"\001LAHF" /* LAHF/SAHF in long mode */
"\002CMP" /* CMP legacy */
"\003SVM" /* Secure Virtual Mode */
"\004ExtAPIC" /* Extended APIC register */
"\005CR8" /* CR8 in legacy mode */
"\006ABM" /* LZCNT instruction */
"\007SSE4A" /* SSE4A */
"\010MAS" /* Misaligned SSE mode */
"\011Prefetch" /* 3DNow! Prefetch/PrefetchW */
"\012OSVW" /* OS visible workaround */
"\013IBS" /* Instruction based sampling */
"\014XOP" /* XOP extended instructions */
"\015SKINIT" /* SKINIT/STGI */
"\016WDT" /* Watchdog timer */
"\017<b14>"
"\020LWP" /* Lightweight Profiling */
"\021FMA4" /* 4-operand FMA instructions */
"\022TCE" /* Translation Cache Extension */
"\023<b18>"
"\024NodeId" /* NodeId MSR support */
"\025<b20>"
"\026TBM" /* Trailing Bit Manipulation */
"\027Topology" /* Topology Extensions */
"\030PCX_CORE" /* Core Performance Counter */
"\031PCX_NB" /* NB Performance Counter */
"\032<b25>"
"\033<b26>"
"\034<b27>"
"\035<b28>"
"\036<b29>"
"\037<b30>"
"\040<b31>"
);
}
if (cpu_vendor_id == CPU_VENDOR_CENTAUR)
print_via_padlock_info();
/*
* INVALID CPU TOPOLOGY INFORMATION PRINT
* DEPRECATED - CPU_TOPOLOGY_DETECTION moved to
* - sys/platform/pc64/x86_64/mp_machdep.c
* - sys/kern/subr_cpu_topology
*/
#if 0
if ((cpu_feature & CPUID_HTT) &&
cpu_vendor_id == CPU_VENDOR_AMD)
cpu_feature &= ~CPUID_HTT;
#endif
/*
* If this CPU supports HTT or CMP then mention the
* number of physical/logical cores it contains.
*/
#if 0
if (cpu_feature & CPUID_HTT)
htt = (cpu_procinfo & CPUID_HTT_CORES) >> 16;
if (cpu_vendor_id == CPU_VENDOR_AMD &&
(amd_feature2 & AMDID2_CMP))
cmp = (cpu_procinfo2 & AMDID_CMP_CORES) + 1;
else if (cpu_vendor_id == CPU_VENDOR_INTEL &&
(cpu_high >= 4)) {
cpuid_count(4, 0, regs);
if ((regs[0] & 0x1f) != 0)
cmp = ((regs[0] >> 26) & 0x3f) + 1;
}
void
printcpuinfo(void)
{
u_int regs[4], i;
char *brand;
cpu_class = i386_cpus[cpu].cpu_class;
printf("CPU: ");
strncpy(cpu_model, i386_cpus[cpu].cpu_name, sizeof (cpu_model));
/* Check for extended CPUID information and a processor name. */
init_exthigh();
if (cpu_exthigh >= 0x80000004) {
brand = cpu_brand;
for (i = 0x80000002; i < 0x80000005; i++) {
do_cpuid(i, regs);
memcpy(brand, regs, sizeof(regs));
brand += sizeof(regs);
}
}
if (cpu_vendor_id == CPU_VENDOR_INTEL) {
if ((cpu_id & 0xf00) > 0x300) {
u_int brand_index;
cpu_model[0] = '\0';
switch (cpu_id & 0x3000) {
case 0x1000:
strcpy(cpu_model, "Overdrive ");
break;
case 0x2000:
strcpy(cpu_model, "Dual ");
break;
}
switch (cpu_id & 0xf00) {
case 0x400:
strcat(cpu_model, "i486 ");
/* Check the particular flavor of 486 */
switch (cpu_id & 0xf0) {
case 0x00:
case 0x10:
strcat(cpu_model, "DX");
break;
case 0x20:
strcat(cpu_model, "SX");
break;
case 0x30:
strcat(cpu_model, "DX2");
break;
case 0x40:
strcat(cpu_model, "SL");
break;
case 0x50:
strcat(cpu_model, "SX2");
break;
case 0x70:
strcat(cpu_model,
"DX2 Write-Back Enhanced");
break;
case 0x80:
strcat(cpu_model, "DX4");
break;
}
break;
case 0x500:
/* Check the particular flavor of 586 */
strcat(cpu_model, "Pentium");
switch (cpu_id & 0xf0) {
case 0x00:
strcat(cpu_model, " A-step");
break;
case 0x10:
strcat(cpu_model, "/P5");
break;
case 0x20:
strcat(cpu_model, "/P54C");
break;
case 0x30:
strcat(cpu_model, "/P24T");
break;
case 0x40:
strcat(cpu_model, "/P55C");
break;
case 0x70:
strcat(cpu_model, "/P54C");
break;
case 0x80:
strcat(cpu_model, "/P55C (quarter-micron)");
break;
default:
/* nothing */
break;
}
#if defined(I586_CPU) && !defined(NO_F00F_HACK)
/*
* XXX - If/when Intel fixes the bug, this
* should also check the version of the
* CPU, not just that it's a Pentium.
*/
has_f00f_bug = 1;
#endif
break;
case 0x600:
/* Check the particular flavor of 686 */
switch (cpu_id & 0xf0) {
case 0x00:
strcat(cpu_model, "Pentium Pro A-step");
break;
case 0x10:
strcat(cpu_model, "Pentium Pro");
break;
case 0x30:
case 0x50:
case 0x60:
strcat(cpu_model,
"Pentium II/Pentium II Xeon/Celeron");
cpu = CPU_PII;
break;
case 0x70:
case 0x80:
case 0xa0:
case 0xb0:
strcat(cpu_model,
"Pentium III/Pentium III Xeon/Celeron");
cpu = CPU_PIII;
break;
default:
strcat(cpu_model, "Unknown 80686");
break;
}
break;
case 0xf00:
strcat(cpu_model, "Pentium 4");
cpu = CPU_P4;
break;
default:
strcat(cpu_model, "unknown");
break;
}
/*
* If we didn't get a brand name from the extended
* CPUID, try to look it up in the brand table.
*/
if (cpu_high > 0 && *cpu_brand == '\0') {
brand_index = cpu_procinfo & CPUID_BRAND_INDEX;
if (brand_index <= MAX_BRAND_INDEX &&
cpu_brandtable[brand_index] != NULL)
strcpy(cpu_brand,
cpu_brandtable[brand_index]);
}
}
} else if (cpu_vendor_id == CPU_VENDOR_AMD) {
/*
* Values taken from AMD Processor Recognition
* http://www.amd.com/K6/k6docs/pdf/20734g.pdf
* (also describes ``Features'' encodings.
*/
strcpy(cpu_model, "AMD ");
switch (cpu_id & 0xFF0) {
case 0x410:
strcat(cpu_model, "Standard Am486DX");
break;
case 0x430:
strcat(cpu_model, "Enhanced Am486DX2 Write-Through");
break;
case 0x470:
strcat(cpu_model, "Enhanced Am486DX2 Write-Back");
break;
case 0x480:
strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Through");
break;
case 0x490:
strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Back");
break;
case 0x4E0:
strcat(cpu_model, "Am5x86 Write-Through");
break;
case 0x4F0:
strcat(cpu_model, "Am5x86 Write-Back");
break;
case 0x500:
strcat(cpu_model, "K5 model 0");
tsc_freq = 0;
break;
case 0x510:
strcat(cpu_model, "K5 model 1");
break;
case 0x520:
strcat(cpu_model, "K5 PR166 (model 2)");
break;
case 0x530:
strcat(cpu_model, "K5 PR200 (model 3)");
break;
case 0x560:
strcat(cpu_model, "K6");
break;
case 0x570:
strcat(cpu_model, "K6 266 (model 1)");
break;
case 0x580:
strcat(cpu_model, "K6-2");
break;
case 0x590:
strcat(cpu_model, "K6-III");
break;
case 0x5a0:
strcat(cpu_model, "Geode LX");
/*
* Make sure the TSC runs through suspension,
* otherwise we can't use it as timecounter
*/
wrmsr(0x1900, rdmsr(0x1900) | 0x20ULL);
break;
default:
strcat(cpu_model, "Unknown");
break;
}
#if defined(I586_CPU) && defined(CPU_WT_ALLOC)
if ((cpu_id & 0xf00) == 0x500) {
if (((cpu_id & 0x0f0) > 0)
&& ((cpu_id & 0x0f0) < 0x60)
&& ((cpu_id & 0x00f) > 3))
enable_K5_wt_alloc();
else if (((cpu_id & 0x0f0) > 0x80)
|| (((cpu_id & 0x0f0) == 0x80)
&& (cpu_id & 0x00f) > 0x07))
enable_K6_2_wt_alloc();
else if ((cpu_id & 0x0f0) > 0x50)
enable_K6_wt_alloc();
}
#endif
} else if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
strcpy(cpu_model, "Cyrix ");
switch (cpu_id & 0xff0) {
case 0x440:
strcat(cpu_model, "MediaGX");
break;
case 0x520:
strcat(cpu_model, "6x86");
break;
case 0x540:
cpu_class = CPUCLASS_586;
strcat(cpu_model, "GXm");
break;
case 0x600:
strcat(cpu_model, "6x86MX");
break;
default:
/*
* Even though CPU supports the cpuid
* instruction, it can be disabled.
* Therefore, this routine supports all Cyrix
* CPUs.
*/
switch (cyrix_did & 0xf0) {
case 0x00:
switch (cyrix_did & 0x0f) {
case 0x00:
strcat(cpu_model, "486SLC");
break;
case 0x01:
strcat(cpu_model, "486DLC");
break;
case 0x02:
strcat(cpu_model, "486SLC2");
break;
case 0x03:
strcat(cpu_model, "486DLC2");
break;
case 0x04:
strcat(cpu_model, "486SRx");
break;
case 0x05:
strcat(cpu_model, "486DRx");
break;
case 0x06:
strcat(cpu_model, "486SRx2");
break;
case 0x07:
strcat(cpu_model, "486DRx2");
break;
case 0x08:
strcat(cpu_model, "486SRu");
break;
case 0x09:
strcat(cpu_model, "486DRu");
break;
case 0x0a:
strcat(cpu_model, "486SRu2");
break;
case 0x0b:
strcat(cpu_model, "486DRu2");
break;
default:
strcat(cpu_model, "Unknown");
break;
}
break;
case 0x10:
switch (cyrix_did & 0x0f) {
case 0x00:
strcat(cpu_model, "486S");
break;
case 0x01:
strcat(cpu_model, "486S2");
break;
case 0x02:
strcat(cpu_model, "486Se");
break;
case 0x03:
strcat(cpu_model, "486S2e");
break;
case 0x0a:
strcat(cpu_model, "486DX");
break;
case 0x0b:
strcat(cpu_model, "486DX2");
break;
case 0x0f:
strcat(cpu_model, "486DX4");
break;
default:
strcat(cpu_model, "Unknown");
break;
}
break;
case 0x20:
if ((cyrix_did & 0x0f) < 8)
strcat(cpu_model, "6x86"); /* Where did you get it? */
else
strcat(cpu_model, "5x86");
break;
case 0x30:
strcat(cpu_model, "6x86");
break;
case 0x40:
if ((cyrix_did & 0xf000) == 0x3000) {
cpu_class = CPUCLASS_586;
strcat(cpu_model, "GXm");
} else
strcat(cpu_model, "MediaGX");
break;
case 0x50:
strcat(cpu_model, "6x86MX");
break;
case 0xf0:
switch (cyrix_did & 0x0f) {
case 0x0d:
strcat(cpu_model, "Overdrive CPU");
break;
case 0x0e:
strcpy(cpu_model, "Texas Instruments 486SXL");
break;
case 0x0f:
strcat(cpu_model, "486SLC/DLC");
break;
default:
strcat(cpu_model, "Unknown");
break;
}
break;
default:
strcat(cpu_model, "Unknown");
break;
}
break;
}
} else if (cpu_vendor_id == CPU_VENDOR_RISE) {
strcpy(cpu_model, "Rise ");
switch (cpu_id & 0xff0) {
case 0x500: /* 6401 and 6441 (Kirin) */
case 0x520: /* 6510 (Lynx) */
strcat(cpu_model, "mP6");
break;
default:
strcat(cpu_model, "Unknown");
}
} else if (cpu_vendor_id == CPU_VENDOR_CENTAUR) {
switch (cpu_id & 0xff0) {
case 0x540:
strcpy(cpu_model, "IDT WinChip C6");
/*
* http://www.centtech.com/c6_data_sheet.pdf
*
* I-12 RDTSC may return incoherent values in EDX:EAX
* I-13 RDTSC hangs when certain event counters are used
*/
tsc_freq = 0;
break;
case 0x580:
strcpy(cpu_model, "IDT WinChip 2");
break;
case 0x590:
strcpy(cpu_model, "IDT WinChip 3");
break;
case 0x660:
strcpy(cpu_model, "VIA C3 Samuel");
break;
case 0x670:
if (cpu_id & 0x8)
strcpy(cpu_model, "VIA C3 Ezra");
else
strcpy(cpu_model, "VIA C3 Samuel 2");
break;
case 0x680:
strcpy(cpu_model, "VIA C3 Ezra-T");
break;
case 0x690:
strcpy(cpu_model, "VIA C3 Nehemiah");
break;
case 0x6a0:
case 0x6d0:
strcpy(cpu_model, "VIA C7 Esther");
break;
case 0x6f0:
strcpy(cpu_model, "VIA Nano");
break;
default:
strcpy(cpu_model, "VIA/IDT Unknown");
}
} else if (cpu_vendor_id == CPU_VENDOR_IBM) {
strcpy(cpu_model, "Blue Lightning CPU");
} else if (cpu_vendor_id == CPU_VENDOR_NSC) {
switch (cpu_id & 0xff0) {
case 0x540:
strcpy(cpu_model, "Geode SC1100");
cpu = CPU_GEODE1100;
if ((cpu_id & CPUID_STEPPING) == 0)
tsc_freq = 0;
break;
default:
strcpy(cpu_model, "Geode/NSC unknown");
break;
}
}
/*
* Replace cpu_model with cpu_brand minus leading spaces if
* we have one.
*/
brand = cpu_brand;
while (*brand == ' ')
++brand;
if (*brand != '\0')
strcpy(cpu_model, brand);
printf("%s (", cpu_model);
switch(cpu_class) {
case CPUCLASS_286:
printf("286");
break;
case CPUCLASS_386:
printf("386");
break;
#if defined(I486_CPU)
case CPUCLASS_486:
printf("486");
break;
#endif
#if defined(I586_CPU)
case CPUCLASS_586:
if (tsc_freq != 0) {
hw_clockrate = (tsc_freq + 5000) / 1000000;
printf("%jd.%02d-MHz ",
(intmax_t)(tsc_freq + 4999) / 1000000,
(u_int)((tsc_freq + 4999) / 10000) % 100);
}
printf("586");
break;
#endif
#if defined(I686_CPU)
case CPUCLASS_686:
if (tsc_freq != 0) {
hw_clockrate = (tsc_freq + 5000) / 1000000;
printf("%jd.%02d-MHz ",
(intmax_t)(tsc_freq + 4999) / 1000000,
(u_int)((tsc_freq + 4999) / 10000) % 100);
}
printf("686");
break;
#endif
default:
printf("Unknown"); /* will panic below... */
}
printf("-class CPU)\n");
if(*cpu_vendor)
printf(" Origin = \"%s\"",cpu_vendor);
if(cpu_id)
printf(" Id = 0x%x", cpu_id);
if (cpu_vendor_id == CPU_VENDOR_INTEL ||
cpu_vendor_id == CPU_VENDOR_AMD ||
cpu_vendor_id == CPU_VENDOR_TRANSMETA ||
cpu_vendor_id == CPU_VENDOR_RISE ||
cpu_vendor_id == CPU_VENDOR_CENTAUR ||
cpu_vendor_id == CPU_VENDOR_NSC ||
(cpu_vendor_id == CPU_VENDOR_CYRIX &&
((cpu_id & 0xf00) > 0x500))) {
printf(" Family = 0x%x", CPUID_TO_FAMILY(cpu_id));
printf(" Model = 0x%x", CPUID_TO_MODEL(cpu_id));
printf(" Stepping = %u", cpu_id & CPUID_STEPPING);
if (cpu_vendor_id == CPU_VENDOR_CYRIX)
printf("\n DIR=0x%04x", cyrix_did);
/*
* AMD CPUID Specification
* http://support.amd.com/us/Embedded_TechDocs/25481.pdf
*
* Intel Processor Identification and CPUID Instruction
* http://www.intel.com/assets/pdf/appnote/241618.pdf
*/
if (cpu_high > 0) {
/*
* Here we should probably set up flags indicating
* whether or not various features are available.
* The interesting ones are probably VME, PSE, PAE,
* and PGE. The code already assumes without bothering
* to check that all CPUs >= Pentium have a TSC and
* MSRs.
*/
printf("\n Features=0x%b", cpu_feature,
"\020"
"\001FPU" /* Integral FPU */
"\002VME" /* Extended VM86 mode support */
"\003DE" /* Debugging Extensions (CR4.DE) */
"\004PSE" /* 4MByte page tables */
"\005TSC" /* Timestamp counter */
"\006MSR" /* Machine specific registers */
"\007PAE" /* Physical address extension */
"\010MCE" /* Machine Check support */
"\011CX8" /* CMPEXCH8 instruction */
"\012APIC" /* SMP local APIC */
"\013oldMTRR" /* Previous implementation of MTRR */
"\014SEP" /* Fast System Call */
"\015MTRR" /* Memory Type Range Registers */
"\016PGE" /* PG_G (global bit) support */
"\017MCA" /* Machine Check Architecture */
"\020CMOV" /* CMOV instruction */
"\021PAT" /* Page attributes table */
"\022PSE36" /* 36 bit address space support */
"\023PN" /* Processor Serial number */
"\024CLFLUSH" /* Has the CLFLUSH instruction */
"\025<b20>"
"\026DTS" /* Debug Trace Store */
"\027ACPI" /* ACPI support */
"\030MMX" /* MMX instructions */
"\031FXSR" /* FXSAVE/FXRSTOR */
"\032SSE" /* Streaming SIMD Extensions */
"\033SSE2" /* Streaming SIMD Extensions #2 */
"\034SS" /* Self snoop */
"\035HTT" /* Hyperthreading (see EBX bit 16-23) */
"\036TM" /* Thermal Monitor clock slowdown */
"\037IA64" /* CPU can execute IA64 instructions */
"\040PBE" /* Pending Break Enable */
);
if (cpu_feature2 != 0) {
printf("\n Features2=0x%b", cpu_feature2,
"\020"
"\001SSE3" /* SSE3 */
"\002PCLMULQDQ" /* Carry-Less Mul Quadword */
"\003DTES64" /* 64-bit Debug Trace */
"\004MON" /* MONITOR/MWAIT Instructions */
"\005DS_CPL" /* CPL Qualified Debug Store */
"\006VMX" /* Virtual Machine Extensions */
"\007SMX" /* Safer Mode Extensions */
"\010EST" /* Enhanced SpeedStep */
"\011TM2" /* Thermal Monitor 2 */
"\012SSSE3" /* SSSE3 */
"\013CNXT-ID" /* L1 context ID available */
"\014<b11>"
"\015FMA" /* Fused Multiply Add */
"\016CX16" /* CMPXCHG16B Instruction */
"\017xTPR" /* Send Task Priority Messages*/
"\020PDCM" /* Perf/Debug Capability MSR */
"\021<b16>"
"\022PCID" /* Process-context Identifiers*/
"\023DCA" /* Direct Cache Access */
"\024SSE4.1" /* SSE 4.1 */
"\025SSE4.2" /* SSE 4.2 */
"\026x2APIC" /* xAPIC Extensions */
"\027MOVBE" /* MOVBE Instruction */
"\030POPCNT" /* POPCNT Instruction */
"\031TSCDLT" /* TSC-Deadline Timer */
"\032AESNI" /* AES Crypto */
"\033XSAVE" /* XSAVE/XRSTOR States */
"\034OSXSAVE" /* OS-Enabled State Management*/
"\035AVX" /* Advanced Vector Extensions */
"\036F16C" /* Half-precision conversions */
"\037RDRAND" /* RDRAND Instruction */
"\040HV" /* Hypervisor */
);
}
if (amd_feature != 0) {
printf("\n AMD Features=0x%b", amd_feature,
"\020" /* in hex */
"\001<s0>" /* Same */
"\002<s1>" /* Same */
"\003<s2>" /* Same */
"\004<s3>" /* Same */
"\005<s4>" /* Same */
"\006<s5>" /* Same */
"\007<s6>" /* Same */
"\010<s7>" /* Same */
"\011<s8>" /* Same */
"\012<s9>" /* Same */
"\013<b10>" /* Undefined */
"\014SYSCALL" /* Have SYSCALL/SYSRET */
"\015<s12>" /* Same */
"\016<s13>" /* Same */
"\017<s14>" /* Same */
"\020<s15>" /* Same */
"\021<s16>" /* Same */
"\022<s17>" /* Same */
"\023<b18>" /* Reserved, unknown */
"\024MP" /* Multiprocessor Capable */
"\025NX" /* Has EFER.NXE, NX */
"\026<b21>" /* Undefined */
"\027MMX+" /* AMD MMX Extensions */
"\030<s23>" /* Same */
"\031<s24>" /* Same */
"\032FFXSR" /* Fast FXSAVE/FXRSTOR */
"\033Page1GB" /* 1-GB large page support */
"\034RDTSCP" /* RDTSCP */
"\035<b28>" /* Undefined */
"\036LM" /* 64 bit long mode */
"\0373DNow!+" /* AMD 3DNow! Extensions */
"\0403DNow!" /* AMD 3DNow! */
);
}
if (amd_feature2 != 0) {
printf("\n AMD Features2=0x%b", amd_feature2,
"\020"
"\001LAHF" /* LAHF/SAHF in long mode */
"\002CMP" /* CMP legacy */
"\003SVM" /* Secure Virtual Mode */
"\004ExtAPIC" /* Extended APIC register */
"\005CR8" /* CR8 in legacy mode */
"\006ABM" /* LZCNT instruction */
"\007SSE4A" /* SSE4A */
"\010MAS" /* Misaligned SSE mode */
"\011Prefetch" /* 3DNow! Prefetch/PrefetchW */
"\012OSVW" /* OS visible workaround */
"\013IBS" /* Instruction based sampling */
"\014XOP" /* XOP extended instructions */
"\015SKINIT" /* SKINIT/STGI */
"\016WDT" /* Watchdog timer */
"\017<b14>"
"\020LWP" /* Lightweight Profiling */
"\021FMA4" /* 4-operand FMA instructions */
"\022<b17>"
"\023<b18>"
"\024NodeId" /* NodeId MSR support */
"\025<b20>"
"\026TBM" /* Trailing Bit Manipulation */
"\027Topology" /* Topology Extensions */
"\030<b23>"
"\031<b24>"
"\032<b25>"
"\033<b26>"
"\034<b27>"
"\035<b28>"
"\036<b29>"
"\037<b30>"
"\040<b31>"
);
}
if (via_feature_rng != 0 || via_feature_xcrypt != 0)
print_via_padlock_info();
if ((cpu_feature & CPUID_HTT) &&
cpu_vendor_id == CPU_VENDOR_AMD)
cpu_feature &= ~CPUID_HTT;
/*
* If this CPU supports P-state invariant TSC then
* mention the capability.
*/
if (tsc_is_invariant) {
printf("\n TSC: P-state invariant");
if (tsc_perf_stat)
printf(", performance statistics");
}
}
} else if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
printf(" DIR=0x%04x", cyrix_did);
printf(" Stepping=%u", (cyrix_did & 0xf000) >> 12);
printf(" Revision=%u", (cyrix_did & 0x0f00) >> 8);
#ifndef CYRIX_CACHE_REALLY_WORKS
if (cpu == CPU_M1 && (cyrix_did & 0xff00) < 0x1700)
printf("\n CPU cache: write-through mode");
#endif
}
void
initializecpu(void)
{
switch (cpu) {
#ifdef I486_CPU
case CPU_BLUE:
init_bluelightning();
break;
case CPU_486DLC:
init_486dlc();
break;
case CPU_CY486DX:
init_cy486dx();
break;
case CPU_M1SC:
init_5x86();
break;
#ifdef CPU_I486_ON_386
case CPU_486:
init_i486_on_386();
break;
#endif
case CPU_M1:
init_6x86();
break;
#endif /* I486_CPU */
#ifdef I586_CPU
case CPU_586:
switch (cpu_vendor_id) {
case CPU_VENDOR_AMD:
#ifdef CPU_WT_ALLOC
if (((cpu_id & 0x0f0) > 0) &&
((cpu_id & 0x0f0) < 0x60) &&
((cpu_id & 0x00f) > 3))
enable_K5_wt_alloc();
else if (((cpu_id & 0x0f0) > 0x80) ||
(((cpu_id & 0x0f0) == 0x80) &&
(cpu_id & 0x00f) > 0x07))
enable_K6_2_wt_alloc();
else if ((cpu_id & 0x0f0) > 0x50)
enable_K6_wt_alloc();
#endif
if ((cpu_id & 0xf0) == 0xa0)
/*
* Make sure the TSC runs through
* suspension, otherwise we can't use
* it as timecounter
*/
wrmsr(0x1900, rdmsr(0x1900) | 0x20ULL);
break;
case CPU_VENDOR_CENTAUR:
init_winchip();
break;
case CPU_VENDOR_TRANSMETA:
init_transmeta();
break;
case CPU_VENDOR_RISE:
init_rise();
break;
}
break;
#endif
#ifdef I686_CPU
case CPU_M2:
init_6x86MX();
break;
case CPU_686:
switch (cpu_vendor_id) {
case CPU_VENDOR_INTEL:
switch (cpu_id & 0xff0) {
case 0x610:
init_ppro();
break;
case 0x660:
init_mendocino();
break;
}
break;
#ifdef CPU_ATHLON_SSE_HACK
case CPU_VENDOR_AMD:
/*
* Sometimes the BIOS doesn't enable SSE instructions.
* According to AMD document 20734, the mobile
* Duron, the (mobile) Athlon 4 and the Athlon MP
* support SSE. These correspond to cpu_id 0x66X
* or 0x67X.
*/
if ((cpu_feature & CPUID_XMM) == 0 &&
((cpu_id & ~0xf) == 0x660 ||
(cpu_id & ~0xf) == 0x670 ||
(cpu_id & ~0xf) == 0x680)) {
u_int regs[4];
wrmsr(MSR_HWCR, rdmsr(MSR_HWCR) & ~0x08000);
do_cpuid(1, regs);
cpu_feature = regs[3];
}
break;
#endif
case CPU_VENDOR_CENTAUR:
init_via();
break;
case CPU_VENDOR_TRANSMETA:
init_transmeta();
break;
}
#if defined(PAE) || defined(PAE_TABLES)
if ((amd_feature & AMDID_NX) != 0) {
uint64_t msr;
msr = rdmsr(MSR_EFER) | EFER_NXE;
wrmsr(MSR_EFER, msr);
pg_nx = PG_NX;
elf32_nxstack = 1;
}
#endif
break;
#endif
default:
break;
}
#if defined(CPU_ENABLE_SSE)
if ((cpu_feature & CPUID_XMM) && (cpu_feature & CPUID_FXSR)) {
load_cr4(rcr4() | CR4_FXSR | CR4_XMM);
cpu_fxsr = hw_instruction_sse = 1;
}
#endif
}