void configure_adc( UINT8 ref, UINT8 samp_rate, UINT8 samp_time, UINT8 presc, UINT8 ressel, UINT8 gain, UINT8 neg_ain, UINT8 ain ){ configure_global_ports(); enable_adc_clk(); adc_ptr = adc; bankA_ptr = bankA; disable_adc(); /* BIN = (0xFFF)(V_in * GAIN / V_ref) */ adc_ptr->REFCTRL.reg |= ref; // Select a reference adc_ptr->AVGCTRL.reg |= samp_rate; // Now collect a number // of samples at a time. // Total sampling time length = (SAMPLEN+1)*(Clk_ADC/2) adc_ptr->SAMPCTRL.reg = samp_time; // Set sampling time adc_ptr->CTRLB.reg |= presc << 8u; // Set clock prescaler adc_ptr->CTRLB.reg |= ressel << 4; // Select resolution adc_ptr->INPUTCTRL.reg |= gain << 24u; // Select Gain adc_ptr->INPUTCTRL.reg |= neg_ain << 8 // Map the negative terminal | ain // Map the positive terminal ; enable_adc(); }
void start_timer(){ TCCR1A = 0; TCNT1 = 53035; //~=10Hz TCCR1B = (1<<CS11); TIMSK1 = (1<<TOIE1); //timer1 interrupt enabled enable_adc(); ADCSRA |= (1<<ADSC); //start ADC conversion }
void saradc_enable(void) { int i; enable_bandgap(); set_clock_src(0); //0-xtal, 1-clk81 //set adc clock as 1.28Mhz @sys=27MHz set_clock_divider(20); enable_clock(); enable_adc(); set_sample_mode(DIFF_MODE); set_tempsen(0); disable_fifo_irq(); disable_continuous_sample(); disable_chan0_delta(); disable_chan1_delta(); set_input_delay(10, INPUT_DELAY_TB_1US); set_sample_delay(10, SAMPLE_DELAY_TB_1US); set_block_delay(10, BLOCK_DELAY_TB_1US); // channels sampling mode setting for(i=0; i<AML_ADC_SARADC_CHAN_NUM; i++) { set_sample_sw(i, IDLE_SW); set_sample_mux(i, g_chan_mux[i]); } // idle mode setting set_idle_sw(IDLE_SW); set_idle_mux(g_chan_mux[AML_ADC_CHAN_0]); // detect mode setting set_detect_sw(DETECT_SW); set_detect_mux(g_chan_mux[AML_ADC_CHAN_0]); disable_detect_sw(); disable_detect_pullup(); set_detect_irq_pol(0); disable_detect_irq(); set_cal_voltage(7); enable_sample_engine(); #if AML_ADC_SAMPLE_DEBUG printf("ADCREG reg0 =%x\n", get_reg(PP_SAR_ADC_REG0)); printf("ADCREG ch list =%x\n",get_reg(PP_SAR_ADC_CHAN_LIST)); printf("ADCREG avg =%x\n", get_reg(PP_SAR_ADC_AVG_CNTL)); printf("ADCREG reg3 =%x\n", get_reg(PP_SAR_ADC_REG3)); printf("ADCREG ch72 sw =%x\n",get_reg(PP_SAR_ADC_AUX_SW)); printf("ADCREG ch10 sw =%x\n",get_reg(PP_SAR_ADC_CHAN_10_SW)); printf("ADCREG detect&idle=%x\n",get_reg(PP_SAR_ADC_DETECT_IDLE_SW)); #endif //AML_ADC_SAMPLE_DEBUG select_temp(); enable_temp(); enable_temp__(); udelay(1000); }
static void saradc_reset(void) { int i; //set adc clock as 1.28Mhz set_clock_divider(20); enable_clock(); enable_adc(); #if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8 enable_bandgap(); #endif set_sample_mode(DIFF_MODE); set_tempsen(0); disable_fifo_irq(); disable_continuous_sample(); disable_chan0_delta(); disable_chan1_delta(); set_input_delay(10, INPUT_DELAY_TB_1US); set_sample_delay(10, SAMPLE_DELAY_TB_1US); set_block_delay(10, BLOCK_DELAY_TB_1US); // channels sampling mode setting for(i=0; i<SARADC_CHAN_NUM; i++) { set_sample_sw(i, IDLE_SW); set_sample_mux(i, chan_mux[i]); } // idle mode setting set_idle_sw(IDLE_SW); set_idle_mux(chan_mux[CHAN_0]); // detect mode setting set_detect_sw(DETECT_SW); set_detect_mux(chan_mux[CHAN_0]); disable_detect_sw(); disable_detect_pullup(); set_detect_irq_pol(0); disable_detect_irq(); // set_sc_phase(); enable_sample_engine(); // printk("ADCREG reg0 =%x\n", get_reg(SAR_ADC_REG0)); // printk("ADCREG ch list =%x\n", get_reg(SAR_ADC_CHAN_LIST)); // printk("ADCREG avg =%x\n", get_reg(SAR_ADC_AVG_CNTL)); // printk("ADCREG reg3=%x\n", get_reg(SAR_ADC_REG3)); // printk("ADCREG ch72 sw=%x\n", get_reg(SAR_ADC_AUX_SW)); // printk("ADCREG ch10 sw=%x\n", get_reg(SAR_ADC_CHAN_10_SW)); // printk("ADCREG detect&idle=%x\n", get_reg(SAR_ADC_DETECT_IDLE_SW)); }
static void saradc_init(void) { int i; enable_bandgap(); //low speed, set to clk81 without division set_clock_src(1); //0-xtal, 1-clk81 set_clock_divider(0); enable_clock(); enable_adc(); set_sample_mode(DIFF_MODE); set_tempsen(0); disable_fifo_irq(); disable_continuous_sample(); disable_chan0_delta(); disable_chan1_delta(); set_input_delay(10, INPUT_DELAY_TB_1US); set_sample_delay(10, SAMPLE_DELAY_TB_1US); set_block_delay(10, BLOCK_DELAY_TB_1US); aml_set_reg32_bits(P_AO_SAR_ADC_DELAY, 3, 27, 2); // channels sampling mode setting for(i=0; i<AML_ADC_SARADC_CHAN_NUM; i++) { set_sample_sw(i, IDLE_SW); set_sample_mux(i, g_chan_mux[i]); } // idle mode setting set_idle_sw(IDLE_SW); set_idle_mux(g_chan_mux[AML_ADC_CHAN_0]); // detect mode setting set_detect_sw(DETECT_SW); set_detect_mux(g_chan_mux[AML_ADC_CHAN_0]); disable_detect_sw(); disable_detect_pullup(); set_detect_irq_pol(0); disable_detect_irq(); set_cal_voltage(7); set_sc_phase(); enable_sample_engine(); udelay(1000); while (get_fifo_cnt()) { i = get_fifo_sample() & 0x3ff; } }
static inline void saradc_power_control(int on) { if (on) { #if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8 enable_bandgap(); udelay(10); #endif enable_adc(); udelay(5); enable_clock(); enable_sample_engine(); } else { disable_sample_engine(); disable_clock(); disable_adc(); #if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8 disable_bandgap(); #endif } }