static void bootblock_southbridge_init(void)
{
enable_spi_prefetch();
enable_port80_on_lpc();
set_spi_speed();
/* Enable upper 128bytes of CMOS */
RCBA32(RC) = (1 << 2);
}
static void bootblock_southbridge_init(void)
{
#if CONFIG_COLLECT_TIMESTAMPS
store_initial_timestamp();
#endif
map_rcba();
enable_spi_prefetch();
enable_port80_on_lpc();
set_spi_speed();
}
static void bootblock_southbridge_init(void)
{
#if CONFIG_COLLECT_TIMESTAMPS
store_initial_timestamp();
#endif
enable_spi_prefetch();
enable_port80_on_lpc();
set_spi_speed();
/* Enable upper 128bytes of CMOS */
RCBA32(RC) = (1 << 2);
}
/**
* lpc_early_init() - set up LPC serial ports and other early things
*
* @dev: LPC device
* @return 0 if OK, -ve on error
*/
static int lpc_early_init(struct udevice *dev)
{
struct reg_info {
u32 base;
u32 size;
} values[4], *ptr;
int count;
int i;
count = fdtdec_get_int_array_count(gd->fdt_blob, dev->of_offset,
"intel,gen-dec", (u32 *)values,
sizeof(values) / sizeof(u32));
if (count < 0)
return -EINVAL;
/* Set COM1/COM2 decode range */
dm_pci_write_config16(dev->parent, LPC_IO_DEC, 0x0010);
/* Enable PS/2 Keyboard/Mouse, EC areas and COM1 */
dm_pci_write_config16(dev->parent, LPC_EN, KBC_LPC_EN | MC_LPC_EN |
GAMEL_LPC_EN | COMA_LPC_EN);
/* Write all registers but use 0 if we run out of data */
count = count * sizeof(u32) / sizeof(values[0]);
for (i = 0, ptr = values; i < ARRAY_SIZE(values); i++, ptr++) {
u32 reg = 0;
if (i < count)
reg = ptr->base | PCI_COMMAND_IO | (ptr->size << 16);
dm_pci_write_config32(dev->parent, LPC_GENX_DEC(i), reg);
}
enable_spi_prefetch(dev->parent);
/* This is already done in start.S, but let's do it in C */
enable_port80_on_lpc(dev->parent);
set_spi_speed();
return 0;
}
