Exemplo n.º 1
0
int ehci_hcd_init(int index, enum usb_init_type init,
		struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
	struct usb_ehci *ehci = (struct usb_ehci *)(USB_BASE_ADDR +
		(0x200 * index));

	if (index > 3)
		return -EINVAL;
	enable_usboh3_clk(1);
	mdelay(1);

	/* Do board specific initialization */
	board_ehci_hcd_init(index);

	usb_power_config(index);
	usb_oc_config(index);
	usb_internal_phy_clock_gate(index, 1);
	usb_phy_enable(index, ehci);

	*hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
	*hcor = (struct ehci_hcor *)((uint32_t)*hccr +
			HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));

	board_ehci_power(index, (init == USB_INIT_DEVICE) ? 0 : 1);
	if (init == USB_INIT_DEVICE)
		return 0;
	setbits_le32(&ehci->usbmode, CM_HOST);
	__raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
	setbits_le32(&ehci->portsc, USB_EN);

	mdelay(10);

	return 0;
}
Exemplo n.º 2
0
int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
    struct usb_ehci *ehci;

    enable_usboh3_clk(1);
    mdelay(1);

    /* Do board specific initialization */
    board_ehci_hcd_init(CONFIG_MXC_USB_PORT);

#if CONFIG_MXC_USB_PORT == 1
    /* USB Host 1 */
    usbh1_power_config();
    usbh1_oc_config();
    usbh1_internal_phy_clock_gate(1);
    usbh1_phy_enable();
#else
#error "MXC USB port not yet supported"
#endif

    ehci = (struct usb_ehci *)(USBOH3_USB_BASE_ADDR +
                               (0x200 * CONFIG_MXC_USB_PORT));
    *hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
    *hcor = (struct ehci_hcor *)((uint32_t)*hccr +
                                 HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
    setbits_le32(&ehci->usbmode, CM_HOST);

    __raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
    setbits_le32(&ehci->portsc, USB_EN);

    mdelay(10);

    return 0;
}
Exemplo n.º 3
0
int ehci_hcd_init(int index, enum usb_init_type init,
		struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
	struct usb_ehci *ehci;

	/* The only user for this is efikamx-usb */
	ehci_set_controller_priv(index, NULL, &mx5_ehci_ops);
	set_usboh3_clk();
	enable_usboh3_clk(true);
	set_usb_phy_clk();
	enable_usb_phy1_clk(true);
	enable_usb_phy2_clk(true);
	mdelay(1);

	/* Do board specific initialization */
	board_ehci_hcd_init(CONFIG_MXC_USB_PORT);

	ehci = (struct usb_ehci *)(OTG_BASE_ADDR +
		(0x200 * CONFIG_MXC_USB_PORT));
	*hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
	*hcor = (struct ehci_hcor *)((uint32_t)*hccr +
			HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
	setbits_le32(&ehci->usbmode, CM_HOST);

	__raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
	setbits_le32(&ehci->portsc, USB_EN);

	mxc_set_usbcontrol(CONFIG_MXC_USB_PORT, CONFIG_MXC_USB_FLAGS);
	mdelay(10);

	/* Do board specific post-initialization */
	board_ehci_hcd_postinit(ehci, CONFIG_MXC_USB_PORT);

	return 0;
}
Exemplo n.º 4
0
/*
 * mxc_udc_init function
 */
int mxc_udc_destroy(void)
{
	usb_udc_destroy();
	enable_usboh3_clk(0);
	enable_usb_phy1_clk(0);

	return 0;
}
Exemplo n.º 5
0
/*
 * mxc_udc_init function
 */
int mxc_udc_init(void)
{
	set_usboh3_clk();
	set_usb_phy1_clk();
	enable_usboh3_clk(1);
	enable_usb_phy1_clk(1);
	usb_udc_init();

	return 0;
}
Exemplo n.º 6
0
/*
 * mxc_udc_init function
 */
int mxc_udc_init(void)
{
	set_usboh3_clk();
	set_usb_phy1_clk();
	enable_usboh3_clk(1);
#if defined(CONFIG_MX6Q) || defined(CONFIG_MX6DL)
	udc_disable_over_current();
#endif
	enable_usb_phy1_clk(1);
	usb_udc_init();

	return 0;
}
Exemplo n.º 7
0
/*
 * mxc_udc_init function
 */
int mxc_udc_init(void)
{
    udc_pins_setting();
	set_usb_phy1_clk();
	enable_usboh3_clk(1);
#if (defined(CONFIG_MX6) || defined(CONFIG_MX7))
	udc_disable_over_current();
#endif
	enable_usb_phy1_clk(1);
	usb_udc_init();

	return 0;
}
Exemplo n.º 8
0
int ehci_hcd_init(int index, enum usb_init_type init,
                  struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
    enum usb_init_type type;
#if defined(CONFIG_MX6)
    u32 controller_spacing = 0x200;
#elif defined(CONFIG_MX7)
    u32 controller_spacing = 0x10000;
#endif
    struct usb_ehci *ehci = (struct usb_ehci *)(USB_BASE_ADDR +
                            (controller_spacing * index));
    int ret;

    if (index > 3)
        return -EINVAL;
    enable_usboh3_clk(1);
    mdelay(1);

    /* Do board specific initialization */
    ret = board_ehci_hcd_init(index);
    if (ret)
        return ret;

    usb_power_config(index);
    usb_oc_config(index);

#if defined(CONFIG_MX6)
    usb_internal_phy_clock_gate(index, 1);
    usb_phy_enable(index, ehci);
#endif
    type = board_usb_phy_mode(index);

    *hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
    *hcor = (struct ehci_hcor *)((uint32_t)*hccr +
                                 HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));

    if ((type == init) || (type == USB_INIT_DEVICE))
        board_ehci_power(index, (type == USB_INIT_DEVICE) ? 0 : 1);
    if (type != init)
        return -ENODEV;
    if (type == USB_INIT_DEVICE)
        return 0;

    setbits_le32(&ehci->usbmode, CM_HOST);
    writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
    setbits_le32(&ehci->portsc, USB_EN);

    mdelay(10);

    return 0;
}
Exemplo n.º 9
0
int ehci_hcd_init(void)
{
	struct usb_ehci *ehci;
#ifdef CONFIG_MX53
	struct clkctl *sc_regs = (struct clkctl *)CCM_BASE_ADDR;
	u32 reg;

	reg = __raw_readl(&sc_regs->cscmr1) & ~(1 << 26);
	/* derive USB PHY clock multiplexer from PLL3 */
	reg |= 1 << 26;
	__raw_writel(reg, &sc_regs->cscmr1);
#endif

	set_usboh3_clk();
	enable_usboh3_clk(1);
	set_usb_phy2_clk();
	enable_usb_phy2_clk(1);
	mdelay(1);

	/* Do board specific initialization */
	board_ehci_hcd_init(CONFIG_MXC_USB_PORT);

	ehci = (struct usb_ehci *)(OTG_BASE_ADDR +
		(0x200 * CONFIG_MXC_USB_PORT));
	hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
	hcor = (struct ehci_hcor *)((uint32_t)hccr +
			HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
	setbits_le32(&ehci->usbmode, CM_HOST);

	__raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
	setbits_le32(&ehci->portsc, USB_EN);

	mxc_set_usbcontrol(CONFIG_MXC_USB_PORT, CONFIG_MXC_USB_FLAGS);
	mdelay(10);

	/* Do board specific post-initialization */
	board_ehci_hcd_postinit(ehci, CONFIG_MXC_USB_PORT);

	return 0;
}
Exemplo n.º 10
0
int ehci_mx6_common_init(struct usb_ehci *ehci, int index)
{
	int ret;

	enable_usboh3_clk(1);
	mdelay(1);

	/* Do board specific initialization */
	ret = board_ehci_hcd_init(index);
	if (ret)
		return ret;

	usb_power_config(index);
	usb_oc_config(index);

#if defined(CONFIG_MX6)
	usb_internal_phy_clock_gate(index, 1);
	usb_phy_enable(index, ehci);
#endif

	return 0;
}
Exemplo n.º 11
0
/* Configure PLL/PFD freq */
void clock_init(void)
{
	/*
	 * ROM has enabled clocks:
	 * A4 side: SIRC 16Mhz (DIV1-3 off),  FIRC 48Mhz (DIV1-2 on),
	 *          Non-LP-boot:  SOSC, SPLL PFD0 (scs selected)
	 * A7 side:  SPLL PFD0 (scs selected, 413Mhz),
	 *           APLL PFD0 (352Mhz), DDRCLK, all NIC clocks
	 *           A7 Plat0 (NIC0) = 176Mhz, Plat1 (NIC1) = 176Mhz,
	 *           IP BUS (NIC1_BUS) = 58.6Mhz
	 *
	 * In u-boot:
	 * 1. Enable PFD1-3 of APLL for A7 side. Enable FIRC and DIVs.
	 * 2. Enable USB PLL
	 * 3. Init the clocks of peripherals used in u-boot bu
	 *    without set rate interface.The clocks for these
	 *    peripherals are enabled in this intialization.
	 * 4.Other peripherals with set clock rate interface
	 *   does not be set in this function.
	 */

	scg_a7_firc_init();

	scg_a7_soscdiv_init();

	/* APLL PFD1 = 270Mhz, PFD2=480Mhz, PFD3=800Mhz */
	scg_enable_pll_pfd(SCG_APLL_PFD1_CLK, 35);
	scg_enable_pll_pfd(SCG_APLL_PFD2_CLK, 20);
	scg_enable_pll_pfd(SCG_APLL_PFD3_CLK, 12);

	init_clk_lpuart();

	init_clk_rgpio2p();

	enable_usboh3_clk(1);
}
Exemplo n.º 12
0
int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
	struct usb_ehci *ehci;
	u32 reg;
#ifdef CONFIG_MX53
	struct clkctl *sc_regs = (struct clkctl *)CCM_BASE_ADDR;

	reg = __raw_readl(&sc_regs->cscmr1) & ~(1 << 26);
	/* derive USB PHY clock multiplexer from PLL3 */
	reg |= 1 << 26;
	__raw_writel(reg, &sc_regs->cscmr1);
#endif

if (clks_run == 0) {
	set_usboh3_clk();
	enable_usboh3_clk(1);
	set_usb_phy_clk();
	enable_usb_phy1_clk(1);
	enable_usb_phy2_clk(1);
	mdelay(1);
	clks_run = 1;
}

#ifndef CONFIG_MXC_USB_PORT1SC
#define	CONFIG_MXC_USB_PORT1SC	(2 << 30)
#define	CONFIG_MXC_USB_FLAGS1	0
#endif
#ifndef CONFIG_MXC_USB_PORT2SC
#define	CONFIG_MXC_USB_PORT2SC	(2 << 30)
#define	CONFIG_MXC_USB_FLAGS2	0
#endif

	/* Do board specific initialization */
	board_ehci_hcd_init(index);

	ehci = (struct usb_ehci *)(OTG_BASE_ADDR +
		(0x200 * index));
	*hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
	*hcor = (struct ehci_hcor *)((uint32_t)*hccr +
			HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
	setbits_le32(&ehci->usbmode, CM_HOST);

	switch (index) {
	case 0:
		__raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
		setbits_le32(&ehci->portsc, USB_EN);
		mxc_set_usbcontrol(index, CONFIG_MXC_USB_FLAGS);
		break;
	case 1:
		__raw_writel(CONFIG_MXC_USB_PORT1SC, &ehci->portsc);
		setbits_le32(&ehci->portsc, USB_EN);
		mxc_set_usbcontrol(index, CONFIG_MXC_USB_FLAGS1);
		break;
	case 2:
		__raw_writel(CONFIG_MXC_USB_PORT2SC, &ehci->portsc);
		setbits_le32(&ehci->portsc, USB_EN);
		mxc_set_usbcontrol(index, CONFIG_MXC_USB_FLAGS2);
		break;
//	case 3:
//		__raw_writel(CONFIG_MXC_USB_PORT3SC, &ehci->portsc);
//		setbits_le32(&ehci->portsc, USB_EN);
//		mxc_set_usbcontrol(index, CONFIG_MXC_USB_FLAGS3);
//		break;
	}

	/* Do board specific post-initialization */
	board_ehci_hcd_postinit(ehci, index);

	return 0;
}