void enx_video_init(void)
{
enx_reg_set(RSTR0, VDEO, 0); // Get video out of reset state
enx_reg_16(VHT) = 857 | 0x5000;
enx_reg_16(VLT) = (623 | (21 << 11));
}
void enx_dac_init(void)
{
enx_reg_set(RSTR0, DAC, 0); // Get dac out of reset state
enx_reg_16(DAC_PC) = 0x0000;
enx_reg_16(DAC_CP) = 0x0009;
}
void enx_irq_enable(void)
{
enx_reg_32(EHIDR) = 0x00000000; // IRQs an Hostprozessor weiterreichen
enx_reg_32(IPR4) = 0x55555555; // alles auf HIRQ0
enx_reg_32(IPR5) = 0x55555555; // das auch noch
enx_reg_16(ISR0) = 0xFFFE; // Clear all irq states
enx_reg_16(ISR1) = 0xFFFE; // Clear all irq states
enx_reg_16(ISR2) = 0xFFFE; // Clear all irq states
enx_reg_16(ISR3) = 0xFFFE; // Clear all irq states
enx_reg_16(ISR4) = 0xFFFE; // Clear all irq states
enx_reg_16(ISR5) = 0xFFFE; // Clear all irq states
enx_reg_16(IMR0) = 0x0001; // mask all IRQ's (=disable them)
enx_reg_16(IMR1) = 0x0001;
enx_reg_16(IMR2) = 0x0001;
enx_reg_16(IMR3) = 0x0001;
enx_reg_16(IMR4) = 0x0001;
enx_reg_16(IMR5) = 0x0001;
enx_reg_32(IDR) = 0x00000000;
}
void enx_irq_disable(void)
{
enx_reg_16(IMR0) = 0xFFFE; // Mask all IRQ's
enx_reg_16(IMR1) = 0xFFFE; // Mask all IRQ's
enx_reg_16(IMR2) = 0xFFFE; // Mask all IRQ's
enx_reg_16(IMR3) = 0xFFFE; // Mask all IRQ's
enx_reg_16(IMR4) = 0xFFFE; // Mask all IRQ's
enx_reg_16(IMR5) = 0xFFFE; // Mask all IRQ's
enx_reg_16(IMR0) = 0x0001; // Mask all IRQ's
enx_reg_16(IMR1) = 0x0001; // Mask all IRQ's
enx_reg_16(IMR2) = 0x0001; // Mask all IRQ's
enx_reg_16(IMR3) = 0x0001; // Mask all IRQ's
enx_reg_16(IMR4) = 0x0001; // Mask all IRQ's
enx_reg_16(IMR5) = 0x0001; // Mask all IRQ's
}
