void
eeprom_factory_reset(char *in)
{
ewb(EE_MAGIC_OFFSET , VERSION_1);
ewb(EE_MAGIC_OFFSET+1, VERSION_2);
cc_factory_reset();
checkFrequency();
ewb(EE_RF_ROUTER_ID, 0);
ewb(EE_RF_ROUTER_ROUTER, 0);
ewb(EE_REQBL, 0);
ewb(EE_LED, 2);
#ifdef HAS_LCD
ewb(EE_CONTRAST, 0x40);
ewb(EE_BRIGHTNESS, 0x80);
ewb(EE_SLEEPTIME, 30);
#endif
#ifdef HAS_ETHERNET
ethernet_reset();
#endif
#ifdef HAS_FS
ewb(EE_LOGENABLED, 0x00);
#endif
#ifdef HAS_RF_ROUTER
ewb(EE_RF_ROUTER_ID, 0x00);
ewb(EE_RF_ROUTER_ROUTER, 0x00);
#endif
if(in[1] != 'x')
prepare_boot(0);
}
static inline int update_status(struct net_device *dev, unsigned long status,
unsigned long mask)
{
struct am_net_private *np = netdev_priv(dev);
int need_reset = 0;
int need_rx_restart = 0;
int res = 0;
if (status & NOR_INTR_EN) //Normal Interrupts Process
{
if (status & TX_INTR_EN) //Transmit Interrupt Process
{
IO_WRITE32((1 << 0 | 1 << 16),np->base_addr + ETH_DMA_5_Status);
res |= 1;
}
if (status & RX_INTR_EN) //Receive Interrupt Process
{
IO_WRITE32((1 << 6 | 1 << 16),np->base_addr + ETH_DMA_5_Status);
res |= 2;
}
if (status & EARLY_RX_INTR_EN) {
IO_WRITE32((EARLY_RX_INTR_EN | NOR_INTR_EN),np->base_addr + ETH_DMA_5_Status);
}
if (status & TX_BUF_UN_EN) {
IO_WRITE32((1 << 2 | 1 << 16),np->base_addr + ETH_DMA_5_Status);
res |= 1;
//this error will cleard in start tx...
if (debug > 1)
printk(KERN_WARNING "[" DRV_NAME "]" "Tx bufer unenable\n");
}
} else if (status & ANOR_INTR_EN) //Abnormal Interrupts Process
{
if (status & RX_BUF_UN) {
IO_WRITE32((RX_BUF_UN | ANOR_INTR_EN),np->base_addr + ETH_DMA_5_Status);
np->stats.rx_over_errors++;
need_rx_restart++;
res |= 2;
//printk(KERN_WARNING DRV_NAME "Receive Buffer Unavailable\n");
if (debug > 1)
printk(KERN_WARNING "[" DRV_NAME "]" "Rx bufer unenable\n");
}
if (status & RX_STOP_EN) {
IO_WRITE32((RX_STOP_EN | ANOR_INTR_EN),
np->base_addr + ETH_DMA_5_Status);
need_rx_restart++;
res |= 2;
}
if (status & RX_WATCH_TIMEOUT) {
IO_WRITE32((RX_WATCH_TIMEOUT | ANOR_INTR_EN),
np->base_addr + ETH_DMA_5_Status);
need_rx_restart++;
}
if (status & FATAL_BUS_ERROR) {
IO_WRITE32((FATAL_BUS_ERROR | ANOR_INTR_EN),
np->base_addr + ETH_DMA_5_Status);
need_reset++;
printk(KERN_WARNING "[" DRV_NAME "]" "fatal bus error\n");
}
if (status & EARLY_TX_INTR_EN) {
IO_WRITE32((EARLY_TX_INTR_EN | ANOR_INTR_EN),
np->base_addr + ETH_DMA_5_Status);
}
if (status & TX_STOP_EN) {
IO_WRITE32((TX_STOP_EN | ANOR_INTR_EN),
np->base_addr + ETH_DMA_5_Status);
res |= 1;
}
if (status & TX_JABBER_TIMEOUT) {
IO_WRITE32((TX_JABBER_TIMEOUT | ANOR_INTR_EN),
np->base_addr + ETH_DMA_5_Status);
printk(KERN_WARNING "[" DRV_NAME "]" "tx jabber timeout\n");
np->first_tx = 1;
}
if (status & RX_FIFO_OVER) {
IO_WRITE32((RX_FIFO_OVER | ANOR_INTR_EN),
np->base_addr + ETH_DMA_5_Status);
np->stats.rx_fifo_errors++;
need_rx_restart++;
res |= 2;
printk(KERN_WARNING "[" DRV_NAME "]" "Rx fifo over\n");
}
if (status & TX_UNDERFLOW) {
IO_WRITE32((TX_UNDERFLOW | ANOR_INTR_EN),
np->base_addr + ETH_DMA_5_Status);
printk(KERN_WARNING "[" DRV_NAME "]" "Tx underflow\n");
np->first_tx = 1;
res |= 1;
}
}
if (need_reset) {
printk(KERN_WARNING DRV_NAME "system reset\n");
free_ringdesc(dev);
ethernet_reset(dev);
} else if (need_rx_restart) {
IO_WRITE32(1, np->base_addr + ETH_DMA_2_Re_Poll_Demand);
}
return res;
}
