static int exynos4_usb_phy1_init(struct platform_device *pdev)
{
u32 phypwr;
u32 phyclk;
u32 rstcon;
atomic_inc(&host_usage);
if (exynos4_usb_host_phy_is_on()) {
dev_err(&pdev->dev, "Already power on PHY\n");
return 0;
}
/*
* set XuhostOVERCUR to in-active by controlling ET6PUD[15:14]
* 0x0 : pull-up/down disabled
* 0x1 : pull-down enabled
* 0x2 : reserved
* 0x3 : pull-up enabled
*/
writel((__raw_readl(ETC6PUD) & ~(0x3 << 14)) | (0x3 << 14),
ETC6PUD);
exynos_usb_phy_control(USB_PHY1, PHY_ENABLE);
/* set clock frequency for PLL */
phyclk = exynos_usb_phy_set_clock(pdev);
phyclk &= ~(PHY1_COMMON_ON_N);
writel(phyclk, EXYNOS4_PHYCLK);
/* set to normal HSIC 0 and 1 of PHY1 */
phypwr = readl(EXYNOS4_PHYPWR);
phypwr &= ~(PHY1_STD_NORMAL_MASK
| EXYNOS4210_HSIC0_NORMAL_MASK
| EXYNOS4210_HSIC1_NORMAL_MASK);
writel(phypwr, EXYNOS4_PHYPWR);
/* floating prevention logic: disable */
writel((readl(EXYNOS4_PHY1CON) | FPENABLEN), EXYNOS4_PHY1CON);
/* reset all ports of both PHY and Link */
rstcon = readl(EXYNOS4_RSTCON)
| EXYNOS4210_HOST_LINK_PORT_SWRST_MASK
| EXYNOS4210_PHY1_SWRST_MASK;
writel(rstcon, EXYNOS4_RSTCON);
udelay(10);
rstcon &= ~(EXYNOS4210_HOST_LINK_PORT_SWRST_MASK
| EXYNOS4210_PHY1_SWRST_MASK);
writel(rstcon, EXYNOS4_RSTCON);
udelay(80);
return 0;
}
static int exynos4210_usb_phy1_init(struct platform_device *pdev)
{
struct clk *otg_clk;
u32 rstcon;
int err;
atomic_inc(&host_usage);
otg_clk = clk_get(&pdev->dev, "otg");
if (IS_ERR(otg_clk)) {
dev_err(&pdev->dev, "Failed to get otg clock\n");
return PTR_ERR(otg_clk);
}
err = clk_enable(otg_clk);
if (err) {
clk_put(otg_clk);
return err;
}
if (exynos4_usb_host_phy_is_on())
return 0;
writel(readl(S5P_USBHOST_PHY_CONTROL) | S5P_USBHOST_PHY_ENABLE,
S5P_USBHOST_PHY_CONTROL);
exynos4210_usb_phy_clkset(pdev);
/* floating prevention logic: disable */
writel((readl(EXYNOS4_PHY1CON) | FPENABLEN), EXYNOS4_PHY1CON);
/* set to normal HSIC 0 and 1 of PHY1 */
writel((readl(EXYNOS4_PHYPWR) & ~PHY1_HSIC_NORMAL_MASK),
EXYNOS4_PHYPWR);
/* set to normal standard USB of PHY1 */
writel((readl(EXYNOS4_PHYPWR) & ~PHY1_STD_NORMAL_MASK), EXYNOS4_PHYPWR);
/* reset all ports of both PHY and Link */
rstcon = readl(EXYNOS4_RSTCON) | HOST_LINK_PORT_SWRST_MASK |
PHY1_SWRST_MASK;
writel(rstcon, EXYNOS4_RSTCON);
udelay(10);
rstcon &= ~(HOST_LINK_PORT_SWRST_MASK | PHY1_SWRST_MASK);
writel(rstcon, EXYNOS4_RSTCON);
udelay(80);
clk_disable(otg_clk);
clk_put(otg_clk);
return 0;
}
static int exynos4_usb_phy1_init(struct platform_device *pdev)
{
u32 phypwr;
u32 phyclk;
u32 rstcon;
if (!strcmp(pdev->name, "s5p-ehci"))
set_bit(HOST_PHY_EHCI, &usb_phy_control.usage);
else if (!strcmp(pdev->name, "s5p-ohci"))
set_bit(HOST_PHY_OHCI, &usb_phy_control.usage);
else if (!strcmp(pdev->name, "s3c-usbgadget"))
set_bit(HOST_PHY_DEVICE, &usb_phy_control.usage);
dev_info(&pdev->dev, "usb phy usage(%ld)\n",usb_phy_control.usage);
if (exynos4_usb_host_phy_is_on()) {
dev_err(&pdev->dev, "Already power on PHY\n");
return 0;
}
/*
* set XuhostOVERCUR to in-active by controlling ET6PUD[15:14]
* 0x0 : pull-up/down disabled
* 0x1 : pull-down enabled
* 0x2 : reserved
* 0x3 : pull-up enabled
*/
writel((__raw_readl(ETC6PUD) & ~(0x3 << 14)) | (0x3 << 14),
ETC6PUD);
exynos_usb_phy_control(USB_PHY1, PHY_ENABLE);
/* set clock frequency for PLL */
phyclk = readl(EXYNOS4_PHYCLK) & ~(EXYNOS4210_CLKSEL_MASK);
phyclk |= exynos_usb_phy_set_clock(pdev);
#ifdef CONFIG_USB_OHCI_S5P
phyclk |= PHY1_COMMON_ON_N;
#else
phyclk &= ~(PHY1_COMMON_ON_N);
#endif
writel(phyclk, EXYNOS4_PHYCLK);
/* set to normal HSIC 0 and 1 of PHY1 */
phypwr = readl(EXYNOS4_PHYPWR);
phypwr &= ~(PHY1_STD_NORMAL_MASK
| EXYNOS4210_HSIC0_NORMAL_MASK
| EXYNOS4210_HSIC1_NORMAL_MASK);
writel(phypwr, EXYNOS4_PHYPWR);
/* floating prevention logic: disable */
writel((readl(EXYNOS4_PHY1CON) | FPENABLEN), EXYNOS4_PHY1CON);
/* reset all ports of both PHY and Link */
rstcon = readl(EXYNOS4_RSTCON)
| EXYNOS4210_HOST_LINK_PORT_SWRST_MASK
| EXYNOS4210_PHY1_SWRST_MASK;
writel(rstcon, EXYNOS4_RSTCON);
udelay(10);
rstcon &= ~(EXYNOS4210_HOST_LINK_PORT_SWRST_MASK
| EXYNOS4210_PHY1_SWRST_MASK);
writel(rstcon, EXYNOS4_RSTCON);
udelay(80);
return 0;
}
static int exynos4_usb_phy1_resume(struct platform_device *pdev)
{
u32 rstcon;
u32 phypwr;
int err;
#if defined(CONFIG_LINK_DEVICE_HSIC) || defined(CONFIG_LINK_DEVICE_USB)
/* HSIC LPA: reset-resume, let cp know pda active from LPA */
/* slave wake at lpa wake ??? */
/* 12.04.27 Move start of phy1_resume, If usb cable power on the
* host phy, EHCI resume miss the PDA_ACTVIE, then CP can't send Host
* wakeup Irq */
if (!strcmp(pdev->name, "s5p-ehci"))
set_hsic_lpa_states(STATE_HSIC_LPA_WAKE);
#endif
if (exynos4_usb_host_phy_is_on()) {
/* set to resume HSIC 0 and 1 and standard of PHY1 */
phypwr = readl(EXYNOS4_PHYPWR);
if (soc_is_exynos4210()) {
phypwr &= ~(PHY1_STD_FORCE_SUSPEND
| EXYNOS4210_HSIC0_FORCE_SUSPEND
| EXYNOS4210_HSIC1_FORCE_SUSPEND);
} else {
phypwr = readl(EXYNOS4_PHYPWR);
phypwr &= ~(PHY1_STD_FORCE_SUSPEND
| EXYNOS4212_HSIC0_FORCE_SUSPEND
| EXYNOS4212_HSIC1_FORCE_SUSPEND);
}
writel(phypwr, EXYNOS4_PHYPWR);
if (usb_phy_control.lpa_entered) {
usb_phy_control.lpa_entered = 0;
err = 1;
} else
err = 0;
} else {
phypwr = readl(EXYNOS4_PHYPWR);
/* set to normal HSIC 0 and 1 of PHY1 */
if (soc_is_exynos4210()) {
writel(PHY_ENABLE, S5P_USBHOST_PHY_CONTROL);
phypwr &= ~(PHY1_STD_NORMAL_MASK
| EXYNOS4210_HSIC0_NORMAL_MASK
| EXYNOS4210_HSIC1_NORMAL_MASK);
writel(phypwr, EXYNOS4_PHYPWR);
/* reset all ports of both PHY and Link */
rstcon = readl(EXYNOS4_RSTCON)
| EXYNOS4210_HOST_LINK_PORT_SWRST_MASK
| EXYNOS4210_PHY1_SWRST_MASK;
writel(rstcon, EXYNOS4_RSTCON);
udelay(10);
rstcon &= ~(EXYNOS4210_HOST_LINK_PORT_SWRST_MASK
| EXYNOS4210_PHY1_SWRST_MASK);
writel(rstcon, EXYNOS4_RSTCON);
} else {
exynos_usb_phy_control(USB_PHY
| USB_PHY_HSIC0
| USB_PHY_HSIC1,
PHY_ENABLE);
/* set to normal of Device */
phypwr = readl(EXYNOS4_PHYPWR) & ~PHY0_NORMAL_MASK;
writel(phypwr, EXYNOS4_PHYPWR);
/* reset both PHY and Link of Device */
rstcon = readl(EXYNOS4_RSTCON) | PHY0_SWRST_MASK;
writel(rstcon, EXYNOS4_RSTCON);
udelay(10);
rstcon &= ~PHY0_SWRST_MASK;
writel(rstcon, EXYNOS4_RSTCON);
/* set to normal of Host */
phypwr &= ~(PHY1_STD_NORMAL_MASK
| EXYNOS4212_HSIC0_NORMAL_MASK
| EXYNOS4212_HSIC1_NORMAL_MASK);
writel(phypwr, EXYNOS4_PHYPWR);
/* reset all ports of both PHY and Link */
rstcon = readl(EXYNOS4_RSTCON)
| EXYNOS4212_HOST_LINK_PORT_SWRST_MASK
| EXYNOS4212_PHY1_SWRST_MASK;
writel(rstcon, EXYNOS4_RSTCON);
udelay(10);
rstcon &= ~(EXYNOS4212_HOST_LINK_PORT_SWRST_MASK
| EXYNOS4212_PHY1_SWRST_MASK);
writel(rstcon, EXYNOS4_RSTCON);
}
usb_phy_control.lpa_entered = 0;
err = 1;
}
udelay(80);
return err;
}
static int exynos4_usb_phy20_is_on(void)
{
return exynos4_usb_host_phy_is_on();
}
int exynos4_check_usb_op(void)
{
u32 phypwr;
u32 op = 1;
unsigned long flags;
int ret;
ret = clk_enable(phy_clk);
if (ret)
return 0;
local_irq_save(flags);
phypwr = readl(EXYNOS4_PHYPWR);
/*If USB Device is power on, */
if (exynos_usb_device_phy_is_on()) {
op = 1;
goto done;
} else if (!exynos4_usb_host_phy_is_on()) {
op = 0;
goto done;
}
/*If USB Device & Host is suspended, */
if (soc_is_exynos4210()) {
if (phypwr & (PHY1_STD_FORCE_SUSPEND
| EXYNOS4210_HSIC0_FORCE_SUSPEND
| EXYNOS4210_HSIC1_FORCE_SUSPEND)) {
#if defined(CONFIG_LINK_DEVICE_HSIC) || defined(CONFIG_LINK_DEVICE_USB)
/* HSIC LPA: LPA USB phy retention reume call the usb
* reset resume, so we should let CP to HSIC L3 mode. */
set_hsic_lpa_states(STATE_HSIC_LPA_ENTER);
#endif
writel(readl(EXYNOS4_PHYPWR)
| PHY1_STD_ANALOG_POWERDOWN,
EXYNOS4_PHYPWR);
writel(PHY_DISABLE, S5P_USBHOST_PHY_CONTROL);
op = 0;
}
} else {
if (phypwr & (PHY1_STD_FORCE_SUSPEND
| EXYNOS4212_HSIC0_FORCE_SUSPEND
| EXYNOS4212_HSIC1_FORCE_SUSPEND)) {
#if defined(CONFIG_LINK_DEVICE_HSIC) || defined(CONFIG_LINK_DEVICE_USB)
/* HSIC LPA: LPA USB phy retention reume call the usb
* reset resume, so we should let CP to HSIC L3 mode. */
set_hsic_lpa_states(STATE_HSIC_LPA_ENTER);
#endif
/* unset to normal of Host */
writel(readl(EXYNOS4_PHYPWR)
| PHY1_STD_ANALOG_POWERDOWN
| EXYNOS4212_HSIC0_ANALOG_POWERDOWN
| EXYNOS4212_HSIC1_ANALOG_POWERDOWN,
EXYNOS4_PHYPWR);
/* unset to normal of Device */
writel((readl(EXYNOS4_PHYPWR) | PHY0_NORMAL_MASK),
EXYNOS4_PHYPWR);
exynos_usb_phy_control(USB_PHY
| USB_PHY_HSIC0
| USB_PHY_HSIC1,
PHY_DISABLE);
op = 0;
usb_phy_control.lpa_entered = 1;
}
}
done:
local_irq_restore(flags);
clk_disable(phy_clk);
return op;
}
static int exynos4_usb_phy1_init(struct platform_device *pdev)
{
struct clk *otg_clk;
u32 phypwr;
u32 phyclk;
u32 rstcon;
int err;
struct completion done;
#ifdef CONFIG_USB_EHCI_S5P
struct modemctl *mc = global_mc;
#endif
/* add by cym 20120921 */
#ifdef CONFIG_USB_EHCI_S5P
#ifdef CONFIG_SMM6260_MODEM
/* end add */
printk("[XJ] cp -> ap wakeup host: %d\n",smm6260_is_host_wakeup());
/* add by cym 20120921 */
#endif
#endif
/* end add */
#ifdef CONFIG_USB_EHCI_S5P
#ifdef CONFIG_SMM6260_MODEM
if (!smm6260_is_host_wakeup()) {
smm6260_set_slave_wakeup(1);
}
if((mc != NULL)&&(mc->in_l3_state == 1)){
init_completion(&done);
mc->l3_done = &done;
// mc->transfer_flag=1;
printk("---wait for wakeup go low no more than 0.5s\n"); //xujie temp
if (!wait_for_completion_timeout(&done, 2*HZ)) {
printk("completion wait timeout\n");
}
}
#endif
#endif
otg_clk = clk_get(&pdev->dev, "usbotg");
if (IS_ERR(otg_clk)) {
dev_err(&pdev->dev, "Failed to get otg clock\n");
return PTR_ERR(otg_clk);
}
err = clk_enable(otg_clk);
if (err) {
clk_put(otg_clk);
return err;
}
if (soc_is_exynos4210()) {
exynos4_usb_phy_control(USB_PHY1, PHY_ENABLE);
} else {
exynos4_usb_phy_control(USB_PHY
| USB_PHY_HSIC0
| USB_PHY_HSIC1,
PHY_ENABLE);
}
atomic_inc(&host_usage);
if (exynos4_usb_host_phy_is_on()) {
dev_err(&pdev->dev, "Already power on PHY\n");
clk_disable(otg_clk);
clk_put(otg_clk);
return 0;
}
/*
* set XuhostOVERCUR to in-active by controlling ET6PUD[15:14]
* 0x0 : pull-up/down disabled
* 0x1 : pull-down enabled
* 0x2 : reserved
* 0x3 : pull-up enabled
*/
writel((__raw_readl(ETC6PUD) & ~(0x3 << 14)) | (0x3 << 14),
ETC6PUD);
/* set clock frequency for PLL */
phyclk = exynos4_usb_phy_set_clock(pdev);
writel(phyclk, EXYNOS4_PHYCLK);
phypwr = readl(EXYNOS4_PHYPWR);
/* set to normal HSIC 0 and 1 of PHY1 */
if (soc_is_exynos4210()) {
phypwr &= ~(PHY1_STD_NORMAL_MASK
| EXYNOS4210_HSIC0_NORMAL_MASK
| EXYNOS4210_HSIC1_NORMAL_MASK);
writel(phypwr, EXYNOS4_PHYPWR);
/* floating prevention logic: disable */
writel((readl(EXYNOS4_PHY1CON) | FPENABLEN), EXYNOS4_PHY1CON);
/* reset all ports of both PHY and Link */
rstcon = readl(EXYNOS4_RSTCON)
| EXYNOS4210_HOST_LINK_PORT_SWRST_MASK
| EXYNOS4210_PHY1_SWRST_MASK;
writel(rstcon, EXYNOS4_RSTCON);
udelay(10);
rstcon &= ~(EXYNOS4210_HOST_LINK_PORT_SWRST_MASK
| EXYNOS4210_PHY1_SWRST_MASK);
writel(rstcon, EXYNOS4_RSTCON);
} else {
/* USB MUX change from Device to Host */
exynos_usb_mux_change(pdev, 1);
phypwr &= ~(PHY1_STD_NORMAL_MASK
| EXYNOS4212_HSIC0_NORMAL_MASK
| EXYNOS4212_HSIC1_NORMAL_MASK);
writel(phypwr, EXYNOS4_PHYPWR);
/* reset all ports of both PHY and Link */
rstcon = readl(EXYNOS4_RSTCON)
| EXYNOS4212_HOST_LINK_PORT_SWRST_MASK
| EXYNOS4212_PHY1_SWRST_MASK;
writel(rstcon, EXYNOS4_RSTCON);
udelay(10);
rstcon &= ~(EXYNOS4212_HOST_LINK_PORT_SWRST_MASK
| EXYNOS4212_PHY1_SWRST_MASK);
writel(rstcon, EXYNOS4_RSTCON);
}
udelay(80);
#ifdef CONFIG_USB_EHCI_S5P
/* modify by cym 20141010 */
#if 0
usb_hub_gpio_init();// liang
#else
#ifndef CONFIG_USB_EXYNOS_SWITCH
usb_hub_gpio_init();
#endif
#endif
/* end modify */
#endif
clk_disable(otg_clk);
clk_put(otg_clk);
//exynos_usb_mux_change(pdev, 0);//wjp for device function
return 0;
}
static int exynos4_usb_phy1_resume(struct platform_device *pdev)
{
struct clk *otg_clk;
u32 rstcon;
u32 phypwr;
int err = 0;
otg_clk = clk_get(&pdev->dev, "usbotg");
if (IS_ERR(otg_clk)) {
dev_err(&pdev->dev, "Failed to get otg clock\n");
return PTR_ERR(otg_clk);
}
err = clk_enable(otg_clk);
if (err) {
clk_put(otg_clk);
return err;
}
if (exynos4_usb_host_phy_is_on()) {
/* set to resume HSIC 0 and 1 and standard of PHY1 */
phypwr = readl(EXYNOS4_PHYPWR);
if (soc_is_exynos4210()) {
phypwr &= ~(PHY1_STD_FORCE_SUSPEND
| EXYNOS4210_HSIC0_FORCE_SUSPEND
| EXYNOS4210_HSIC1_FORCE_SUSPEND);
} else {
/* USB MUX change from Device to Host */
if (!exynos4_usb_device_phy_is_on())
exynos_usb_mux_change(pdev, 1);
phypwr = readl(EXYNOS4_PHYPWR);
phypwr &= ~(PHY1_STD_FORCE_SUSPEND
| EXYNOS4212_HSIC0_FORCE_SUSPEND
| EXYNOS4212_HSIC1_FORCE_SUSPEND);
}
writel(phypwr, EXYNOS4_PHYPWR);
err = 0;
} else {
phypwr = readl(EXYNOS4_PHYPWR);
/* set to normal HSIC 0 and 1 of PHY1 */
if (soc_is_exynos4210()) {
exynos4_usb_phy_control(USB_PHY1, PHY_ENABLE);
phypwr &= ~(PHY1_STD_NORMAL_MASK
| EXYNOS4210_HSIC0_NORMAL_MASK
| EXYNOS4210_HSIC1_NORMAL_MASK);
writel(phypwr, EXYNOS4_PHYPWR);
/* reset all ports of both PHY and Link */
rstcon = readl(EXYNOS4_RSTCON)
| EXYNOS4210_HOST_LINK_PORT_SWRST_MASK
| EXYNOS4210_PHY1_SWRST_MASK;
writel(rstcon, EXYNOS4_RSTCON);
udelay(10);
rstcon &= ~(EXYNOS4210_HOST_LINK_PORT_SWRST_MASK
| EXYNOS4210_PHY1_SWRST_MASK);
writel(rstcon, EXYNOS4_RSTCON);
} else {
exynos4_usb_phy_control(USB_PHY
| USB_PHY_HSIC0
| USB_PHY_HSIC1,
PHY_ENABLE);
/* USB MUX change from Device to Host */
if (!exynos4_usb_device_phy_is_on())
exynos_usb_mux_change(pdev, 1);
phypwr &= ~(PHY1_STD_NORMAL_MASK
| EXYNOS4212_HSIC0_NORMAL_MASK
| EXYNOS4212_HSIC1_NORMAL_MASK);
writel(phypwr, EXYNOS4_PHYPWR);
/* reset all ports of both PHY and Link */
rstcon = readl(EXYNOS4_RSTCON)
| EXYNOS4212_HOST_LINK_PORT_SWRST_MASK
| EXYNOS4212_PHY1_SWRST_MASK;
writel(rstcon, EXYNOS4_RSTCON);
udelay(10);
rstcon &= ~(EXYNOS4212_HOST_LINK_PORT_SWRST_MASK
| EXYNOS4212_PHY1_SWRST_MASK);
writel(rstcon, EXYNOS4_RSTCON);
}
err = 1;
}
udelay(80);
clk_disable(otg_clk);
clk_put(otg_clk);
return err;
}
int exynos4_check_usb_op(void)
{
static struct clk *otg_clk;
unsigned long flags;
u32 phypwr;
u32 op = 1;
if (!otg_clk) {
otg_clk = clk_get(NULL, "usbotg");
if (IS_ERR(otg_clk)) {
printk(KERN_ERR"Failed to get otg clock\n");
otg_clk = NULL;
return 0;
}
}
clk_enable(otg_clk);
local_irq_save(flags);
phypwr = readl(EXYNOS4_PHYPWR);
/*If USB Device is power on, */
if (exynos4_usb_device_phy_is_on()) {
op = 1;
goto done;
} else if (!exynos4_usb_host_phy_is_on()) {
op = 0;
goto done;
}
/*If USB Device & Host is suspended, */
if (soc_is_exynos4210()) {
if (phypwr & (PHY1_STD_FORCE_SUSPEND
| EXYNOS4210_HSIC0_FORCE_SUSPEND
| EXYNOS4210_HSIC1_FORCE_SUSPEND)) {
writel(readl(EXYNOS4_PHYPWR)
| PHY1_STD_ANALOG_POWERDOWN,
EXYNOS4_PHYPWR);
exynos4_usb_phy_control(USB_PHY1, PHY_DISABLE);
op = 0;
}
} else {
if (phypwr & (PHY1_STD_FORCE_SUSPEND
| EXYNOS4212_HSIC0_FORCE_SUSPEND
| EXYNOS4212_HSIC1_FORCE_SUSPEND)) {
writel(readl(EXYNOS4_PHYPWR)
| PHY1_STD_ANALOG_POWERDOWN
| EXYNOS4212_HSIC0_ANALOG_POWERDOWN
| EXYNOS4212_HSIC1_ANALOG_POWERDOWN,
EXYNOS4_PHYPWR);
exynos4_usb_phy_control(USB_PHY
| USB_PHY_HSIC0
| USB_PHY_HSIC1,
PHY_DISABLE);
op = 0;
}
}
done:
local_irq_restore(flags);
clk_disable(otg_clk);
return op;
}
static int exynos4_check_usb_op(void)
{
u32 phypwr;
u32 op = 1;
unsigned long flags;
int ret;
ret = clk_enable(phy_clk);
if (ret)
return 0;
local_irq_save(flags);
phypwr = readl(EXYNOS4_PHYPWR);
/*If USB Device is power on, */
if (exynos_usb_device_phy_is_on()) {
op = 1;
goto done;
} else if (!exynos4_usb_host_phy_is_on()) {
op = 0;
goto done;
}
/*If USB Device & Host is suspended, */
if (soc_is_exynos4210()) {
if (phypwr & (PHY1_STD_FORCE_SUSPEND
| EXYNOS4210_HSIC0_FORCE_SUSPEND
| EXYNOS4210_HSIC1_FORCE_SUSPEND)) {
writel(readl(EXYNOS4_PHYPWR)
| PHY1_STD_ANALOG_POWERDOWN,
EXYNOS4_PHYPWR);
writel(PHY_DISABLE, S5P_USBHOST_PHY_CONTROL);
op = 0;
}
} else {
if (phypwr & (PHY1_STD_FORCE_SUSPEND
| EXYNOS4212_HSIC0_FORCE_SUSPEND
| EXYNOS4212_HSIC1_FORCE_SUSPEND)) {
/* unset to normal of Host */
writel(readl(EXYNOS4_PHYPWR)
| PHY1_STD_ANALOG_POWERDOWN
| EXYNOS4212_HSIC0_ANALOG_POWERDOWN
| EXYNOS4212_HSIC1_ANALOG_POWERDOWN,
EXYNOS4_PHYPWR);
/* unset to normal of Device */
writel((readl(EXYNOS4_PHYPWR) | PHY0_NORMAL_MASK),
EXYNOS4_PHYPWR);
exynos_usb_phy_control(USB_PHY
| USB_PHY_HSIC0
| USB_PHY_HSIC1,
PHY_DISABLE);
op = 0;
usb_phy_control.lpa_entered = 1;
}
}
done:
local_irq_restore(flags);
clk_disable(phy_clk);
return op;
}
static int exynos4_usb_phy1_resume(struct platform_device *pdev)
{
u32 rstcon;
u32 phypwr;
int err;
if (exynos4_usb_host_phy_is_on()) {
/* set to resume HSIC 0 and 1 and standard of PHY1 */
phypwr = readl(EXYNOS4_PHYPWR);
if (soc_is_exynos4210()) {
phypwr &= ~(PHY1_STD_FORCE_SUSPEND
| EXYNOS4210_HSIC0_FORCE_SUSPEND
| EXYNOS4210_HSIC1_FORCE_SUSPEND);
} else {
phypwr = readl(EXYNOS4_PHYPWR);
phypwr &= ~(PHY1_STD_FORCE_SUSPEND
| EXYNOS4212_HSIC0_FORCE_SUSPEND
| EXYNOS4212_HSIC1_FORCE_SUSPEND);
}
writel(phypwr, EXYNOS4_PHYPWR);
if (usb_phy_control.lpa_entered) {
usb_phy_control.lpa_entered = 0;
err = 1;
} else
err = 0;
} else {
phypwr = readl(EXYNOS4_PHYPWR);
/* set to normal HSIC 0 and 1 of PHY1 */
if (soc_is_exynos4210()) {
writel(PHY_ENABLE, S5P_USBHOST_PHY_CONTROL);
phypwr &= ~(PHY1_STD_NORMAL_MASK
| EXYNOS4210_HSIC0_NORMAL_MASK
| EXYNOS4210_HSIC1_NORMAL_MASK);
writel(phypwr, EXYNOS4_PHYPWR);
/* reset all ports of both PHY and Link */
rstcon = readl(EXYNOS4_RSTCON)
| EXYNOS4210_HOST_LINK_PORT_SWRST_MASK
| EXYNOS4210_PHY1_SWRST_MASK;
writel(rstcon, EXYNOS4_RSTCON);
udelay(10);
rstcon &= ~(EXYNOS4210_HOST_LINK_PORT_SWRST_MASK
| EXYNOS4210_PHY1_SWRST_MASK);
writel(rstcon, EXYNOS4_RSTCON);
} else {
exynos_usb_phy_control(USB_PHY
| USB_PHY_HSIC0
| USB_PHY_HSIC1,
PHY_ENABLE);
/* set to normal of Device */
phypwr = readl(EXYNOS4_PHYPWR) & ~PHY0_NORMAL_MASK;
writel(phypwr, EXYNOS4_PHYPWR);
/* reset both PHY and Link of Device */
rstcon = readl(EXYNOS4_RSTCON) | PHY0_SWRST_MASK;
writel(rstcon, EXYNOS4_RSTCON);
udelay(10);
rstcon &= ~PHY0_SWRST_MASK;
writel(rstcon, EXYNOS4_RSTCON);
/* set to normal of Host */
phypwr &= ~(PHY1_STD_NORMAL_MASK
| EXYNOS4212_HSIC0_NORMAL_MASK
| EXYNOS4212_HSIC1_NORMAL_MASK);
writel(phypwr, EXYNOS4_PHYPWR);
/* reset all ports of both PHY and Link */
rstcon = readl(EXYNOS4_RSTCON)
| EXYNOS4212_HOST_LINK_PORT_SWRST_MASK
| EXYNOS4212_PHY1_SWRST_MASK;
writel(rstcon, EXYNOS4_RSTCON);
udelay(10);
rstcon &= ~(EXYNOS4212_HOST_LINK_PORT_SWRST_MASK
| EXYNOS4212_PHY1_SWRST_MASK);
writel(rstcon, EXYNOS4_RSTCON);
}
usb_phy_control.lpa_entered = 0;
err = 1;
}
udelay(80);
return err;
}
static int exynos4_usb_phy1_resume(struct platform_device *pdev)
{
u32 rstcon;
u32 phypwr;
int err;
if (exynos4_usb_host_phy_is_on()) {
/* set to resume HSIC 0 and 1 and standard of PHY1 */
phypwr = readl(EXYNOS4_PHYPWR);
if (soc_is_exynos4210()) {
phypwr &= ~(PHY1_STD_FORCE_SUSPEND
| EXYNOS4210_HSIC0_FORCE_SUSPEND
| EXYNOS4210_HSIC1_FORCE_SUSPEND);
} else {
phypwr = readl(EXYNOS4_PHYPWR);
phypwr &= ~(PHY1_STD_FORCE_SUSPEND
| EXYNOS4212_HSIC0_FORCE_SUSPEND
| EXYNOS4212_HSIC1_FORCE_SUSPEND);
}
writel(phypwr, EXYNOS4_PHYPWR);
if (usb_phy_control.lpa_entered) {
#if defined(CONFIG_LINK_DEVICE_HSIC) || defined(CONFIG_LINK_DEVICE_USB) \
|| defined(CONFIG_MDM_HSIC_PM)
if (!strcmp(pdev->name, "s5p-ehci"))
set_hsic_lpa_states(STATE_HSIC_LPA_WAKE);
#endif
usb_phy_control.lpa_entered = 0;
err = 1;
} else {
err = 0;
}
} else {
phypwr = readl(EXYNOS4_PHYPWR);
/* set to normal HSIC 0 and 1 of PHY1 */
if (soc_is_exynos4210()) {
writel(PHY_ENABLE, S5P_USBHOST_PHY_CONTROL);
phypwr &= ~(PHY1_STD_NORMAL_MASK
| EXYNOS4210_HSIC0_NORMAL_MASK
| EXYNOS4210_HSIC1_NORMAL_MASK);
writel(phypwr, EXYNOS4_PHYPWR);
/* reset all ports of both PHY and Link */
rstcon = readl(EXYNOS4_RSTCON)
| EXYNOS4210_HOST_LINK_PORT_SWRST_MASK
| EXYNOS4210_PHY1_SWRST_MASK;
writel(rstcon, EXYNOS4_RSTCON);
udelay(10);
rstcon &= ~(EXYNOS4210_HOST_LINK_PORT_SWRST_MASK
| EXYNOS4210_PHY1_SWRST_MASK);
writel(rstcon, EXYNOS4_RSTCON);
} else {
exynos_usb_phy_control(USB_PHY
| USB_PHY_HSIC0
| USB_PHY_HSIC1,
PHY_ENABLE);
/* set to normal of Device */
phypwr = readl(EXYNOS4_PHYPWR) & ~PHY0_NORMAL_MASK;
writel(phypwr, EXYNOS4_PHYPWR);
/* reset both PHY and Link of Device */
rstcon = readl(EXYNOS4_RSTCON) | PHY0_SWRST_MASK;
writel(rstcon, EXYNOS4_RSTCON);
udelay(10);
rstcon &= ~PHY0_SWRST_MASK;
writel(rstcon, EXYNOS4_RSTCON);
/* set to normal of Host */
phypwr &= ~(PHY1_STD_NORMAL_MASK
| EXYNOS4212_HSIC0_NORMAL_MASK
| EXYNOS4212_HSIC1_NORMAL_MASK);
writel(phypwr, EXYNOS4_PHYPWR);
/* reset all ports of both PHY and Link */
rstcon = readl(EXYNOS4_RSTCON)
| EXYNOS4212_HOST_LINK_PORT_SWRST_MASK
| EXYNOS4212_PHY1_SWRST_MASK;
writel(rstcon, EXYNOS4_RSTCON);
udelay(10);
rstcon &= ~(EXYNOS4212_HOST_LINK_PORT_SWRST_MASK
| EXYNOS4212_PHY1_SWRST_MASK);
writel(rstcon, EXYNOS4_RSTCON);
}
#if defined(CONFIG_LINK_DEVICE_HSIC) || defined(CONFIG_LINK_DEVICE_USB) \
|| defined(CONFIG_MDM_HSIC_PM)
if (!strcmp(pdev->name, "s5p-ehci"))
set_hsic_lpa_states(STATE_HSIC_LPA_WAKE);
#endif
usb_phy_control.lpa_entered = 0;
err = 1;
}
udelay(80);
return err;
}
static int exynos4_usb_phy1_init(struct platform_device *pdev)
{
struct clk *otg_clk;
struct clk *xusbxti_clk;
u32 phyclk;
u32 rstcon;
int err;
atomic_inc(&host_usage);
otg_clk = clk_get(&pdev->dev, "otg");
if (IS_ERR(otg_clk)) {
dev_err(&pdev->dev, "Failed to get otg clock\n");
return PTR_ERR(otg_clk);
}
err = clk_enable(otg_clk);
if (err) {
clk_put(otg_clk);
return err;
}
if (exynos4_usb_host_phy_is_on())
return 0;
writel(readl(S5P_USBHOST_PHY_CONTROL) | S5P_USBHOST_PHY_ENABLE,
S5P_USBHOST_PHY_CONTROL);
/* */
phyclk = readl(EXYNOS4_PHYCLK) & ~CLKSEL_MASK;
xusbxti_clk = clk_get(&pdev->dev, "xusbxti");
if (xusbxti_clk && !IS_ERR(xusbxti_clk)) {
switch (clk_get_rate(xusbxti_clk)) {
case 12 * MHZ:
phyclk |= CLKSEL_12M;
break;
case 24 * MHZ:
phyclk |= CLKSEL_24M;
break;
default:
case 48 * MHZ:
/* */
break;
}
clk_put(xusbxti_clk);
}
writel(phyclk, EXYNOS4_PHYCLK);
/* */
writel((readl(EXYNOS4_PHY1CON) | FPENABLEN), EXYNOS4_PHY1CON);
/* */
writel((readl(EXYNOS4_PHYPWR) & ~PHY1_HSIC_NORMAL_MASK),
EXYNOS4_PHYPWR);
/* */
writel((readl(EXYNOS4_PHYPWR) & ~PHY1_STD_NORMAL_MASK), EXYNOS4_PHYPWR);
/* */
rstcon = readl(EXYNOS4_RSTCON) | HOST_LINK_PORT_SWRST_MASK |
PHY1_SWRST_MASK;
writel(rstcon, EXYNOS4_RSTCON);
udelay(10);
rstcon &= ~(HOST_LINK_PORT_SWRST_MASK | PHY1_SWRST_MASK);
writel(rstcon, EXYNOS4_RSTCON);
udelay(80);
clk_disable(otg_clk);
clk_put(otg_clk);
return 0;
}
