void
bwtwo_burner(void *v, u_int on, u_int flags)
{
struct bwtwo_softc *sc = v;
int s;
#if defined(SUN4)
if (CPU_ISSUN4 && (sc->sc_bustype == BUS_OBIO)) {
if (ISSET(sc->sc_sunfb.sf_flags, FB_PFOUR)) {
fb_pfour_burner(v, on, flags);
return;
}
if (on)
stba(AC_SYSENABLE, ASI_CONTROL,
lduba(AC_SYSENABLE, ASI_CONTROL) | SYSEN_VIDEO);
else
stba(AC_SYSENABLE, ASI_CONTROL,
lduba(AC_SYSENABLE, ASI_CONTROL) & ~SYSEN_VIDEO);
return;
}
#endif
s = splhigh();
if (on)
sc->sc_reg->fbc_ctrl |= FBC_VENAB | FBC_TIMING;
else {
sc->sc_reg->fbc_ctrl &= ~FBC_VENAB;
if (flags & WSDISPLAY_BURN_VBLANK)
sc->sc_reg->fbc_ctrl &= ~FBC_TIMING;
}
splx(s);
}
void
cgeightattach(struct device *parent, struct device *self, void *args)
{
struct cgeight_softc *sc = (struct cgeight_softc *)self;
struct confargs *ca = args;
int node = 0;
volatile struct bt_regs *bt;
int isconsole = 0;
/* Map the pfour register. */
SET(sc->sc_sunfb.sf_flags, FB_PFOUR);
sc->sc_sunfb.sf_pfour = (volatile u_int32_t *)
mapiodev(ca->ca_ra.ra_reg, 0, sizeof(u_int32_t));
if (cputyp == CPU_SUN4) {
struct eeprom *eep = (struct eeprom *)eeprom_va;
/*
* Assume this is the console if there's no eeprom info
* to be found.
*/
if (eep == NULL || eep->ee_diag.eed_console == EED_CONS_P4)
isconsole = 1;
}
/* Map the Brooktree. */
sc->sc_fbc = (volatile struct fbcontrol *)
mapiodev(ca->ca_ra.ra_reg,
PFOUR_COLOR_OFF_CMAP, sizeof(struct fbcontrol));
sc->sc_phys = ca->ca_ra.ra_reg[0];
/* enable video */
fb_pfour_burner(sc, 1, 0);
bt = &sc->sc_fbc->fbc_dac;
BT_INIT(bt, 0);
fb_setsize(&sc->sc_sunfb, 1, 1152, 900, node, ca->ca_bustype);
sc->sc_sunfb.sf_ro.ri_hw = sc;
/*
* Map the overlay and overlay enable planes.
*/
sc->sc_enable = (volatile u_char *)mapiodev(ca->ca_ra.ra_reg,
PFOUR_COLOR_OFF_ENABLE, round_page(sc->sc_sunfb.sf_fbsize));
sc->sc_sunfb.sf_ro.ri_bits = mapiodev(ca->ca_ra.ra_reg,
PFOUR_COLOR_OFF_OVERLAY, round_page(sc->sc_sunfb.sf_fbsize));
cgeight_reset(sc, WSDISPLAYIO_MODE_EMUL);
printf(": p4, %dx%d", sc->sc_sunfb.sf_width,
sc->sc_sunfb.sf_height);
fbwscons_init(&sc->sc_sunfb, isconsole);
if (isconsole)
fbwscons_console_init(&sc->sc_sunfb, -1);
fbwscons_attach(&sc->sc_sunfb, &cgeight_accessops, isconsole);
}
void
cgfourattach(struct device *parent, struct device *self, void *args)
{
struct cgfour_softc *sc = (struct cgfour_softc *)self;
struct confargs *ca = args;
int node = 0;
volatile struct bt_regs *bt;
int isconsole = 0;
printf(": p4");
/* Map the pfour register. */
SET(sc->sc_sunfb.sf_flags, FB_PFOUR);
sc->sc_sunfb.sf_pfour = (volatile u_int32_t *)
mapiodev(ca->ca_ra.ra_reg, 0, sizeof(u_int32_t));
if (cputyp == CPU_SUN4) {
struct eeprom *eep = (struct eeprom *)eeprom_va;
/*
* Assume this is the console if there's no eeprom info
* to be found.
*/
if (eep == NULL || eep->eeConsole == EE_CONS_P4OPT)
isconsole = 1;
}
/*
* When the ROM has mapped in a cgfour display, the address
* maps only the video RAM, so in any case we have to map the
* registers ourselves. We only need the video RAM if we are
* going to print characters via rconsole.
*/
sc->sc_phys = ca->ca_ra.ra_reg[0];
/* enable video */
fb_pfour_burner(sc, 1, 0);
bt = &sc->sc_fbc->fbc_dac;
BT_INIT(bt, 24);
/*
* XXX should initialize the enable plane, instead of expecting the
* PROM to do so for us
*/
fb_setsize(&sc->sc_sunfb, 8, 1152, 900, node, ca->ca_bustype);
/*
* XXX this only maps the color plane, not the overlay or the enable
* planes
*/
sc->sc_sunfb.sf_ro.ri_bits = mapiodev(ca->ca_ra.ra_reg,
PFOUR_COLOR_OFF_COLOR, round_page(sc->sc_sunfb.sf_fbsize));
sc->sc_sunfb.sf_ro.ri_hw = sc;
fbwscons_init(&sc->sc_sunfb, isconsole ? 0 : RI_CLEAR);
fbwscons_setcolormap(&sc->sc_sunfb, cgfour_setcolor);
printf(", %dx%d\n", sc->sc_sunfb.sf_width, sc->sc_sunfb.sf_height);
if (isconsole) {
fbwscons_console_init(&sc->sc_sunfb, -1);
}
fbwscons_attach(&sc->sc_sunfb, &cgfour_accessops, isconsole);
}
