uint16_t AsebaGetBuffer(AsebaVMState *vm, uint8_t * data, uint16_t maxLength, uint16_t* source) {
int flags;
uint16_t ret = 0;
size_t u;
// Touching the FIFO, mask the interrupt ...
USBMaskInterrupts(flags);
u = get_used(&AsebaUsb.rx);
/* Minium packet size == len + src + msg_type == 6 bytes */
if(u >= 6) {
int len;
fifo_peek((unsigned char *) &len, &AsebaUsb.rx, 2);
if (u >= len + 6) {
memcpy_out_fifo((unsigned char *) &len, &AsebaUsb.rx, 2);
memcpy_out_fifo((unsigned char *) source, &AsebaUsb.rx, 2);
// msg_type is not in the len but is always present
len = len + 2;
/* Yay ! We have a complete packet ! */
if(len > maxLength)
len = maxLength;
memcpy_out_fifo(data, &AsebaUsb.rx, len);
ret = len;
}
}
if(usb_uart_serial_port_open())
USBCDCKickRx();
else
fifo_reset(&AsebaUsb.rx);
USBUnmaskInterrupts(flags);
return ret;
}
static PyObject* fifoReset(PyObject* self, PyObject* arg)
{
unsigned int fifo_id ;
if(!PyArg_ParseTuple(arg, "l", &fifo_id))
return NULL;
fifo_reset(fifo_id);
return Py_BuildValue("l", 1) ;
}
static void
pci_uart_reset(struct pci_uart_softc *sc)
{
uint16_t divisor;
divisor = DEFAULT_RCLK / DEFAULT_BAUD / 16;
sc->dll = divisor;
sc->dlh = divisor >> 16;
fifo_reset(&sc->rxfifo, 1); /* no fifo until enabled by software */
}
void reset(void) {
gpio_set_value(RADIO_SDN, 1);
mdelay(10);
gpio_set_value(RADIO_SDN, 0);
mdelay(10);
u8 buff[10];
//POWER_UP
/*
printk(KERN_ALERT "Set CS to 1 \n");
cs_high();
printk(KERN_ALERT "get CS %d \n",gpio_get_value(SSpin));
mdelay(5000);
printk(KERN_ALERT "Set CS to 0 \n");
cs_low();
printk(KERN_ALERT "get CS %d \n",gpio_get_value(SSpin));
mdelay(5000);
printk(KERN_ALERT "Set CS to 1 \n");
cs_high();
printk(KERN_ALERT "get CS %d \n",gpio_get_value(SSpin));
mdelay(5000);
printk(KERN_ALERT "Set CS to 0 \n");
cs_low();
printk(KERN_ALERT "get CS %d \n",gpio_get_value(SSpin));
*/
//const unsigned char init_command[] = {0x02, 0x01, 0x01, x3, x2, x1, x0};// no patch, boot main app. img, FREQ_VCXO, return 1 byte
u8 init_command[] = { RF_POWER_UP };
SendCmdReceiveAnswer(7, 1, init_command, buff);
mdelay(20);
//ppp(buff, 1);
SendCmdReceiveAnswer(7, 1, init_command, buff);
mdelay(20);
u8 PART_INFO_command[] = { 0x01 }; // Part Info
SendCmdReceiveAnswer(1, 9, PART_INFO_command, buff);
//ppp(buff, 9);
u8 get_int_status_command[] = { 0x20, 0x00, 0x00, 0x00 }; // Clear all pending interrupts and get the interrupt status back
SendCmdReceiveAnswer(4, 9, get_int_status_command, buff);
//ppp(buff, 9);
//const char gpio_pin_cfg_command[] = {0x13, 0x02, 0x02, 0x02, 0x02, 0x08, 0x11, 0x00}; // Set all GPIOs LOW; Link NIRQ to CTS; Link SDO to MISO; Max drive strength
// u8 gpio_pin_cfg_command[] = { 0x13, 0x14, 0x02, 0x21, 0x20,
// 0x27, 0x0b, 0x00 };
// SendCmdReceiveAnswer(8, 8, gpio_pin_cfg_command, buff);
// //ppp(buff, 8);
//
setRFParameters();
fifo_reset();
}
/******************************************************************************
Description.: copy a picture from testpictures.h and signal this to all output
plugins, afterwards switch to the next frame of the animation.
Input Value.: arg is not used
Return Value: NULL
******************************************************************************/
void *worker_thread(void *arg)
{
int i = 0;
int remaining ;
char * fPointer ;
int outlen = 0;
int vsync = 0 ;
/* set cleanup handler to cleanup allocated ressources */
pthread_cleanup_push(worker_cleanup, NULL);
while(!pglobal->stop) {
pthread_mutex_lock(&pglobal->in[plugin_number].db);
//TODO: need to iterate to get the vsync signal and then grab a full frame
fifo_reset();
fifo_read(grab_buffer, 320*240*3);
i = 0 ;
vsync = 0 ;
while(!vsync && i < (320*240*3)){
unsigned short * shortVal ;
shortVal = &grab_buffer[i];
if(*shortVal == 0xAA55){
i+=2 ;
if( (i < (320*240*2)) && grab_buffer[i+(320*240)] == 0x55){
vsync = 1 ;
fPointer = &grab_buffer[i];
break ;
}
}
i ++ ;
}
if(vsync){
DBG("Vsync found !\n");
if(!write_jpegmem_gray(fPointer, 320, 240, &pglobal->in[plugin_number].buf, &outlen, 100)){
printf("compression error !\n");
exit(EXIT_FAILURE);
}
pglobal->in[plugin_number].size = outlen ;
/* signal fresh_frame */
pthread_cond_broadcast(&pglobal->in[plugin_number].db_update);
}
pthread_mutex_unlock(&pglobal->in[plugin_number].db);
}
IPRINT("leaving input thread, calling cleanup function now\n");
pthread_cleanup_pop(1);
return NULL;
}
void AsebaSendBuffer(AsebaVMState *vm, const uint8_t *data, uint16_t length) {
int flags;
// Here we must loop until we can send the data.
// BUT if the usb connection is not available, we drop the packet
if(!usb_uart_serial_port_open())
return;
// Sanity check, should never be true
if (length < 2)
return;
do {
USBMaskInterrupts(flags);
if(get_free(&AsebaUsb.tx) > length + 4) {
length -= 2;
memcpy_to_fifo(&AsebaUsb.tx, (unsigned char *) &length, 2);
memcpy_to_fifo(&AsebaUsb.tx, (unsigned char *) &vm->nodeId, 2);
memcpy_to_fifo(&AsebaUsb.tx, (unsigned char *) data, length + 2);
// Will callback AsebaUsbTxReady
if (!tx_busy) {
tx_busy = 1;
USBCDCKickTx();
}
length = 0;
}
// Usb can be disconnected while sending ...
if(!usb_uart_serial_port_open()) {
fifo_reset(&AsebaUsb.tx);
USBUnmaskInterrupts(flags);
break;
}
USBUnmaskInterrupts(flags);
} while(length);
}
static void
pci_uart_write(struct vmctx *ctx, int vcpu, struct pci_devinst *pi,
int baridx, uint64_t offset, int size, uint64_t value)
{
struct pci_uart_softc *sc;
int fifosz;
uint8_t msr;
sc = pi->pi_arg;
assert(baridx == 0);
assert(size == 1);
/* Open terminal */
if (!sc->opened && sc->stdio) {
pci_uart_opentty(sc);
sc->opened = 1;
}
pthread_mutex_lock(&sc->mtx);
/*
* Take care of the special case DLAB accesses first
*/
if ((sc->lcr & LCR_DLAB) != 0) {
if (offset == REG_DLL) {
sc->dll = value;
goto done;
}
if (offset == REG_DLH) {
sc->dlh = value;
goto done;
}
}
switch (offset) {
case REG_DATA:
if (sc->mcr & MCR_LOOPBACK) {
if (fifo_putchar(&sc->rxfifo, value) != 0)
sc->lsr |= LSR_OE;
} else if (sc->stdio) {
ttywrite(value);
} /* else drop on floor */
sc->thre_int_pending = true;
break;
case REG_IER:
/*
* Apply mask so that bits 4-7 are 0
* Also enables bits 0-3 only if they're 1
*/
sc->ier = value & 0x0F;
break;
case REG_FCR:
/*
* When moving from FIFO and 16450 mode and vice versa,
* the FIFO contents are reset.
*/
if ((sc->fcr & FCR_ENABLE) ^ (value & FCR_ENABLE)) {
fifosz = (value & FCR_ENABLE) ? FIFOSZ : 1;
fifo_reset(&sc->rxfifo, fifosz);
}
/*
* The FCR_ENABLE bit must be '1' for the programming
* of other FCR bits to be effective.
*/
if ((value & FCR_ENABLE) == 0) {
sc->fcr = 0;
} else {
if ((value & FCR_RCV_RST) != 0)
fifo_reset(&sc->rxfifo, FIFOSZ);
sc->fcr = value &
(FCR_ENABLE | FCR_DMA | FCR_RX_MASK);
}
break;
case REG_LCR:
sc->lcr = value;
break;
case REG_MCR:
/* Apply mask so that bits 5-7 are 0 */
sc->mcr = value & 0x1F;
msr = 0;
if (sc->mcr & MCR_LOOPBACK) {
/*
* In the loopback mode certain bits from the
* MCR are reflected back into MSR
*/
if (sc->mcr & MCR_RTS)
msr |= MSR_CTS;
if (sc->mcr & MCR_DTR)
msr |= MSR_DSR;
if (sc->mcr & MCR_OUT1)
msr |= MSR_RI;
if (sc->mcr & MCR_OUT2)
msr |= MSR_DCD;
}
/*
* Detect if there has been any change between the
* previous and the new value of MSR. If there is
* then assert the appropriate MSR delta bit.
*/
if ((msr & MSR_CTS) ^ (sc->msr & MSR_CTS))
sc->msr |= MSR_DCTS;
if ((msr & MSR_DSR) ^ (sc->msr & MSR_DSR))
sc->msr |= MSR_DDSR;
if ((msr & MSR_DCD) ^ (sc->msr & MSR_DCD))
sc->msr |= MSR_DDCD;
if ((sc->msr & MSR_RI) != 0 && (msr & MSR_RI) == 0)
sc->msr |= MSR_TERI;
/*
* Update the value of MSR while retaining the delta
* bits.
*/
sc->msr &= MSR_DELTA_MASK;
sc->msr |= msr;
break;
case REG_LSR:
/*
* Line status register is not meant to be written to
* during normal operation.
*/
break;
case REG_MSR:
/*
* As far as I can tell MSR is a read-only register.
*/
break;
case REG_SCR:
sc->scr = value;
break;
default:
break;
}
done:
pci_uart_toggle_intr(sc);
pthread_mutex_unlock(&sc->mtx);
}
static
int
usart_configure_as_uart (sBSPACMperiphUARTstate * usp,
const sBSPACMperiphUARTconfiguration * cfgp)
{
USART_TypeDef * usart;
const sBSPACMdeviceEFM32periphUARTdevcfg * devcfgp;
if (! (usp && usp->uart)) {
return -1;
}
usart = (USART_TypeDef *)usp->uart;
/* For a USART the devcfgp object is actual a
* sBSPACMdeviceEFM32periphUSARTdevcfg, but that structure simply
* extends the UART part of the configuration. */
devcfgp = (const sBSPACMdeviceEFM32periphUARTdevcfg *)usp->devcfg.ptr;
/* If enabling configuration, enable the high-frequency peripheral
* clock and the clock for the uart itself.
*
* If disabling configuration, disable the interrupts. */
if (cfgp) {
CMU_ClockEnable(cmuClock_HFPER, true);
CMU_ClockEnable(devcfgp->common.clock, true);
} else {
NVIC_DisableIRQ(devcfgp->rx_irqn);
NVIC_DisableIRQ(devcfgp->tx_irqn);
NVIC_ClearPendingIRQ(devcfgp->rx_irqn);
NVIC_ClearPendingIRQ(devcfgp->tx_irqn);
}
USART_Reset(usart);
if (usp->rx_fifo_ni_) {
fifo_reset(usp->rx_fifo_ni_);
}
if (usp->tx_fifo_ni_) {
fifo_reset(usp->tx_fifo_ni_);
}
usp->tx_state_ = 0;
if (cfgp) {
unsigned int baud_rate = cfgp->speed_baud;
if (0 == baud_rate) {
baud_rate = 115200;
}
/* Configure the USART for 8N1. Set TXBL at half-full. */
usart->FRAME = USART_FRAME_DATABITS_EIGHT | USART_FRAME_PARITY_NONE | USART_FRAME_STOPBITS_ONE;
usart->CTRL |= USART_CTRL_TXBIL_HALFFULL;
USART_BaudrateAsyncSet(usart, 0, baud_rate, usartOVS16);
CMU_ClockEnable(cmuClock_GPIO, true);
} else {
/* Done with device; turn it off */
CMU_ClockEnable(devcfgp->common.clock, false);
}
/* Enable or disable UART pins. To avoid false start, when enabling
* configure TX as high. This relies on a comment in the EMLIB code
* that manipulating registers of disabled modules has no effect
* (unlike TM4C where it causes a HardFault). We'll see. */
vBSPACMdeviceEFM32pinmuxConfigure(&devcfgp->common.rx_pinmux, !!cfgp, 1);
vBSPACMdeviceEFM32pinmuxConfigure(&devcfgp->common.tx_pinmux, !!cfgp, 0);
if (cfgp) {
usart->ROUTE = USART_ROUTE_RXPEN | USART_ROUTE_TXPEN | devcfgp->common.location;
/* Clear and enable RX interrupts. TX interrupts are enabled at the
* peripheral when there's something to transmit. TX and RX are
* enabled at the NVIC now. */
usart->IFC = _USART_IF_MASK;
usart->IEN = USART_IF_RXDATAV;
NVIC_ClearPendingIRQ(devcfgp->rx_irqn);
NVIC_ClearPendingIRQ(devcfgp->tx_irqn);
NVIC_EnableIRQ(devcfgp->rx_irqn);
NVIC_EnableIRQ(devcfgp->tx_irqn);
/* Configuration complete; enable the USART */
usart->CMD = USART_CMD_RXEN | USART_CMD_TXEN;
}
return 0;
}
static int
leuart_configure (sBSPACMperiphUARTstate * usp,
const sBSPACMperiphUARTconfiguration * cfgp)
{
LEUART_TypeDef * leuart;
const sBSPACMdeviceEFM32periphLEUARTdevcfg * devcfgp;
if (! (usp && usp->uart)) {
return -1;
}
leuart = (LEUART_TypeDef *)usp->uart;
devcfgp = (const sBSPACMdeviceEFM32periphLEUARTdevcfg *)usp->devcfg.ptr;
/* Configure LFB's source, enable the low-energy peripheral clock, and the clock for the
* leuart itself */
if (cfgp) {
/* LFB is required for LEUART. Power-up is LFRCO which doesn't
* work so good; if we were told a source to use, override
* whatever was there. */
if (devcfgp->lfbsel) {
CMU_ClockSelectSet(cmuClock_LFB, devcfgp->lfbsel);
}
CMU_ClockEnable(cmuClock_CORELE, true);
CMU_ClockEnable(devcfgp->common.clock, true);
} else {
NVIC_DisableIRQ(devcfgp->irqn);
NVIC_ClearPendingIRQ(devcfgp->irqn);
}
LEUART_Reset(leuart);
leuart->FREEZE = LEUART_FREEZE_REGFREEZE;
leuart->CMD = LEUART_CMD_RXDIS | LEUART_CMD_TXDIS;
if (usp->rx_fifo_ni_) {
fifo_reset(usp->rx_fifo_ni_);
}
if (usp->tx_fifo_ni_) {
fifo_reset(usp->tx_fifo_ni_);
}
usp->tx_state_ = 0;
if (cfgp) {
unsigned int speed_baud = cfgp->speed_baud;
if (0 == speed_baud) {
speed_baud = 9600;
}
/* Configure the LEUART for rate at 8N1. */
leuart->CTRL = LEUART_CTRL_DATABITS_EIGHT | LEUART_CTRL_PARITY_NONE | LEUART_CTRL_STOPBITS_ONE;
LEUART_BaudrateSet(leuart, 0, speed_baud);
CMU_ClockEnable(cmuClock_GPIO, true);
}
/* Enable or disable UART pins. To avoid false start, when enabling
* configure TX as high. This relies on a comment in the EMLIB code
* that manipulating registers of disabled modules has no effect
* (unlike TM4C where it causes a HardFault). We'll see. */
vBSPACMdeviceEFM32pinmuxConfigure(&devcfgp->common.rx_pinmux, !!cfgp, 1);
vBSPACMdeviceEFM32pinmuxConfigure(&devcfgp->common.tx_pinmux, !!cfgp, 0);
if (cfgp) {
leuart->ROUTE = LEUART_ROUTE_RXPEN | LEUART_ROUTE_TXPEN | devcfgp->common.location;
/* Clear and enable RX interrupts at the device. Device TX
* interrupts are enabled at the peripheral when there's something
* to transmit. Clear then enable interrupts at the NVIC. */
leuart->IFC = _LEUART_IF_MASK;
leuart->IEN = LEUART_IF_RXDATAV;
NVIC_ClearPendingIRQ(devcfgp->irqn);
NVIC_EnableIRQ(devcfgp->irqn);
/* Configuration complete; enable the LEUART, and release the
* registers to synchronize. */
leuart->CMD = LEUART_CMD_RXEN | LEUART_CMD_TXEN;
leuart->FREEZE = 0;
} else {
CMU_ClockEnable(devcfgp->common.clock, false);
}
return 0;
}
static
hBSPACMperiphUART
spi_configure (sBSPACMperiphUARTstate * usp,
const sBSPACMperiphUARTconfiguration * cfgp)
{
USART_TypeDef * usart;
const sBSPACMdeviceEFM32periphUSARTdevcfg * devcfgp;
if (! (usp && usp->uart)) {
return NULL;
}
usart = (USART_TypeDef *)usp->uart;
devcfgp = (const sBSPACMdeviceEFM32periphUSARTdevcfg *)usp->devcfg.ptr;
/* If enabling configuration, enable the high-frequency peripheral
* clock and the clock for the uart itself.
*
* If disabling configuration, disable the interrupts. */
if (cfgp) {
CMU_ClockEnable(cmuClock_HFPER, true);
CMU_ClockEnable(devcfgp->uart.common.clock, true);
} else {
NVIC_DisableIRQ(devcfgp->uart.rx_irqn);
NVIC_DisableIRQ(devcfgp->uart.tx_irqn);
NVIC_ClearPendingIRQ(devcfgp->uart.rx_irqn);
NVIC_ClearPendingIRQ(devcfgp->uart.tx_irqn);
}
USART_Reset(usart);
if (usp->rx_fifo_ni_) {
fifo_reset(usp->rx_fifo_ni_);
}
if (usp->tx_fifo_ni_) {
fifo_reset(usp->tx_fifo_ni_);
}
usp->tx_state_ = 0;
if (cfgp) {
/* Setting baudrate */
usart->CLKDIV = 128 * (SystemCoreClock / 1000000UL - 2);
/* Configure USART */
/* Using synchronous (USART) mode, MSB first */
usart->CTRL = USART_CTRL_SYNC | USART_CTRL_MSBF;
// NOT AUTOCS
// usart->CTRL |= USART_CTRL_AUTOCS
/* Clearing old transfers/receptions, and disabling interrupts */
usart->CMD = USART_CMD_CLEARRX | USART_CMD_CLEARTX;
usart->IEN = 0;
/* Enabling Master, TX and RX */
CMU_ClockEnable(cmuClock_GPIO, true);
} else {
/* Done with device; turn it off */
CMU_ClockEnable(devcfgp->uart.common.clock, false);
}
/* Enable or disable UART pins. To avoid false start, when enabling
* configure TX as high. This relies on a comment in the EMLIB code
* that manipulating registers of disabled modules has no effect
* (unlike TM4C where it causes a HardFault). We'll see. */
vBSPACMdeviceEFM32pinmuxConfigure(&devcfgp->uart.common.rx_pinmux, !!cfgp, 0);
vBSPACMdeviceEFM32pinmuxConfigure(&devcfgp->uart.common.tx_pinmux, !!cfgp, 0);
vBSPACMdeviceEFM32pinmuxConfigure(&devcfgp->clk_pinmux, !!cfgp, 0);
vBSPACMdeviceEFM32pinmuxConfigure(&devcfgp->cs_pinmux, !!cfgp, 1);
if (cfgp) {
/* Enabling pins and setting location */
usart->ROUTE = USART_ROUTE_TXPEN | USART_ROUTE_RXPEN | USART_ROUTE_CLKPEN | USART_ROUTE_CSPEN | devcfgp->uart.common.location;
/* Clear and enable RX interrupts. TX interrupts are enabled at the
* peripheral when there's something to transmit. TX and RX are
* enabled at the NVIC now. */
usart->IFC = _USART_IF_MASK;
//usart->IEN = USART_IF_RXDATAV;
NVIC_ClearPendingIRQ(devcfgp->uart.rx_irqn);
NVIC_ClearPendingIRQ(devcfgp->uart.tx_irqn);
NVIC_EnableIRQ(devcfgp->uart.rx_irqn);
NVIC_EnableIRQ(devcfgp->uart.tx_irqn);
/* Configuration complete; enable the USART */
usart->CMD = USART_CMD_MASTEREN | USART_CMD_TXEN | USART_CMD_RXEN;
}
return usp;
}
static void ss_realize(DeviceState *dev, Error **errp)
{
SlaveBootInt *s = SBI(dev);
const char *prefix = object_get_canonical_path(OBJECT(dev));
unsigned int i;
const char *port_name;
Chardev *chr;
for (i = 0; i < ARRAY_SIZE(slave_boot_regs_info); ++i) {
DepRegisterInfo *r = &s->regs_info[
slave_boot_regs_info[i].decode.addr / 4];
*r = (DepRegisterInfo) {
.data = (uint8_t *)&s->regs[
slave_boot_regs_info[i].decode.addr / 4],
.data_size = sizeof(uint32_t),
.access = &slave_boot_regs_info[i],
.debug = SBI_ERR_DEBUG,
.prefix = prefix,
.opaque = s,
};
}
port_name = g_strdup("smap_busy_b");
qdev_init_gpio_out_named(dev, &s->smap_busy, port_name, 1);
g_free((gpointer) port_name);
port_name = g_strdup("smap_in_b");
qdev_init_gpio_in_named(dev, smap_update, port_name, 2);
g_free((gpointer) port_name);
chr = qemu_chr_find("sbi");
qdev_prop_set_chr(dev, "chardev", chr);
if (!qemu_chr_fe_get_driver(&s->chr)) {
DPRINT("SBI interface not connected\n");
} else {
qemu_chr_fe_set_handlers(&s->chr, ss_sbi_can_receive, ss_sbi_receive,
NULL, NULL, s, NULL, true);
}
fifo_create8(&s->fifo, 1024 * 4);
}
static void ss_reset(DeviceState *dev)
{
SlaveBootInt *s = SBI(dev);
uint32_t i;
for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) {
dep_register_reset(&s->regs_info[i]);
}
fifo_reset(&s->fifo);
s->busy_line = 1;
qemu_set_irq(s->smap_busy, s->busy_line);
ss_update_busy_line(s);
sbi_update_irq(s);
/* Note : cs always 0 when rp is not connected
* i.e slave always respond to master data irrespective of
* master state
*
* as rdwr is also 0, initial state of sbi is data load. Hack this bit
* to become 1, when sbi changes to write mode. So, its assumed in
* non remote-port model master should expect data when slave wishes
* to send.
*/
}
int main(int argc, char ** argv){
unsigned int i ;
long start_time, end_time ;
double diff_time ;
struct timespec cpu_time ;
if(fifo_open(0) < 0){
printf("cannot open fifo !\n");
return -1 ;
}
fifo_reset(0);
unsigned int size = fifo_getSize(0) ;
unsigned int nb_avail = fifo_getNbAvailable(0);
unsigned int nb_free = fifo_getNbFree(0);
printf("fifo 0 of size %d contains %d tokens , %d free slots \n", size, nb_avail, nb_free);
while(1){
fifo_reset(0);
fifo_read(0, buffer, 4096);
printf("done \n");
}
//fifo_reset(0) ;
//return 0 ;
fifo_write(0, buffer, 640);
sleep(3);
//fifo_read(0, buffer, 1024);
size = fifo_getSize(0) ;
nb_avail = fifo_getNbAvailable(0);
nb_free = fifo_getNbFree(0);
printf("fifo 0 of size %d contains %d tokens , %d free slots \n", size, nb_avail, nb_free);
return 0 ;
clock_gettime(CLOCK_REALTIME, &cpu_time);
start_time = cpu_time.tv_nsec ;
fifo_write(0, buffer, 4096) ;
clock_gettime(CLOCK_REALTIME, &cpu_time);
end_time = cpu_time.tv_nsec ;
diff_time = end_time - start_time ;
diff_time = diff_time/1000000000.0 ;
printf("transffered %d bytes in %f s : %f B/s \n", 4096, diff_time, 4096/diff_time);
printf("read and write done \n");
//printf("fifo 1 is %d large and contains %d tokens \n", fifo_getSize(1), fifo_getNbAvailable(1));
/*while(1){
fifo_reset(1);
fifo_read(1, buffer, 32*6);
for(i = 0 ; i < 5 ; i ++){
unsigned int posx0, posy0, posx1, posy1;
posy0 = buffer[i*(6)];
posy0 += (buffer[(i*(6))+1] & 0x03 << 8);
posx0 = (buffer[(i*(6))+1] & 0xFC >> 2);
posx0 += (buffer[(i*(6))+2] & 0x03 << 8);
posy1 = (buffer[i*(6)+2] & 0xFC >> 2);
posy1 += (buffer[(i*(6))+3] & 0x03 << 8);
posx1 = (buffer[(i*(6))+3] & 0xFC >> 2);
posx1 += (buffer[(i*(6))+4] & 0x03 << 8);
printf("x[%d] = %d, y[%d] = %d \n", i, (posx0 + posx1)/2, i, (posy0 + posy1)/2);
}
sleep(1);
}*/ //blob_tracking test ...
fifo_close(0);
}
int main(int argc, char ** argv){
long start_time, end_time ;
double diff_time ;
struct timespec cpu_time ;
unsigned short vsync1, vsync2 ;
FILE * rgb_fd, * yuv_fd ;
int i,j, res, inc = 0;
unsigned int nbFrames = 1 ;
unsigned int pos = 0 ;
unsigned char * image_buffer, * start_buffer, * end_ptr; //yuv frame buffer
unsigned char * rgb_buffer ;
unsigned short fifo_state, fifo_data ;
float y, u, v ;
float r, g, b ;
if(argc > 1){
nbFrames = atoi(argv[1]);
}
if(fifo_open(1) < 0 || image_buffer == 0){
printf("Error opening fifo 0 \n");
return -1 ;
}
image_buffer = (unsigned char *) malloc(IMAGE_WIDTH*IMAGE_HEIGHT*3);
for(inc = 0 ; inc < nbFrames ; ){
sprintf(yuv_file_name, "./grabbed_frame%04d.jpg", inc);
yuv_fd = fopen(yuv_file_name, "w");
if(yuv_fd == NULL){
perror("Error opening output file");
exit(EXIT_FAILURE);
}
//fifo_reset(1);
clock_gettime(CLOCK_REALTIME, &cpu_time);
start_time = cpu_time.tv_nsec ;
fifo_reset(1);
fifo_read(1, image_buffer, IMAGE_WIDTH*IMAGE_HEIGHT*3);
clock_gettime(CLOCK_REALTIME, &cpu_time);
end_time = cpu_time.tv_nsec ;
diff_time = end_time - start_time ;
diff_time = diff_time/1000000000 ;
printf("transffered %d bytes in %f s : %f B/s \n", (IMAGE_WIDTH * IMAGE_HEIGHT*3), diff_time, (IMAGE_WIDTH * IMAGE_HEIGHT*3)/diff_time);
start_buffer = image_buffer ;
end_ptr = &image_buffer[IMAGE_WIDTH*IMAGE_HEIGHT*3];
vsync1 = *((unsigned short *) start_buffer) ;
vsync2 = *((unsigned short *) &start_buffer[(IMAGE_WIDTH*IMAGE_HEIGHT)+2]) ;
while(vsync1 != 0x55AA && vsync2 != 0x55AA && start_buffer < end_ptr){
start_buffer+=2 ;
vsync1 = *((unsigned short *) start_buffer) ;
vsync2 = *((unsigned short *) &start_buffer[(IMAGE_WIDTH*IMAGE_HEIGHT)+2]) ;
//printf("vsync2 : %x \n", vsync2);
}
if(vsync1 == 0x55AA && vsync2 == 0x55AA){
inc ++ ;
printf("frame found !\n");
}else{
//fclose(yuv_fd);
//continue ;
start_buffer = image_buffer ;
inc ++ ;
}
start_buffer += 2 ;
printf("frame captures \n");
write_jpegfile(start_buffer, IMAGE_WIDTH, IMAGE_HEIGHT, 1, yuv_fd, 100);
fclose(yuv_fd);
}
fifo_close(1);
return 0 ;
}