/**
* Set System Clock HSI48 at 48MHz
*/
void rcc_clock_setup_in_hsi48_out_48mhz(void)
{
rcc_osc_on(RCC_HSI48);
rcc_wait_for_osc_ready(RCC_HSI48);
rcc_set_hpre(RCC_CFGR_HPRE_NODIV);
rcc_set_ppre(RCC_CFGR_PPRE_NODIV);
flash_prefetch_enable();
flash_set_ws(FLASH_ACR_LATENCY_024_048MHZ);
rcc_set_sysclk_source(RCC_HSI48);
rcc_apb1_frequency = 48000000;
rcc_ahb_frequency = 48000000;
}
void rcc_clock_setup_hsi_3v3(const clock_scale_t *clock)
{
/* Enable internal high-speed oscillator. */
rcc_osc_on(HSI);
rcc_wait_for_osc_ready(HSI);
/* Select HSI as SYSCLK source. */
rcc_set_sysclk_source(RCC_CFGR_SW_HSI);
// /* Enable/disable high performance mode */
// if (!clock->power_save) {
// pwr_set_vos_scale(SCALE1);
// } else {
// pwr_set_vos_scale(SCALE2);
// }
/*
* Set prescalers for AHB, ADC, ABP1, ABP2.
* Do this before touching the PLL (TODO: why?).
*/
rcc_set_hpre(clock->hpre);
rcc_set_ppre1(clock->ppre1);
rcc_set_ppre2(clock->ppre2);
rcc_set_main_pll_hsi(clock->pllm, clock->plln,
clock->pllp, clock->pllq);
/* Enable PLL oscillator and wait for it to stabilize. */
rcc_osc_on(PLL);
rcc_wait_for_osc_ready(PLL);
/* Configure flash settings. */
flash_set_ws(clock->flash_config);
/* Select PLL as SYSCLK source. */
rcc_set_sysclk_source(RCC_CFGR_SW_PLL);
/* Wait for PLL clock to be selected. */
rcc_wait_for_sysclk_status(PLL);
/* Set the peripheral clock frequencies used. */
rcc_apb1_frequency = clock->apb1_frequency;
rcc_apb2_frequency = clock->apb2_frequency;
/* Disable internal high-speed oscillator. */
//rcc_osc_off(HSI);
}
void rcc_clock_setup_in_hsi_out_48mhz(void)
{
/* Enable internal high-speed oscillator. */
rcc_osc_on(HSI);
rcc_wait_for_osc_ready(HSI);
/* Select HSI as SYSCLK source. */
rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_HSICLK);
/*
* Set prescalers for AHB, ADC, ABP1, ABP2.
* Do this before touching the PLL (TODO: why?).
*/
rcc_set_hpre(RCC_CFGR_HPRE_SYSCLK_NODIV); /* Set. 48MHz Max. 72MHz */
rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV8); /* Set. 6MHz Max. 14MHz */
rcc_set_ppre1(RCC_CFGR_PPRE1_HCLK_DIV2); /* Set. 24MHz Max. 36MHz */
rcc_set_ppre2(RCC_CFGR_PPRE2_HCLK_NODIV); /* Set. 48MHz Max. 72MHz */
rcc_set_usbpre(RCC_CFGR_USBPRE_PLL_CLK_NODIV); /* Set. 48MHz Max. 48MHz */
/*
* Sysclk runs with 48MHz -> 1 waitstates.
* 0WS from 0-24MHz
* 1WS from 24-48MHz
* 2WS from 48-72MHz
*/
flash_set_ws(FLASH_ACR_LATENCY_1WS);
/*
* Set the PLL multiplication factor to 12.
* 8MHz (internal) * 12 (multiplier) / 2 (PLLSRC_HSI_CLK_DIV2) = 48MHz
*/
rcc_set_pll_multiplication_factor(RCC_CFGR_PLLMUL_PLL_CLK_MUL12);
/* Select HSI/2 as PLL source. */
rcc_set_pll_source(RCC_CFGR_PLLSRC_HSI_CLK_DIV2);
/* Enable PLL oscillator and wait for it to stabilize. */
rcc_osc_on(PLL);
rcc_wait_for_osc_ready(PLL);
/* Select PLL as SYSCLK source. */
rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_PLLCLK);
/* Set the peripheral clock frequencies used */
rcc_ppre1_frequency = 24000000;
rcc_ppre2_frequency = 48000000;
}
void rcc_clock_setup_pll(const struct rcc_clock_scale *clock)
{
/* Enable internal high-speed oscillator. */
rcc_osc_on(RCC_HSI16);
rcc_wait_for_osc_ready(RCC_HSI16);
/* Select HSI as SYSCLK source. */
rcc_set_sysclk_source(RCC_CFGR_SW_HSI16);
/* Wait for HSI16 clock to be selected. */
rcc_wait_for_sysclk_status(RCC_HSI16);
/* Enable/disable high performance mode */
pwr_set_vos_range(clock->voltage_scale);
/*
* Set prescalers for AHB, ADC, ABP1, ABP2.
* Do this before touching the PLL (TODO: why?).
*/
rcc_set_hpre(clock->hpre);
rcc_set_ppre1(clock->ppre1);
rcc_set_ppre2(clock->ppre2);
rcc_set_main_pll(clock->pll_source, clock->pllm, clock->plln,
clock->pllp, clock->pllq, clock->pllr);
/* Enable PLL oscillator and wait for it to stabilize. */
rcc_osc_on(RCC_PLL);
rcc_wait_for_osc_ready(RCC_PLL);
/* Configure flash settings. */
flash_set_ws(clock->flash_config);
/* Select PLL as SYSCLK source. */
rcc_set_sysclk_source(RCC_CFGR_SW_PLL);
/* Wait for PLL clock to be selected. */
rcc_wait_for_sysclk_status(RCC_PLL);
/* Set the peripheral clock frequencies used. */
rcc_apb1_frequency = clock->apb1_frequency;
rcc_apb2_frequency = clock->apb2_frequency;
rcc_set_msi_range(clock->msi_range);
}
/* Set the clock to max speed. */
static void clock_setup(void)
{
#if defined(STM32F0)
rcc_clock_setup_in_hsi_out_48mhz();
#elif defined(STM32L0)
/* After a reset, the system uses [email protected]. */
/* end result: 32MHz PLLVCO from HSI16,
* no system/periph clock divide.
*/
/* increase the latency to 1 wait state (we'll be speeding up) */
flash_set_ws(1);
/* turn on HSI16 */
rcc_osc_on(RCC_HSI16);
rcc_wait_for_osc_ready(RCC_HSI16);
/* run AHB, APB1, APB2 at full speed */
rcc_set_hpre(RCC_CFGR_HPRE_NODIV);
rcc_set_ppre1(RCC_CFGR_PPRE1_NODIV);
rcc_set_ppre2(RCC_CFGR_PPRE2_NODIV);
/* turn off PLL and wait for it to fully stop */
rcc_osc_off(RCC_PLL);
while (RCC_CR & RCC_CR_PLLRDY);
/* set PLL source to HSI16 */
RCC_CFGR &= ~(1<<16); // RCC_CFGR_PLLSRC
/* set up PLL */
rcc_set_pll_multiplier(RCC_CFGR_PLLMUL_MUL4);
rcc_set_pll_divider(RCC_CFGR_PLLDIV_DIV2);
/* turn on and switch to PLL */
rcc_osc_on(RCC_PLL);
rcc_wait_for_osc_ready(RCC_PLL);
rcc_set_sysclk_source(RCC_PLL);
rcc_ahb_frequency = 32000000;
rcc_apb1_frequency = 32000000;
rcc_apb2_frequency = 32000000;
#else
#error "Implement a clock setup."
#endif
}
static void rcc_clock_setup_pll_f3_special(const rcc_clock_scale_t *clock)
{
/* Turn on the appropriate source for the PLL */
// TODO, some f3's have extra bits here
enum rcc_osc my_osc;
if (clock->pll_source == RCC_CFGR_PLLSRC_HSE_PREDIV) {
my_osc = RCC_HSE;
} else {
my_osc = RCC_HSI;
}
rcc_osc_on(my_osc);
while (!rcc_is_osc_ready(my_osc));
/* Configure flash settings. */
flash_set_ws(clock->flash_config);
/*
* Set prescalers for AHB, ADC, ABP1, ABP2.
* Do this before touching the PLL (TODO: why?).
*/
rcc_set_hpre(clock->hpre);
rcc_set_ppre1(clock->ppre1);
rcc_set_ppre2(clock->ppre2);
rcc_osc_off(RCC_PLL);
while (rcc_is_osc_ready(RCC_PLL));
rcc_set_pll_source(clock->pll_source);
rcc_set_pll_multiplier(clock->pll_mul);
// TODO - iff pll_div != 0, then maybe we're on a target that
// has the dividers?
/* Enable PLL oscillator and wait for it to stabilize. */
rcc_osc_on(RCC_PLL);
while (!rcc_is_osc_ready(RCC_PLL));
/* Select PLL as SYSCLK source. */
rcc_set_sysclk_source(RCC_CFGR_SW_PLL);
rcc_wait_for_sysclk_status(RCC_PLL);
/* Set the peripheral clock frequencies used. */
rcc_ahb_frequency = clock->ahb_frequency;
rcc_apb1_frequency = clock->apb1_frequency;
rcc_apb2_frequency = clock->apb2_frequency;
}
void rcc_clock_setup_pll(const struct rcc_clock_scale *clock)
{
/* Turn on the appropriate source for the PLL */
if (clock->pll_source == RCC_CFGR_PLLSRC_HSE_CLK) {
rcc_osc_on(RCC_HSE);
rcc_wait_for_osc_ready(RCC_HSE);
} else {
rcc_osc_on(RCC_HSI);
rcc_wait_for_osc_ready(RCC_HSI);
}
/*
* Set prescalers for AHB, ADC, ABP1, ABP2.
* Do this before touching the PLL (TODO: why?).
*/
rcc_set_hpre(clock->hpre);
rcc_set_ppre1(clock->ppre1);
rcc_set_ppre2(clock->ppre2);
rcc_periph_clock_enable(RCC_PWR);
pwr_set_vos_scale(clock->voltage_scale);
/* I guess this should be in the settings? */
flash_64bit_enable();
flash_prefetch_enable();
/* Configure flash settings. */
flash_set_ws(clock->flash_config);
rcc_set_pll_configuration(clock->pll_source, clock->pll_mul,
clock->pll_div);
/* Enable PLL oscillator and wait for it to stabilize. */
rcc_osc_on(RCC_PLL);
rcc_wait_for_osc_ready(RCC_PLL);
/* Select PLL as SYSCLK source. */
rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_PLLCLK);
/* Set the peripheral clock frequencies used. */
rcc_ahb_frequency = clock->ahb_frequency;
rcc_apb1_frequency = clock->apb1_frequency;
rcc_apb2_frequency = clock->apb2_frequency;
}
int main(void)
{
int32_t i;
rcc_periph_clock_enable(RCC_GPIOA);
gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_2_MHZ, GPIO_CNF_OUTPUT_PUSHPULL, GPIO5);
flash_set_ws(FLASH_ACR_LATENCY_2WS);
rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV4); /* 14MHz */
rcc_set_hpre(RCC_CFGR_HPRE_SYSCLK_NODIV); /* 56MHz */
rcc_set_ppre1(RCC_CFGR_PPRE1_HCLK_DIV2); /* 28MHz */
rcc_set_ppre2(RCC_CFGR_PPRE2_HCLK_NODIV); /* 56MHz */
rcc_set_pll_multiplication_factor(RCC_CFGR_PLLMUL_PLL_CLK_MUL14); /* 8MHz/2 x14 = 56MHz */
rcc_set_pll_source(RCC_CFGR_PLLSRC_HSI_CLK_DIV2);
rcc_osc_on(PLL);
rcc_wait_for_osc_ready(PLL);
rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_PLLCLK);
rcc_periph_clock_enable(RCC_USART2);
gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO_USART2_TX);
gpio_set_mode(GPIOA, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO_USART2_RX);
uint32_t baud = 57600;
uint32_t clock = 28000000;
USART2_BRR = ((2 * clock) + baud) / (2 * baud);
usart_set_databits(USART2, 8);
usart_set_stopbits(USART2, USART_STOPBITS_1);
usart_set_mode(USART2, USART_MODE_TX_RX);
usart_set_parity(USART2, USART_PARITY_NONE);
usart_set_flow_control(USART2, USART_FLOWCONTROL_NONE);
usart_enable(USART2);
usart_puts(USART2, "ready to receive.\r\n");
gpio_set(GPIOA, GPIO5);
while(1)
{
uint16_t c;
c = usart_recv_blocking(USART2);
usart_send_blocking(USART2, toupper(c));
gpio_toggle(GPIOA, GPIO5);
}
}
/*
* These functions are setting up the whole clock system for the most common
* input clock and output clock configurations.
*/
void rcc_clock_setup_in_hsi_out_64mhz(void)
{
/* Enable internal high-speed oscillator. */
rcc_osc_on(HSI);
rcc_wait_for_osc_ready(HSI);
/* Select HSI as SYSCLK source. */
rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_HSICLK);
/*
* Set prescalers for AHB, ADC, ABP1, ABP2.
* Do this before touching the PLL (TODO: why?).
*/
rcc_set_hpre(RCC_CFGR_HPRE_SYSCLK_NODIV); /* Max. 72MHz */
rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV8); /* Max. 14MHz */
rcc_set_ppre1(RCC_CFGR_PPRE1_HCLK_DIV2); /* Max. 36MHz */
rcc_set_ppre2(RCC_CFGR_PPRE2_HCLK_NODIV); /* Max. 72MHz */
/*
* Sysclk is running with 64MHz -> 2 waitstates.
* 0WS from 0-24MHz
* 1WS from 24-48MHz
* 2WS from 48-72MHz
*/
flash_set_ws(FLASH_LATENCY_2WS);
/*
* Set the PLL multiplication factor to 16.
* 8MHz (internal) * 16 (multiplier) / 2 (PLLSRC_HSI_CLK_DIV2) = 64MHz
*/
rcc_set_pll_multiplication_factor(RCC_CFGR_PLLMUL_PLL_CLK_MUL16);
/* Select HSI/2 as PLL source. */
rcc_set_pll_source(RCC_CFGR_PLLSRC_HSI_CLK_DIV2);
/* Enable PLL oscillator and wait for it to stabilize. */
rcc_osc_on(PLL);
rcc_wait_for_osc_ready(PLL);
/* Select PLL as SYSCLK source. */
rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_PLLCLK);
}
/**
* Setup clocks to run from PLL.
* The arguments provide the pll source, multipliers, dividers, all that's
* needed to establish a system clock.
* @param clock clock information structure
*/
void rcc_clock_setup_pll(const struct rcc_clock_scale *clock)
{
if (clock->pllsrc == RCC_CFGR_PLLSRC_HSE_PREDIV) {
rcc_osc_on(RCC_HSE);
rcc_wait_for_osc_ready(RCC_HSE);
} else {
rcc_osc_on(RCC_HSI);
rcc_wait_for_osc_ready(RCC_HSI);
}
rcc_osc_off(RCC_PLL);
rcc_usb_prescale_1_5();
if (clock->usbdiv1) {
rcc_usb_prescale_1();
}
rcc_wait_for_osc_not_ready(RCC_PLL);
rcc_set_pll_source(clock->pllsrc);
rcc_set_pll_multiplier(clock->pllmul);
rcc_set_prediv(clock->plldiv);
/* Enable PLL oscillator and wait for it to stabilize. */
rcc_osc_on(RCC_PLL);
rcc_wait_for_osc_ready(RCC_PLL);
/* Configure flash settings. */
flash_prefetch_enable();
flash_set_ws(clock->flash_waitstates);
rcc_set_hpre(clock->hpre);
rcc_set_ppre2(clock->ppre2);
rcc_set_ppre1(clock->ppre1);
/* Select PLL as SYSCLK source. */
rcc_set_sysclk_source(RCC_CFGR_SW_PLL);
/* Wait for PLL clock to be selected. */
rcc_wait_for_sysclk_status(RCC_PLL);
/* Set the peripheral clock frequencies used. */
rcc_ahb_frequency = clock->ahb_frequency;
rcc_apb1_frequency = clock->apb1_frequency;
rcc_apb2_frequency = clock->apb2_frequency;
}
void rcc_clock_setup_in_hsi_out_48mhz(void)
{
rcc_osc_on(HSI);
rcc_wait_for_osc_ready(HSI);
rcc_set_sysclk_source(HSI);
rcc_set_hpre(RCC_CFGR_HPRE_NODIV);
rcc_set_ppre(RCC_CFGR_PPRE_NODIV);
flash_set_ws(FLASH_ACR_LATENCY_024_048MHZ);
/* 8MHz * 12 / 2 = 24MHz */
rcc_set_pll_multiplication_factor(RCC_CFGR_PLLMUL_MUL16);
RCC_CFGR &= RCC_CFGR_PLLSRC;
rcc_osc_on(PLL);
rcc_wait_for_osc_ready(PLL);
rcc_set_sysclk_source(PLL);
rcc_ppre_frequency = 48000000;
rcc_core_frequency = 48000000;
}
void rcc_clock_setup_in_hsi_out_40mhz(void)
{
rcc_osc_on(RCC_HSI);
rcc_wait_for_osc_ready(RCC_HSI);
rcc_set_sysclk_source(RCC_HSI);
rcc_set_hpre(RCC_CFGR_HPRE_NODIV);
rcc_set_ppre(RCC_CFGR_PPRE_NODIV);
flash_set_ws(FLASH_ACR_LATENCY_024_048MHZ);
/* 8MHz * 10 / 2 = 40MHz */
rcc_set_pll_multiplication_factor(RCC_CFGR_PLLMUL_MUL10);
RCC_CFGR &= ~RCC_CFGR_PLLSRC;
rcc_osc_on(RCC_PLL);
rcc_wait_for_osc_ready(RCC_PLL);
rcc_set_sysclk_source(RCC_PLL);
rcc_apb1_frequency = 40000000;
rcc_ahb_frequency = 40000000;
}
void rcc_clock_setup_in_hsi_out_16mhz(void)
{
rcc_osc_on(HSI);
rcc_wait_for_osc_ready(HSI);
rcc_set_sysclk_source(HSI);
rcc_set_hpre(RCC_CFGR_HPRE_NODIV);
rcc_set_ppre(RCC_CFGR_PPRE_NODIV);
flash_set_ws(FLASH_ACR_LATENCY_000_024MHZ);
/* 8MHz * 4 / 2 = 16MHz */
rcc_set_pll_multiplication_factor(RCC_CFGR_PLLMUL_MUL4);
RCC_CFGR &= ~RCC_CFGR_PLLSRC;
rcc_osc_on(PLL);
rcc_wait_for_osc_ready(PLL);
rcc_set_sysclk_source(PLL);
rcc_apb1_frequency = 16000000;
rcc_ahb_frequency = 16000000;
}
/**
* Set System Clock PLL at 48MHz from HSI
*/
void rcc_clock_setup_in_hsi_out_48mhz(void)
{
rcc_osc_on(RCC_HSI);
rcc_wait_for_osc_ready(RCC_HSI);
rcc_set_sysclk_source(RCC_HSI);
rcc_set_hpre(RCC_CFGR_HPRE_NODIV);
rcc_set_ppre(RCC_CFGR_PPRE_NODIV);
flash_prefetch_enable();
flash_set_ws(FLASH_ACR_LATENCY_024_048MHZ);
/* 8MHz * 12 / 2 = 48MHz */
rcc_set_pll_multiplication_factor(RCC_CFGR_PLLMUL_MUL12);
rcc_set_pll_source(RCC_CFGR_PLLSRC_HSI_CLK_DIV2);
rcc_osc_on(RCC_PLL);
rcc_wait_for_osc_ready(RCC_PLL);
rcc_set_sysclk_source(RCC_PLL);
rcc_apb1_frequency = 48000000;
rcc_ahb_frequency = 48000000;
}
void rcc_clock_setup_pll(const clock_scale_t *clock)
{
/* Enable internal high-speed oscillator. */
rcc_osc_on(HSI);
rcc_wait_for_osc_ready(HSI);
/*
* Set prescalers for AHB, ADC, ABP1, ABP2.
* Do this before touching the PLL (TODO: why?).
*/
rcc_set_hpre(clock->hpre);
rcc_set_ppre1(clock->ppre1);
rcc_set_ppre2(clock->ppre2);
rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_PWREN);
pwr_set_vos_scale(clock->voltage_scale);
/* I guess this should be in the settings? */
flash_64bit_enable();
flash_prefetch_enable();
/* Configure flash settings. */
flash_set_ws(clock->flash_config);
rcc_set_pll_configuration(clock->pll_source, clock->pll_mul,
clock->pll_div);
/* Enable PLL oscillator and wait for it to stabilize. */
rcc_osc_on(PLL);
rcc_wait_for_osc_ready(PLL);
/* Select PLL as SYSCLK source. */
rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_PLLCLK);
/* Set the peripheral clock frequencies used. */
rcc_ppre1_frequency = clock->apb1_frequency;
rcc_ppre2_frequency = clock->apb2_frequency;
}
/**
* Set up sysclock with PLL from HSI16
* @param clock full struct with desired parameters
*/
void rcc_clock_setup_pll(const struct rcc_clock_scale *clock)
{
/* Turn on the appropriate source for the PLL */
if (clock->pll_source == RCC_CFGR_PLLSRC_HSE_CLK) {
rcc_osc_on(RCC_HSE);
rcc_wait_for_osc_ready(RCC_HSE);
} else {
rcc_osc_on(RCC_HSI16);
rcc_wait_for_osc_ready(RCC_HSI16);
}
rcc_set_hpre(clock->hpre);
rcc_set_ppre1(clock->ppre1);
rcc_set_ppre2(clock->ppre2);
rcc_periph_clock_enable(RCC_PWR);
pwr_set_vos_scale(clock->voltage_scale);
rcc_osc_off(RCC_PLL);
while (rcc_is_osc_ready(RCC_PLL));
flash_prefetch_enable();
flash_set_ws(clock->flash_waitstates);
/* Set up the PLL */
rcc_set_pll_multiplier(clock->pll_mul);
rcc_set_pll_divider(clock->pll_div);
rcc_osc_on(RCC_PLL);
rcc_wait_for_osc_ready(RCC_PLL);
rcc_set_sysclk_source(RCC_PLL);
/* Set the peripheral clock frequencies used. */
rcc_ahb_frequency = clock->ahb_frequency;
rcc_apb1_frequency = clock->apb1_frequency;
rcc_apb2_frequency = clock->apb2_frequency;
}
void rcc_clock_setup_msi(const clock_scale_t *clock)
{
/* Enable internal multi-speed oscillator. */
uint32_t reg = RCC_ICSCR;
reg &= ~(RCC_ICSCR_MSIRANGE_MASK << RCC_ICSCR_MSIRANGE_SHIFT);
reg |= (clock->msi_range << RCC_ICSCR_MSIRANGE_SHIFT);
RCC_ICSCR = reg;
rcc_osc_on(MSI);
rcc_wait_for_osc_ready(MSI);
/* Select MSI as SYSCLK source. */
rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_MSICLK);
/*
* Set prescalers for AHB, ADC, ABP1, ABP2.
* Do this before touching the PLL (TODO: why?).
*/
rcc_set_hpre(clock->hpre);
rcc_set_ppre1(clock->ppre1);
rcc_set_ppre2(clock->ppre2);
rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_PWREN);
pwr_set_vos_scale(clock->voltage_scale);
/* I guess this should be in the settings? */
flash_64bit_enable();
flash_prefetch_enable();
/* Configure flash settings. */
flash_set_ws(clock->flash_config);
/* Set the peripheral clock frequencies used. */
rcc_apb1_frequency = clock->apb1_frequency;
rcc_apb2_frequency = clock->apb2_frequency;
}
void pcb_flash_setup(void)
{
// set waitstates
flash_set_ws(FLASH_ACR_LATENCY_5WS);
flash_unlock();
}
void clock_setup()
{
/*
RCC_CR |= (uint32_t)0x00000001;
RCC_CFGR = 0x00000000;
RCC_CR &= (uint32_t)0xFEF6FFFF;
RCC_PLLCFGR = 0x24003010;
RCC_CR &= (uint32_t)0xFFFBFFFF;
RCC_CIR = 0x00000000;
SCB_VTOR = 0x08000000;
*/
/*
.pllm = 16,
.plln = 336,
.pllp = 2,
.pllq = 7,
.hpre = RCC_CFGR_HPRE_DIV_NONE,
.ppre1 = RCC_CFGR_PPRE_DIV_4,
.ppre2 = RCC_CFGR_PPRE_DIV_2,
.flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE |
FLASH_ACR_LATENCY_5WS,
.apb1_frequency = 42000000,
.apb2_frequency = 84000000,
*/
/* Enable internal high-speed oscillator. */
rcc_osc_on(RCC_HSI);
rcc_wait_for_osc_ready(RCC_HSI);
/* Select HSI as SYSCLK source. */
rcc_set_sysclk_source(RCC_CFGR_SW_HSI);
pwr_set_vos_scale(PWR_SCALE1);
rcc_set_main_pll_hsi(16, 336, 2, 8, 0);
/* Enable PLL oscillator and wait for it to stabilize. */
rcc_osc_on(RCC_PLL);
rcc_wait_for_osc_ready(RCC_PLL);
/* Configure flash settings. */
flash_set_ws(FLASH_ACR_ICE | FLASH_ACR_DCE |
FLASH_ACR_LATENCY_5WS);
/* Select PLL as SYSCLK source. */
rcc_set_sysclk_source(RCC_CFGR_SW_PLL);
rcc_set_hpre(RCC_CFGR_HPRE_DIV_NONE);
rcc_set_ppre1(RCC_CFGR_PPRE_DIV_4);
rcc_set_ppre2(RCC_CFGR_PPRE_DIV_2);
/* Wait for PLL clock to be selected. */
rcc_wait_for_sysclk_status(RCC_PLL);
rcc_ahb_frequency = 168000000;
rcc_apb1_frequency = 42000000;
rcc_apb2_frequency = 84000000;
/* Disable internal high-speed oscillator. */
rcc_osc_off(RCC_HSI);
// clock rate is 1680 to get 10uS interrupt rate
systick_set_reload(168);
systick_set_clocksource(STK_CSR_CLKSOURCE_AHB);
systick_counter_enable();
systick_interrupt_enable();
rcc_periph_clock_enable(RCC_GPIOA);
rcc_periph_clock_enable(RCC_GPIOB);
rcc_periph_clock_enable(RCC_GPIOC);
etk::set_tick_rate(1);
}
void gpio_setup(void) {
rcc_osc_on(RCC_HSE);
rcc_wait_for_osc_ready(RCC_HSE);
rcc_osc_off(RCC_PLL);
rcc_wait_for_osc_not_ready(RCC_PLL);
rcc_set_prediv(RCC_CFGR2_PREDIV_NODIV);
rcc_set_pll_source(RCC_CFGR_PLLSRC_HSE_PREDIV);
rcc_set_pll_multiplier(RCC_CFGR_PLLMUL_PLL_IN_CLK_X3);
rcc_osc_on(RCC_PLL);
rcc_wait_for_osc_ready(RCC_PLL);
rcc_set_hpre(RCC_CFGR_HPRE_DIV_NONE);
rcc_set_ppre2(RCC_CFGR_PPRE1_DIV_2);
rcc_set_ppre1(RCC_CFGR_PPRE2_DIV_NONE);
flash_set_ws(FLASH_ACR_PRFTBE | FLASH_ACR_LATENCY_2WS);
rcc_set_sysclk_source(RCC_CFGR_SW_PLL);
rcc_wait_for_sysclk_status(RCC_PLL);
rcc_ahb_frequency = 60000000;
rcc_apb1_frequency = 30000000;
rcc_apb2_frequency = 30000000;
rcc_periph_clock_enable(RCC_GPIOA);
rcc_periph_clock_enable(RCC_GPIOB);
rcc_periph_clock_enable(RCC_GPIOC);
rcc_periph_clock_enable(RCC_GPIOD);
rcc_periph_clock_enable(RCC_GPIOE);
rcc_periph_clock_enable(RCC_USART1);
rcc_periph_clock_enable(RCC_TIM2);
rcc_periph_clock_enable(RCC_DAC1);
nvic_enable_irq(NVIC_TIM1_CC_IRQ);
nvic_enable_irq(NVIC_TIM2_IRQ);
nvic_enable_irq(NVIC_TIM3_IRQ);
nvic_enable_irq(NVIC_ADC1_2_IRQ);
/* Unused pins. */
gpio_mode_setup(GPIOA, GPIO_MODE_INPUT, GPIO_PUPD_PULLDOWN,
GPIO0 |
GPIO2 |
GPIO6 |
GPIO11 |
GPIO12
);
gpio_mode_setup(GPIOB, GPIO_MODE_INPUT, GPIO_PUPD_PULLDOWN,
GPIO0 |
GPIO1 |
GPIO2 |
GPIO6 |
GPIO7 |
GPIO8 |
GPIO10 |
GPIO11 |
GPIO12 |
GPIO13 |
GPIO14 |
GPIO15
);
gpio_mode_setup(GPIOC, GPIO_MODE_INPUT, GPIO_PUPD_PULLDOWN,
GPIO0 |
GPIO1 |
GPIO2 |
GPIO3 |
GPIO4 |
GPIO5 |
GPIO6 |
GPIO7 |
GPIO8 |
GPIO13
);
gpio_mode_setup(GPIOD, GPIO_MODE_INPUT, GPIO_PUPD_PULLDOWN,
GPIO0 |
GPIO1 |
GPIO2 |
GPIO3 |
GPIO4 |
GPIO5 |
GPIO6 |
GPIO7 |
GPIO11 |
GPIO12 |
GPIO13 |
GPIO14 |
GPIO15
);
gpio_mode_setup(GPIOE, GPIO_MODE_INPUT, GPIO_PUPD_PULLDOWN,
GPIO0 |
GPIO1 |
GPIO3 |
GPIO4 |
GPIO7 |
GPIO8 |
GPIO10 |
GPIO11 |
GPIO12 |
GPIO13 |
GPIO14
);
// gpio_mode_setup(GPIOA, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, GPIO5);
gpio_mode_setup(GPIOC, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, GPIO3);
/* Timer 2, IC2 */
gpio_mode_setup(GPIOA, GPIO_MODE_AF, GPIO_PUPD_PULLUP, GPIO1);
gpio_set_af(GPIOA, GPIO_AF1, GPIO1);
/* USART2 */
gpio_mode_setup(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO9 | GPIO10);
gpio_set_af(GPIOA, GPIO_AF7, GPIO9 | GPIO10);
/* ADC1, channel 4, no filter, fast channel. */
gpio_mode_setup(GPIOA, GPIO_MODE_ANALOG, GPIO_PUPD_NONE, GPIO3);
/* ADC2, channel 4, no filter, fast channel. */
gpio_mode_setup(GPIOA, GPIO_MODE_ANALOG, GPIO_PUPD_NONE, GPIO7);
/* ADC3, channel 2, no filter, fast channel. */
gpio_mode_setup(GPIOE, GPIO_MODE_ANALOG, GPIO_PUPD_NONE, GPIO9);
/* ADC4, channel 2, no filter, fast channel. */
gpio_mode_setup(GPIOE, GPIO_MODE_ANALOG, GPIO_PUPD_NONE, GPIO15);
/* VCTCXO steering, DAC output. */
gpio_mode_setup(GPIOA, GPIO_MODE_ANALOG, GPIO_PUPD_NONE, GPIO4);
}
