static void write_rtl8225(struct net_device *dev, u8 adr, u16 data)
{
int i;
u16 out, select;
u8 bit;
u32 bangdata = (data << 4) | (adr & 0xf);
out = read_nic_word(dev, RFPinsOutput) & 0xfff3;
write_nic_word(dev, RFPinsEnable,
(read_nic_word(dev, RFPinsEnable) | 0x7));
select = read_nic_word(dev, RFPinsSelect);
write_nic_word(dev, RFPinsSelect, select | 0x7 |
SW_CONTROL_GPIO);
force_pci_posting(dev);
udelay(10);
write_nic_word(dev, RFPinsOutput, out | BB_HOST_BANG_EN);
force_pci_posting(dev);
udelay(2);
write_nic_word(dev, RFPinsOutput, out);
force_pci_posting(dev);
udelay(10);
for (i = 15; i >= 0; i--) {
bit = (bangdata & (1 << i)) >> i;
write_nic_word(dev, RFPinsOutput, bit | out);
write_nic_word(dev, RFPinsOutput, bit | out | BB_HOST_BANG_CLK);
write_nic_word(dev, RFPinsOutput, bit | out | BB_HOST_BANG_CLK);
i--;
bit = (bangdata & (1 << i)) >> i;
write_nic_word(dev, RFPinsOutput, bit | out | BB_HOST_BANG_CLK);
write_nic_word(dev, RFPinsOutput, bit | out | BB_HOST_BANG_CLK);
write_nic_word(dev, RFPinsOutput, bit | out);
}
write_nic_word(dev, RFPinsOutput, out | BB_HOST_BANG_EN);
force_pci_posting(dev);
udelay(10);
write_nic_word(dev, RFPinsOutput, out | BB_HOST_BANG_EN);
write_nic_word(dev, RFPinsSelect, select | SW_CONTROL_GPIO);
rtl8185_rf_pins_enable(dev);
}
void rtl8225_rf_sleep(struct net_device *dev)
{
write_rtl8225(dev,0x4,0xdff);
force_pci_posting(dev);
mdelay(1);
rtl8180_set_anaparam(dev, RTL8225_ANAPARAM_SLEEP);
rtl8185_set_anaparam2(dev, RTL8225_ANAPARAM2_SLEEP);
force_pci_posting(dev);
}
void eprom_ck_cycle(struct net_device *dev)
{
write_nic_byte(dev, EPROM_CMD,
(1<<EPROM_CK_SHIFT) | read_nic_byte(dev,EPROM_CMD));
force_pci_posting(dev);
udelay(EPROM_DELAY);
write_nic_byte(dev, EPROM_CMD,
read_nic_byte(dev, EPROM_CMD) &~ (1<<EPROM_CK_SHIFT));
force_pci_posting(dev);
udelay(EPROM_DELAY);
}
static void eprom_ck_cycle(struct net_device *dev)
{
u8 cmdreg;
read_nic_byte_E(dev, EPROM_CMD, &cmdreg);
write_nic_byte_E(dev, EPROM_CMD, cmdreg | EPROM_CK_BIT);
force_pci_posting(dev);
udelay(EPROM_DELAY);
read_nic_byte_E(dev, EPROM_CMD, &cmdreg);
write_nic_byte_E(dev, EPROM_CMD, cmdreg & ~EPROM_CK_BIT);
force_pci_posting(dev);
udelay(EPROM_DELAY);
}
void rtl8225_rf_wakeup(struct net_device *dev)
{
write_rtl8225(dev,0x4,0x9ff);
rtl8180_set_anaparam(dev, RTL8225_ANAPARAM_ON);
rtl8185_set_anaparam2(dev, RTL8225_ANAPARAM2_ON);
force_pci_posting(dev);
}
u32 eprom_read(struct net_device *dev, u32 addr)
{
struct r8180_priv *priv = ieee80211_priv(dev);
short read_cmd[]={1,1,0};
short addr_str[8];
int i;
int addr_len;
u32 ret;
ret=0;
//enable EPROM programming
write_nic_byte(dev, EPROM_CMD,
(EPROM_CMD_PROGRAM<<EPROM_CMD_OPERATING_MODE_SHIFT));
force_pci_posting(dev);
udelay(EPROM_DELAY);
if (priv->epromtype==EPROM_93c56){
addr_str[7]=addr & 1;
addr_str[6]=addr & (1<<1);
addr_str[5]=addr & (1<<2);
addr_str[4]=addr & (1<<3);
addr_str[3]=addr & (1<<4);
addr_str[2]=addr & (1<<5);
addr_str[1]=addr & (1<<6);
addr_str[0]=addr & (1<<7);
addr_len=8;
}else{
addr_str[5]=addr & 1;
addr_str[4]=addr & (1<<1);
addr_str[3]=addr & (1<<2);
addr_str[2]=addr & (1<<3);
addr_str[1]=addr & (1<<4);
addr_str[0]=addr & (1<<5);
addr_len=6;
}
eprom_cs(dev, 1);
eprom_ck_cycle(dev);
eprom_send_bits_string(dev, read_cmd, 3);
eprom_send_bits_string(dev, addr_str, addr_len);
//keep chip pin D to low state while reading.
//I'm unsure if it is necessary, but anyway shouldn't hurt
eprom_w(dev, 0);
for(i=0;i<16;i++){
//eeprom needs a clk cycle between writing opcode&adr
//and reading data. (eeprom outs a dummy 0)
eprom_ck_cycle(dev);
ret |= (eprom_r(dev)<<(15-i));
}
eprom_cs(dev, 0);
eprom_ck_cycle(dev);
//disable EPROM programming
write_nic_byte(dev, EPROM_CMD,
(EPROM_CMD_NORMAL<<EPROM_CMD_OPERATING_MODE_SHIFT));
return ret;
}
void rtl8225_rf_close(struct net_device *dev)
{
write_rtl8225(dev, 0x4, 0x1f);
force_pci_posting(dev);
mdelay(1);
rtl8180_set_anaparam(dev, RTL8225_ANAPARAM_OFF);
rtl8185_set_anaparam2(dev, RTL8225_ANAPARAM2_OFF);
}
void eprom_w(struct net_device *dev,short bit)
{
if(bit)
write_nic_byte(dev, EPROM_CMD, (1<<EPROM_W_SHIFT) | \
read_nic_byte(dev,EPROM_CMD));
else
write_nic_byte(dev, EPROM_CMD, read_nic_byte(dev,EPROM_CMD)\
&~(1<<EPROM_W_SHIFT));
force_pci_posting(dev);
udelay(EPROM_DELAY);
}
void rtl8225_rf_close(struct net_device *dev)
{
struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
if( priv->bSurpriseRemoved == _FALSE) {
write_rtl8225(dev, 0x4, 0x1f);
force_pci_posting(dev);
mdelay(1);
rtl8180_set_anaparam(dev, RTL8225_ANAPARAM_OFF);
rtl8185_set_anaparam2(dev, RTL8225_ANAPARAM2_OFF);
}
}
static void eprom_w(struct net_device *dev, short bit)
{
u8 cmdreg;
read_nic_byte_E(dev, EPROM_CMD, &cmdreg);
if (bit)
write_nic_byte_E(dev, EPROM_CMD, cmdreg | EPROM_W_BIT);
else
write_nic_byte_E(dev, EPROM_CMD, cmdreg & ~EPROM_W_BIT);
force_pci_posting(dev);
udelay(EPROM_DELAY);
}
void eprom_cs(struct net_device *dev, short bit)
{
if(bit)
write_nic_byte(dev, EPROM_CMD,
(1<<EPROM_CS_SHIFT) | \
read_nic_byte(dev, EPROM_CMD)); //enable EPROM
else
write_nic_byte(dev, EPROM_CMD, read_nic_byte(dev, EPROM_CMD)\
&~(1<<EPROM_CS_SHIFT)); //disable EPROM
force_pci_posting(dev);
udelay(EPROM_DELAY);
}
void rtl8225z2_rf_set_chan(struct net_device *dev, short ch)
{
/*
short gset = (priv->ieee80211->state == IEEE80211_LINKED &&
ieee80211_is_54g(priv->ieee80211->current_network)) ||
priv->ieee80211->iw_mode == IW_MODE_MONITOR;
*/
rtl8225z2_SetTXPowerLevel(dev, ch);
RF_WriteReg(dev, 0x7, rtl8225_chan[ch]);
//YJ,add,080828, if set channel failed, write again
if((RF_ReadReg(dev, 0x7) & 0x0F80) != rtl8225_chan[ch])
{
RF_WriteReg(dev, 0x7, rtl8225_chan[ch]);
}
mdelay(1);
force_pci_posting(dev);
mdelay(10);
//deleted by David : 2006/8/9
#if 0
write_nic_byte(dev,SIFS,0x22);// SIFS: 0x22
if(gset)
write_nic_byte(dev,DIFS,20); //DIFS: 20
else
write_nic_byte(dev,DIFS,0x24); //DIFS: 36
if(priv->ieee80211->state == IEEE80211_LINKED &&
ieee80211_is_shortslot(priv->ieee80211->current_network))
write_nic_byte(dev,SLOT,0x9); //SLOT: 9
else
write_nic_byte(dev,SLOT,0x14); //SLOT: 20 (0x14)
if(gset){
write_nic_byte(dev,EIFS,91 - 20); // EIFS: 91 (0x5B)
write_nic_byte(dev,CW_VAL,0x73); //CW VALUE: 0x37
//DMESG("using G net params");
}else{
write_nic_byte(dev,EIFS,91 - 0x24); // EIFS: 91 (0x5B)
write_nic_byte(dev,CW_VAL,0xa5); //CW VALUE: 0x37
//DMESG("using B net params");
}
#endif
}
void rtl8225z2_rf_set_chan(struct net_device *dev, short ch)
{
rtl8225z2_SetTXPowerLevel(dev, ch);
RF_WriteReg(dev, 0x7, rtl8225_chan[ch]);
if ((RF_ReadReg(dev, 0x7) & 0x0F80) != rtl8225_chan[ch])
RF_WriteReg(dev, 0x7, rtl8225_chan[ch]);
mdelay(1);
force_pci_posting(dev);
mdelay(10);
}
void rtl8225_rf_set_chan(struct net_device *dev, short ch)
{
struct r8180_priv *priv = ieee80211_priv(dev);
short gset = (priv->ieee80211->state == IEEE80211_LINKED &&
ieee80211_is_54g(priv->ieee80211->current_network)) ||
priv->ieee80211->iw_mode == IW_MODE_MONITOR;
int eifs_addr;
if(NIC_8187 == priv->card_8187) {
eifs_addr = EIFS_8187;
} else {
eifs_addr = EIFS_8187B;
}
rtl8225_SetTXPowerLevel(dev, ch);
write_rtl8225(dev, 0x7, rtl8225_chan[ch]);
force_pci_posting(dev);
mdelay(10);
write_nic_byte(dev,SIFS,0x22);// SIFS: 0x22
if(gset)
write_nic_byte(dev,DIFS,20); //DIFS: 20
else
write_nic_byte(dev,DIFS,0x24); //DIFS: 36
if(priv->ieee80211->state == IEEE80211_LINKED &&
ieee80211_is_shortslot(priv->ieee80211->current_network))
write_nic_byte(dev,SLOT,0x9); //SLOT: 9
else
write_nic_byte(dev,SLOT,0x14); //SLOT: 20 (0x14)
if(gset){
write_nic_byte(dev,eifs_addr,91 - 20); // EIFS: 91 (0x5B)
write_nic_byte(dev,CW_VAL,0x73); //CW VALUE: 0x37
//DMESG("using G net params");
}else{
write_nic_byte(dev,eifs_addr,91 - 0x24); // EIFS: 91 (0x5B)
write_nic_byte(dev,CW_VAL,0xa5); //CW VALUE: 0x37
//DMESG("using B net params");
}
}
static void eprom_cs(struct net_device *dev, short bit)
{
u8 cmdreg;
read_nic_byte_E(dev, EPROM_CMD, &cmdreg);
if (bit)
/* enable EPROM */
write_nic_byte_E(dev, EPROM_CMD, cmdreg | EPROM_CS_BIT);
else
/* disable EPROM */
write_nic_byte_E(dev, EPROM_CMD, cmdreg & ~EPROM_CS_BIT);
force_pci_posting(dev);
udelay(EPROM_DELAY);
}
static void rtl8225_host_pci_init(struct net_device *dev)
{
write_nic_word(dev, RFPinsOutput, 0x480);
rtl8185_rf_pins_enable(dev);
write_nic_word(dev, RFPinsSelect, 0x88 | SW_CONTROL_GPIO);
write_nic_byte(dev, GP_ENABLE, 0);
force_pci_posting(dev);
mdelay(200);
/* bit 6 is for RF on/off detection */
write_nic_word(dev, GP_ENABLE, 0xff & (~(1 << 6)));
}
void rtl8225_rf_set_chan(struct net_device *dev, short ch)
{
struct r8180_priv *priv = ieee80211_priv(dev);
short gset = (priv->ieee80211->state == IEEE80211_LINKED &&
ieee80211_is_54g(priv->ieee80211->current_network)) ||
priv->ieee80211->iw_mode == IW_MODE_MONITOR;
rtl8225_SetTXPowerLevel(dev, ch);
write_rtl8225(dev, 0x7, rtl8225_chan[ch]);
force_pci_posting(dev);
mdelay(10);
// A mode sifs 0x44, difs 34-14, slot 9, eifs 23, cwm 3, cwM 7, ctstoself 0x10
if(gset){
write_nic_byte(dev,SIFS,0x22);// SIFS: 0x22
write_nic_byte(dev,DIFS,0x14); //DIFS: 20
//write_nic_byte(dev,DIFS,20); //DIFS: 20
}else{
write_nic_byte(dev,SIFS,0x44);// SIFS: 0x22
write_nic_byte(dev,DIFS,50 - 14); //DIFS: 36
}
if(priv->ieee80211->state == IEEE80211_LINKED &&
ieee80211_is_shortslot(priv->ieee80211->current_network))
write_nic_byte(dev,SLOT,0x9); //SLOT: 9
else
write_nic_byte(dev,SLOT,0x14); //SLOT: 20 (0x14)
if(gset){
write_nic_byte(dev,EIFS,81);//91 - 20); // EIFS: 91 (0x5B)
write_nic_byte(dev,CW_VAL,0x73); //CW VALUE: 0x37
//DMESG("using G net params");
}else{
write_nic_byte(dev,EIFS,81); // EIFS: 91 (0x5B)
write_nic_byte(dev,CW_VAL,0xa5); //CW VALUE: 0x37
//DMESG("using B net params");
}
}
void rtl8225_host_pci_init(struct net_device *dev)
{
write_nic_word(dev, RFPinsOutput, 0x480);
rtl8185_rf_pins_enable(dev);
//if(priv->card_8185 == 2 && priv->enable_gpio0 ) /* version D */
//write_nic_word(dev, RFPinsSelect, 0x88);
//else
write_nic_word(dev, RFPinsSelect, 0x88 | SW_CONTROL_GPIO); /* 0x488 | SW_CONTROL_GPIO */
write_nic_byte(dev, GP_ENABLE, 0);
force_pci_posting(dev);
mdelay(200);
write_nic_word(dev, GP_ENABLE, 0xff & (~(1<<6))); /* bit 6 is for RF on/off detection */
}
static void rtl8225_rf_set_chan(struct net_device *dev, short ch)
{
struct r8180_priv *priv = ieee80211_priv(dev);
short gset = (priv->ieee80211->state == IEEE80211_LINKED &&
ieee80211_is_54g(priv->ieee80211->current_network)) ||
priv->ieee80211->iw_mode == IW_MODE_MONITOR;
rtl8225_SetTXPowerLevel(dev, ch);
write_rtl8225(dev, 0x7, rtl8225_chan[ch]);
force_pci_posting(dev);
mdelay(10);
if (gset) {
write_nic_byte(dev, SIFS, 0x22);
write_nic_byte(dev, DIFS, 0x14);
} else {
write_nic_byte(dev, SIFS, 0x44);
write_nic_byte(dev, DIFS, 0x24);
}
if (priv->ieee80211->state == IEEE80211_LINKED &&
ieee80211_is_shortslot(priv->ieee80211->current_network))
write_nic_byte(dev, SLOT, 0x9);
else
write_nic_byte(dev, SLOT, 0x14);
if (gset) {
write_nic_byte(dev, EIFS, 81);
write_nic_byte(dev, CW_VAL, 0x73);
} else {
write_nic_byte(dev, EIFS, 81);
write_nic_byte(dev, CW_VAL, 0xa5);
}
}
void rtl8225z2_SetTXPowerLevel(struct net_device *dev, short ch)
{
struct r8180_priv *priv = ieee80211_priv(dev);
// int GainIdx;
// int GainSetting;
//int i;
//u8 power;
//u8 *cck_power_table;
u8 max_cck_power_level;
//u8 min_cck_power_level;
u8 max_ofdm_power_level;
u8 min_ofdm_power_level;
// u8 cck_power_level = 0xff & priv->chtxpwr[ch];//-by amy 080312
// u8 ofdm_power_level = 0xff & priv->chtxpwr_ofdm[ch];//-by amy 080312
char cck_power_level = (char)(0xff & priv->chtxpwr[ch]);//+by amy 080312
char ofdm_power_level = (char)(0xff & priv->chtxpwr_ofdm[ch]);//+by amy 080312
#if 0
//
// CCX 2 S31, AP control of client transmit power:
// 1. We shall not exceed Cell Power Limit as possible as we can.
// 2. Tolerance is +/- 5dB.
// 3. 802.11h Power Contraint takes higher precedence over CCX Cell Power Limit.
//
// TODO:
// 1. 802.11h power contraint
//
// 071011, by rcnjko.
//
if( priv->OpMode == RT_OP_MODE_INFRASTRUCTURE &&
priv->bWithCcxCellPwr &&
ch == priv->dot11CurrentChannelNumber)
{
u8 CckCellPwrIdx = DbmToTxPwrIdx(dev, WIRELESS_MODE_B, pMgntInfo->CcxCellPwr);
u8 OfdmCellPwrIdx = DbmToTxPwrIdx(dev, WIRELESS_MODE_G, pMgntInfo->CcxCellPwr);
printk("CCX Cell Limit: %d dBm => CCK Tx power index : %d, OFDM Tx power index: %d\n",
priv->CcxCellPwr, CckCellPwrIdx, OfdmCellPwrIdx);
printk("EEPROM channel(%d) => CCK Tx power index: %d, OFDM Tx power index: %d\n",
channel, CckTxPwrIdx, OfdmTxPwrIdx);
if(cck_power_level > CckCellPwrIdx)
cck_power_level = CckCellPwrIdx;
if(ofdm_power_level > OfdmCellPwrIdx)
ofdm_power_level = OfdmCellPwrIdx;
printk("Altered CCK Tx power index : %d, OFDM Tx power index: %d\n",
CckTxPwrIdx, OfdmTxPwrIdx);
}
#endif
#ifdef ENABLE_DOT11D
if(IS_DOT11D_ENABLE(priv->ieee80211) &&
IS_DOT11D_STATE_DONE(priv->ieee80211) )
{
//PRT_DOT11D_INFO pDot11dInfo = GET_DOT11D_INFO(priv->ieee80211);
u8 MaxTxPwrInDbm = DOT11D_GetMaxTxPwrInDbm(priv->ieee80211, ch);
u8 CckMaxPwrIdx = DbmToTxPwrIdx(priv, WIRELESS_MODE_B, MaxTxPwrInDbm);
u8 OfdmMaxPwrIdx = DbmToTxPwrIdx(priv, WIRELESS_MODE_G, MaxTxPwrInDbm);
//printk("Max Tx Power dBm (%d) => CCK Tx power index : %d, OFDM Tx power index: %d\n", MaxTxPwrInDbm, CckMaxPwrIdx, OfdmMaxPwrIdx);
//printk("EEPROM channel(%d) => CCK Tx power index: %d, OFDM Tx power index: %d\n",
// ch, cck_power_level, ofdm_power_level);
if(cck_power_level > CckMaxPwrIdx)
cck_power_level = CckMaxPwrIdx;
if(ofdm_power_level > OfdmMaxPwrIdx)
ofdm_power_level = OfdmMaxPwrIdx;
}
//priv->CurrentCckTxPwrIdx = cck_power_level;
//priv->CurrentOfdmTxPwrIdx = ofdm_power_level;
#endif
max_cck_power_level = 15;
max_ofdm_power_level = 25; // 12 -> 25
min_ofdm_power_level = 10;
#ifdef CONFIG_RTL8185B
#ifdef CONFIG_RTL818X_S
if(cck_power_level > 35)
{
cck_power_level = 35;
}
//
// Set up CCK TXAGC. suggested by SD3 SY.
//
write_nic_byte(dev, CCK_TXAGC, (ZEBRA2_CCK_OFDM_GAIN_SETTING[(u8)cck_power_level]) );
//printk("CCK TX power is %x\n", (ZEBRA2_CCK_OFDM_GAIN_SETTING[cck_power_level]));
force_pci_posting(dev);
mdelay(1);
#else
/* CCK power setting */
if(cck_power_level > max_cck_power_level)
cck_power_level = max_cck_power_level;
cck_power_level += priv->cck_txpwr_base;
if(cck_power_level > 35)
cck_power_level = 35;
if(ch == 14)
cck_power_table = rtl8225z2_tx_power_cck_ch14;
else
cck_power_table = rtl8225z2_tx_power_cck;
for(i=0;i<8;i++){
power = cck_power_table[i];
write_phy_cck(dev, 0x44 + i, power);
}
//write_nic_byte(dev, TX_GAIN_CCK, power);
//2005.11.17,
write_nic_byte(dev, CCK_TXAGC, ZEBRA2_CCK_OFDM_GAIN_SETTING[(u8)cck_power_level]);
force_pci_posting(dev);
mdelay(1);
#endif
#endif
/* OFDM power setting */
// Old:
// if(ofdm_power_level > max_ofdm_power_level)
// ofdm_power_level = 35;
// ofdm_power_level += min_ofdm_power_level;
// Latest:
/* if(ofdm_power_level > (max_ofdm_power_level - min_ofdm_power_level))
ofdm_power_level = max_ofdm_power_level;
else
ofdm_power_level += min_ofdm_power_level;
ofdm_power_level += priv->ofdm_txpwr_base;
*/
if(ofdm_power_level > 35)
ofdm_power_level = 35;
// rtl8185_set_anaparam2(dev,RTL8225_ANAPARAM2_ON);
//rtl8185_set_anaparam2(dev, ANAPARM2_ASIC_ON);
if (priv->up == 0) {
//must add these for rtl8185B down, xiong-2006-11-21
write_phy_ofdm(dev,2,0x42);
write_phy_ofdm(dev,5,0);
write_phy_ofdm(dev,6,0x40);
write_phy_ofdm(dev,7,0);
write_phy_ofdm(dev,8,0x40);
}
//write_nic_byte(dev, TX_GAIN_OFDM, ofdm_power_level);
//2005.11.17,
#ifdef CONFIG_RTL818X_S
write_nic_byte(dev, OFDM_TXAGC, ZEBRA2_CCK_OFDM_GAIN_SETTING[(u8)ofdm_power_level]);
#else
write_nic_byte(dev, OFDM_TXAGC, ZEBRA2_CCK_OFDM_GAIN_SETTING[(u8)ofdm_power_level]*2);
#endif
if(ofdm_power_level<=11)
{
// write_nic_dword(dev,PHY_ADR,0x00005c87);
// write_nic_dword(dev,PHY_ADR,0x00005c89);
write_phy_ofdm(dev,0x07,0x5c);
write_phy_ofdm(dev,0x09,0x5c);
}
if(ofdm_power_level<=17)
{
// write_nic_dword(dev,PHY_ADR,0x00005487);
// write_nic_dword(dev,PHY_ADR,0x00005489);
write_phy_ofdm(dev,0x07,0x54);
write_phy_ofdm(dev,0x09,0x54);
}
else
{
// write_nic_dword(dev,PHY_ADR,0x00005087);
// write_nic_dword(dev,PHY_ADR,0x00005089);
write_phy_ofdm(dev,0x07,0x50);
write_phy_ofdm(dev,0x09,0x50);
}
force_pci_posting(dev);
mdelay(1);
}
void write_rtl8225(struct net_device *dev, u8 adr, u16 data)
{
#ifdef THOMAS_3WIRE
struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
struct usb_device *udev = priv->udev;
int status;
data = (data << 4) | (u16)(adr & 0x0f);
//
// OUT a vendor request to ask 8051 do HW three write operation.
//
//printk("before write rtl8225 , data = %x\n",data);
status = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
0x04, RTL8187_REQT_WRITE,
0x0000, 0x1304, &data, 2, HZ / 2);
if (status < 0)
{
printk("write_rtl8225 TimeOut! status:%x\n", status);
}
/*mdelay(1);
u16 Tmpdata;
status = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
0x04, RTL8187_REQT_READ,
0x0000, 0x1304, &Tmpdata, 2, HZ / 2);
if (status < 0)
{
printk("read_rtl8225 TimeOut! status:%x\n", status);
}
printk("after read rtl8225 , data = %x\n",Tmpdata);*/
#else
#ifdef USE_8051_3WIRE
struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
struct usb_device *udev = priv->udev;
//u8 bit;
u16 wReg80, wReg82, wReg84;
wReg80 = read_nic_word(dev, RFPinsOutput);
wReg80 &= 0xfff3;
wReg82 = read_nic_word(dev, RFPinsEnable);
wReg84 = read_nic_word(dev, RFPinsSelect);
// <RJ_NOTE> 3-wire should be controled by HW when we finish SW 3-wire programming. 2005.08.10, by rcnjko.
//wReg84 &= 0xfff0;
wReg84 &= 0xfff8; //modified by david according to windows segment code.
// We must set SW enabled before terminating HW 3-wire, 2005.07.29, by rcnjko.
write_nic_word(dev, RFPinsEnable, (wReg82|0x0007)); // Set To Output Enable
write_nic_word(dev, RFPinsSelect, (wReg84|0x0007)); // Set To SW Switch
force_pci_posting(dev);
udelay(10); //
write_nic_word(dev, 0x80, (BB_HOST_BANG_EN|wReg80)); // Set SI_EN (RFLE)
force_pci_posting(dev);
udelay(2);
//twreg.struc.enableB = 0;
write_nic_word(dev, 0x80, (wReg80)); // Clear SI_EN (RFLE)
force_pci_posting(dev);
udelay(10);
usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
RTL8187_REQ_SET_REGS, RTL8187_REQT_WRITE,
adr, 0x8225, &data, 2, HZ / 2);
write_nic_word(dev, 0x80, (BB_HOST_BANG_EN|wReg80));
force_pci_posting(dev);
udelay(10);
write_nic_word(dev, 0x80, (wReg80|0x0004));
write_nic_word(dev, 0x84, (wReg84|0x0000));// Set To SW Switch
if(priv->card_type == USB)
mdelay(2);
else
rtl8185_rf_pins_enable(dev);
#else
int i;
u16 out,select;
u8 bit;
u32 bangdata = (data << 4) | (adr & 0xf);
struct r8180_priv *priv = ieee80211_priv(dev);
out = read_nic_word(dev, RFPinsOutput) & 0xfff3;
write_nic_word(dev,RFPinsEnable,
(read_nic_word(dev,RFPinsEnable) | 0x7));
select = read_nic_word(dev, RFPinsSelect);
write_nic_word(dev, RFPinsSelect, select | 0x7 |
((priv->card_type == USB) ? 0 : SW_CONTROL_GPIO));
force_pci_posting(dev);
udelay(10);
write_nic_word(dev, RFPinsOutput, out | BB_HOST_BANG_EN );//| 0x1fff);
force_pci_posting(dev);
udelay(2);
write_nic_word(dev, RFPinsOutput, out);
force_pci_posting(dev);
udelay(10);
for(i=15; i>=0;i--){
bit = (bangdata & (1<<i)) >> i;
write_nic_word(dev, RFPinsOutput, bit | out);
write_nic_word(dev, RFPinsOutput, bit | out | BB_HOST_BANG_CLK);
write_nic_word(dev, RFPinsOutput, bit | out | BB_HOST_BANG_CLK);
i--;
bit = (bangdata & (1<<i)) >> i;
write_nic_word(dev, RFPinsOutput, bit | out | BB_HOST_BANG_CLK);
write_nic_word(dev, RFPinsOutput, bit | out | BB_HOST_BANG_CLK);
write_nic_word(dev, RFPinsOutput, bit | out);
}
write_nic_word(dev, RFPinsOutput, out | BB_HOST_BANG_EN);
force_pci_posting(dev);
udelay(10);
write_nic_word(dev, RFPinsOutput, out |
((priv->card_type == USB) ? 4 : BB_HOST_BANG_EN));
write_nic_word(dev, RFPinsSelect, select |
((priv->card_type == USB) ? 0 : SW_CONTROL_GPIO));
if(priv->card_type == USB)
mdelay(2);
else
rtl8185_rf_pins_enable(dev);
#endif
#endif /*THOMAS_3WIRE*/
}
void rtl8225_SetTXPowerLevel(struct net_device *dev, short ch)
{
struct r8180_priv *priv = ieee80211_priv(dev);
int GainIdx;
int GainSetting;
int i;
u8 power;
u8 *cck_power_table;
u8 max_cck_power_level;
u8 max_ofdm_power_level;
u8 min_ofdm_power_level;
u8 cck_power_level = 0xff & priv->chtxpwr[ch];
u8 ofdm_power_level = 0xff & priv->chtxpwr_ofdm[ch];
if(priv->card_type == USB){
max_cck_power_level = 11;
max_ofdm_power_level = 25; // 12 -> 25
min_ofdm_power_level = 10;
}else{
max_cck_power_level = 35;
max_ofdm_power_level = 35;
min_ofdm_power_level = 0;
}
/* CCK power setting */
if(cck_power_level > max_cck_power_level)
cck_power_level = max_cck_power_level;
GainIdx=cck_power_level % 6;
GainSetting=cck_power_level / 6;
if(ch == 14)
cck_power_table = rtl8225_tx_power_cck_ch14;
else
cck_power_table = rtl8225_tx_power_cck;
// if(priv->card_8185 == 1 && priv->card_8185_Bversion ){
/*Ver B*/
// write_nic_byte(dev, TX_GAIN_CCK, rtl8225_tx_gain_cck_ofdm[GainSetting]);
// }else{
/*Ver C - D */
write_nic_byte(dev, TX_GAIN_CCK, rtl8225_tx_gain_cck_ofdm[GainSetting]>>1);
// }
for(i=0;i<8;i++){
power = cck_power_table[GainIdx * 8 + i];
write_phy_cck(dev, 0x44 + i, power);
}
/* FIXME Is this delay really needeed ? */
force_pci_posting(dev);
mdelay(1);
/* OFDM power setting */
// Old:
// if(ofdm_power_level > max_ofdm_power_level)
// ofdm_power_level = 35;
// ofdm_power_level += min_ofdm_power_level;
// Latest:
if(ofdm_power_level > (max_ofdm_power_level - min_ofdm_power_level))
ofdm_power_level = max_ofdm_power_level;
else
ofdm_power_level += min_ofdm_power_level;
if(ofdm_power_level > 35)
ofdm_power_level = 35;
//
GainIdx=ofdm_power_level % 6;
GainSetting=ofdm_power_level / 6;
#if 1
// if(priv->card_type == USB){
rtl8185_set_anaparam2(dev,RTL8225_ANAPARAM2_ON);
write_phy_ofdm(dev,2,0x42);
write_phy_ofdm(dev,6,0);
write_phy_ofdm(dev,8,0);
// }
#endif
// if(priv->card_8185 == 1 && priv->card_8185_Bversion){
// /*Ver B*/
// write_nic_byte(dev, TX_GAIN_OFDM, rtl8225_tx_gain_cck_ofdm[GainSetting]);
// }else{
/*Ver C - D */
write_nic_byte(dev, TX_GAIN_OFDM, rtl8225_tx_gain_cck_ofdm[GainSetting]>>1);
// }
power = rtl8225_tx_power_ofdm[GainIdx];
write_phy_ofdm(dev, 0x5, power);
write_phy_ofdm(dev, 0x7, power);
force_pci_posting(dev);
mdelay(1);
//write_nic_byte(dev, TX_AGC_CONTROL,4);
}
void rtl8225z2_SetTXPowerLevel(struct net_device *dev, short ch)
{
struct r8180_priv *priv = ieee80211_priv(dev);
// int GainIdx;
// int GainSetting;
int i;
u8 power;
u8 *cck_power_table;
u8 max_cck_power_level;
//u8 min_cck_power_level;
u8 max_ofdm_power_level;
u8 min_ofdm_power_level;
u8 cck_power_level = 0xff & priv->chtxpwr[ch];
u8 ofdm_power_level = 0xff & priv->chtxpwr_ofdm[ch];
max_cck_power_level = 15;
//min_cck_power_level = 0;
max_ofdm_power_level = 25; // 12 -> 25
min_ofdm_power_level = 10;
/* CCK power setting */
if(cck_power_level > max_cck_power_level)
cck_power_level = max_cck_power_level;
cck_power_level += priv->cck_txpwr_base;
if(cck_power_level > 35)
cck_power_level = 35;
if(ch == 14)
cck_power_table = rtl8225z2_tx_power_cck_ch14;
else
cck_power_table = rtl8225z2_tx_power_cck;
for(i=0;i<8;i++){
power = cck_power_table[i];
write_phy_cck(dev, 0x44 + i, power);
}
//write_nic_byte(dev, TX_GAIN_CCK, power);
//2005.11.17,
write_nic_byte(dev, TX_GAIN_CCK, ZEBRA2_CCK_OFDM_GAIN_SETTING[cck_power_level]);
force_pci_posting(dev);
mdelay(1);
/* OFDM power setting */
// Old:
// if(ofdm_power_level > max_ofdm_power_level)
// ofdm_power_level = 35;
// ofdm_power_level += min_ofdm_power_level;
// Latest:
if(ofdm_power_level > (max_ofdm_power_level - min_ofdm_power_level))
ofdm_power_level = max_ofdm_power_level;
else
ofdm_power_level += min_ofdm_power_level;
ofdm_power_level += priv->ofdm_txpwr_base;
if(ofdm_power_level > 35)
ofdm_power_level = 35;
rtl8185_set_anaparam2(dev,RTL8225_ANAPARAM2_ON);
write_phy_ofdm(dev,2,0x42);
write_phy_ofdm(dev,5,0);
write_phy_ofdm(dev,6,0x40);
write_phy_ofdm(dev,7,0);
write_phy_ofdm(dev,8,0x40);
//write_nic_byte(dev, TX_GAIN_OFDM, ofdm_power_level);
//2005.11.17,
write_nic_byte(dev, TX_GAIN_OFDM, ZEBRA2_CCK_OFDM_GAIN_SETTING[ofdm_power_level]);
force_pci_posting(dev);
mdelay(1);
//write_nic_byte(dev, TX_AGC_CONTROL,4);
}
void write_rtl8225(struct net_device *dev, u8 adr, u16 data)
{
int i;
u16 out,select;
u8 bit;
u32 bangdata = (data << 4) | (adr & 0xf);
struct r8180_priv *priv = ieee80211_priv(dev);
out = read_nic_word(dev, RFPinsOutput) & 0xfff3;
write_nic_word(dev,RFPinsEnable,
(read_nic_word(dev,RFPinsEnable) | 0x7));
select = read_nic_word(dev, RFPinsSelect);
write_nic_word(dev, RFPinsSelect, select | 0x7 |
((priv->card_type == USB) ? 0 : SW_CONTROL_GPIO));
force_pci_posting(dev);
udelay(10);
write_nic_word(dev, RFPinsOutput, out | BB_HOST_BANG_EN );//| 0x1fff);
force_pci_posting(dev);
udelay(2);
write_nic_word(dev, RFPinsOutput, out);
force_pci_posting(dev);
udelay(10);
for(i=15; i>=0;i--){
bit = (bangdata & (1<<i)) >> i;
write_nic_word(dev, RFPinsOutput, bit | out);
write_nic_word(dev, RFPinsOutput, bit | out | BB_HOST_BANG_CLK);
write_nic_word(dev, RFPinsOutput, bit | out | BB_HOST_BANG_CLK);
i--;
bit = (bangdata & (1<<i)) >> i;
write_nic_word(dev, RFPinsOutput, bit | out | BB_HOST_BANG_CLK);
write_nic_word(dev, RFPinsOutput, bit | out | BB_HOST_BANG_CLK);
write_nic_word(dev, RFPinsOutput, bit | out);
}
write_nic_word(dev, RFPinsOutput, out | BB_HOST_BANG_EN);
force_pci_posting(dev);
udelay(10);
write_nic_word(dev, RFPinsOutput, out |
((priv->card_type == USB) ? 4 : BB_HOST_BANG_EN));
write_nic_word(dev, RFPinsSelect, select |
((priv->card_type == USB) ? 0 : SW_CONTROL_GPIO));
if(priv->card_type == USB)
mdelay(2);
else
rtl8185_rf_pins_enable(dev);
}
void rtl8225z2_rf_init(struct net_device *dev)
{
struct r8180_priv *priv = ieee80211_priv(dev);
int i;
short channel = 1;
u16 brsr;
u32 data,addr;
priv->chan = channel;
rtl8180_set_anaparam(dev, RTL8225_ANAPARAM_ON);
if(priv->card_type == USB)
rtl8225_host_usb_init(dev);
else
rtl8225_host_pci_init(dev);
write_nic_dword(dev, RF_TIMING, 0x000a8008);
brsr = read_nic_word(dev, BRSR);
write_nic_word(dev, BRSR, 0xffff);
write_nic_dword(dev, RF_PARA, 0x100044);
#if 1 //0->1
rtl8180_set_mode(dev, EPROM_CMD_CONFIG);
write_nic_byte(dev, CONFIG3, 0x44);
rtl8180_set_mode(dev, EPROM_CMD_NORMAL);
#endif
rtl8185_rf_pins_enable(dev);
// mdelay(1000);
write_rtl8225(dev, 0x0, 0x2bf); mdelay(1);
write_rtl8225(dev, 0x1, 0xee0); mdelay(1);
write_rtl8225(dev, 0x2, 0x44d); mdelay(1);
write_rtl8225(dev, 0x3, 0x441); mdelay(1);
write_rtl8225(dev, 0x4, 0x8c3);mdelay(1);
write_rtl8225(dev, 0x5, 0xc72);mdelay(1);
// }
write_rtl8225(dev, 0x6, 0xe6); mdelay(1);
write_rtl8225(dev, 0x7, ((priv->card_type == USB)? 0x82a : rtl8225_chan[channel])); mdelay(1);
write_rtl8225(dev, 0x8, 0x3f); mdelay(1);
write_rtl8225(dev, 0x9, 0x335); mdelay(1);
write_rtl8225(dev, 0xa, 0x9d4); mdelay(1);
write_rtl8225(dev, 0xb, 0x7bb); mdelay(1);
write_rtl8225(dev, 0xc, 0x850); mdelay(1);
write_rtl8225(dev, 0xd, 0xcdf); mdelay(1);
write_rtl8225(dev, 0xe, 0x2b); mdelay(1);
write_rtl8225(dev, 0xf, 0x114);
mdelay(100);
//if(priv->card_type != USB) /* maybe not needed even for 8185 */
// write_rtl8225(dev, 0x7, rtl8225_chan[channel]);
write_rtl8225(dev, 0x0, 0x1b7);
for(i=0;i<95;i++){
write_rtl8225(dev, 0x1, (u8)(i+1));
#if 0
if(priv->phy_ver == 1)
/* version A */
write_rtl8225(dev, 0x2, rtl8225a_rxgain[i]);
else
#endif
/* version B & C & D*/
write_rtl8225(dev, 0x2, rtl8225z2_rxgain[i]);
}
write_rtl8225(dev, 0x3, 0x80);
write_rtl8225(dev, 0x5, 0x4);
write_rtl8225(dev, 0x0, 0xb7);
write_rtl8225(dev, 0x2, 0xc4d);
if(priv->card_type == USB){
// force_pci_posting(dev);
mdelay(200);
write_rtl8225(dev, 0x2, 0x44d);
// force_pci_posting(dev);
mdelay(100);
}//End of if(priv->card_type == USB)
/* FIXME!! rtl8187 we have to check if calibrarion
* is successful and eventually cal. again (repeat
* the two write on reg 2)
*/
// Check for calibration status, 2005.11.17,
data = read_rtl8225(dev, 6);
if (!(data&0x00000080))
{
write_rtl8225(dev, 0x02, 0x0c4d);
force_pci_posting(dev); mdelay(200);
write_rtl8225(dev, 0x02, 0x044d);
force_pci_posting(dev); mdelay(100);
data = read_rtl8225(dev, 6);
if (!(data&0x00000080))
{
DMESGW("RF Calibration Failed!!!!\n");
}
}
//force_pci_posting(dev);
mdelay(200); //200 for 8187
// //if(priv->card_type != USB){
// write_rtl8225(dev, 0x2, 0x44d);
// write_rtl8225(dev, 0x7, rtl8225_chan[channel]);
// write_rtl8225(dev, 0x2, 0x47d);
//
// force_pci_posting(dev);
// mdelay(100);
//
// write_rtl8225(dev, 0x2, 0x44d);
// //}
write_rtl8225(dev, 0x0, 0x2bf);
if(priv->card_type != USB)
rtl8185_rf_pins_enable(dev);
//set up ZEBRA AGC table, 2005.11.17,
for(i=0;i<128;i++){
data = rtl8225_agc[i];
addr = i + 0x80; //enable writing AGC table
write_phy_ofdm(dev, 0xb, data);
mdelay(1);
write_phy_ofdm(dev, 0xa, addr);
mdelay(1);
}
#if 0
for(i=0;i<128;i++){
write_phy_ofdm(dev, 0xb, rtl8225_agc[i]);
mdelay(1);
write_phy_ofdm(dev, 0xa, (u8)i+ 0x80);
mdelay(1);
}
#endif
force_pci_posting(dev);
mdelay(1);
write_phy_ofdm(dev, 0x0, 0x1); mdelay(1);
write_phy_ofdm(dev, 0x1, 0x2); mdelay(1);
write_phy_ofdm(dev, 0x2, ((priv->card_type == USB)? 0x42 : 0x62)); mdelay(1);
write_phy_ofdm(dev, 0x3, 0x0); mdelay(1);
write_phy_ofdm(dev, 0x4, 0x0); mdelay(1);
write_phy_ofdm(dev, 0x5, 0x0); mdelay(1);
write_phy_ofdm(dev, 0x6, 0x40); mdelay(1);
write_phy_ofdm(dev, 0x7, 0x0); mdelay(1);
write_phy_ofdm(dev, 0x8, 0x40); mdelay(1);
write_phy_ofdm(dev, 0x9, 0xfe); mdelay(1);
write_phy_ofdm(dev, 0xa, 0x8); mdelay(1);
//write_phy_ofdm(dev, 0x18, 0xef);
// }
//}
write_phy_ofdm(dev, 0xb, 0x80); mdelay(1);
write_phy_ofdm(dev, 0xc, 0x1);mdelay(1);
//if(priv->card_type != USB)
write_phy_ofdm(dev, 0xd, 0x43);
write_phy_ofdm(dev, 0xe, 0xd3);mdelay(1);
#if 0
if(priv->card_8185 == 1){
if(priv->card_8185_Bversion)
write_phy_ofdm(dev, 0xf, 0x20);/*ver B*/
else
write_phy_ofdm(dev, 0xf, 0x28);/*ver C*/
}else{
#endif
write_phy_ofdm(dev, 0xf, 0x38);mdelay(1);
/*ver D & 8187*/
// }
// if(priv->card_8185 == 1 && priv->card_8185_Bversion)
// write_phy_ofdm(dev, 0x10, 0x04);/*ver B*/
// else
write_phy_ofdm(dev, 0x10, 0x84);mdelay(1);
/*ver C & D & 8187*/
write_phy_ofdm(dev, 0x11, 0x07);mdelay(1);
/*agc resp time 700*/
// if(priv->card_8185 == 2){
/* Ver D & 8187*/
write_phy_ofdm(dev, 0x12, 0x20);mdelay(1);
write_phy_ofdm(dev, 0x13, 0x20);mdelay(1);
#if 0
}else{
static void rtl8225_SetTXPowerLevel(struct net_device *dev, short ch)
{
struct r8180_priv *priv = ieee80211_priv(dev);
int GainIdx;
int GainSetting;
int i;
u8 power;
const u8 *cck_power_table;
u8 max_cck_power_level;
u8 max_ofdm_power_level;
u8 min_ofdm_power_level;
u8 cck_power_level = 0xff & priv->chtxpwr[ch];
u8 ofdm_power_level = 0xff & priv->chtxpwr_ofdm[ch];
max_cck_power_level = 35;
max_ofdm_power_level = 35;
min_ofdm_power_level = 0;
if (cck_power_level > max_cck_power_level)
cck_power_level = max_cck_power_level;
GainIdx = cck_power_level % 6;
GainSetting = cck_power_level / 6;
if (ch == 14)
cck_power_table = rtl8225_tx_power_cck_ch14;
else
cck_power_table = rtl8225_tx_power_cck;
write_nic_byte(dev, TX_GAIN_CCK,
rtl8225_tx_gain_cck_ofdm[GainSetting] >> 1);
for (i = 0; i < 8; i++) {
power = cck_power_table[GainIdx * 8 + i];
write_phy_cck(dev, 0x44 + i, power);
}
/* FIXME Is this delay really needeed ? */
force_pci_posting(dev);
mdelay(1);
if (ofdm_power_level > (max_ofdm_power_level - min_ofdm_power_level))
ofdm_power_level = max_ofdm_power_level;
else
ofdm_power_level += min_ofdm_power_level;
if (ofdm_power_level > 35)
ofdm_power_level = 35;
GainIdx = ofdm_power_level % 6;
GainSetting = ofdm_power_level / 6;
rtl8185_set_anaparam2(dev, RTL8225_ANAPARAM2_ON);
write_phy_ofdm(dev, 2, 0x42);
write_phy_ofdm(dev, 6, 0x00);
write_phy_ofdm(dev, 8, 0x00);
write_nic_byte(dev, TX_GAIN_OFDM,
rtl8225_tx_gain_cck_ofdm[GainSetting] >> 1);
power = rtl8225_tx_power_ofdm[GainIdx];
write_phy_ofdm(dev, 5, power);
write_phy_ofdm(dev, 7, power);
force_pci_posting(dev);
mdelay(1);
}
void rtl8225z2_SetTXPowerLevel(struct net_device *dev, short ch)
{
struct r8180_priv *priv = ieee80211_priv(dev);
u8 max_cck_power_level;
u8 max_ofdm_power_level;
u8 min_ofdm_power_level;
char cck_power_level = (char)(0xff & priv->chtxpwr[ch]);
char ofdm_power_level = (char)(0xff & priv->chtxpwr_ofdm[ch]);
if (IS_DOT11D_ENABLE(priv->ieee80211) &&
IS_DOT11D_STATE_DONE(priv->ieee80211)) {
u8 MaxTxPwrInDbm = DOT11D_GetMaxTxPwrInDbm(priv->ieee80211, ch);
u8 CckMaxPwrIdx = DbmToTxPwrIdx(priv, WIRELESS_MODE_B,
MaxTxPwrInDbm);
u8 OfdmMaxPwrIdx = DbmToTxPwrIdx(priv, WIRELESS_MODE_G,
MaxTxPwrInDbm);
if (cck_power_level > CckMaxPwrIdx)
cck_power_level = CckMaxPwrIdx;
if (ofdm_power_level > OfdmMaxPwrIdx)
ofdm_power_level = OfdmMaxPwrIdx;
}
max_cck_power_level = 15;
max_ofdm_power_level = 25;
min_ofdm_power_level = 10;
if (cck_power_level > 35)
cck_power_level = 35;
write_nic_byte(dev, CCK_TXAGC,
(ZEBRA2_CCK_OFDM_GAIN_SETTING[(u8)cck_power_level]));
force_pci_posting(dev);
mdelay(1);
if (ofdm_power_level > 35)
ofdm_power_level = 35;
if (priv->up == 0) {
write_phy_ofdm(dev, 2, 0x42);
write_phy_ofdm(dev, 5, 0x00);
write_phy_ofdm(dev, 6, 0x40);
write_phy_ofdm(dev, 7, 0x00);
write_phy_ofdm(dev, 8, 0x40);
}
write_nic_byte(dev, OFDM_TXAGC,
ZEBRA2_CCK_OFDM_GAIN_SETTING[(u8)ofdm_power_level]);
if (ofdm_power_level <= 11) {
write_phy_ofdm(dev, 0x07, 0x5c);
write_phy_ofdm(dev, 0x09, 0x5c);
}
if (ofdm_power_level <= 17) {
write_phy_ofdm(dev, 0x07, 0x54);
write_phy_ofdm(dev, 0x09, 0x54);
} else {
write_phy_ofdm(dev, 0x07, 0x50);
write_phy_ofdm(dev, 0x09, 0x50);
}
force_pci_posting(dev);
mdelay(1);
}
void rtl8225z2_rf_init(struct net_device *dev)
{
struct r8180_priv *priv = ieee80211_priv(dev);
int i;
short channel = 1;
u16 brsr;
u32 data, addr;
priv->chan = channel;
rtl8225_host_pci_init(dev);
write_nic_dword(dev, RF_TIMING, 0x000a8008);
brsr = read_nic_word(dev, BRSR);
write_nic_word(dev, BRSR, 0xffff);
write_nic_dword(dev, RF_PARA, 0x100044);
rtl8180_set_mode(dev, EPROM_CMD_CONFIG);
write_nic_byte(dev, CONFIG3, 0x44);
rtl8180_set_mode(dev, EPROM_CMD_NORMAL);
rtl8185_rf_pins_enable(dev);
write_rtl8225(dev, 0x0, 0x2bf); mdelay(1);
write_rtl8225(dev, 0x1, 0xee0); mdelay(1);
write_rtl8225(dev, 0x2, 0x44d); mdelay(1);
write_rtl8225(dev, 0x3, 0x441); mdelay(1);
write_rtl8225(dev, 0x4, 0x8c3); mdelay(1);
write_rtl8225(dev, 0x5, 0xc72); mdelay(1);
write_rtl8225(dev, 0x6, 0xe6); mdelay(1);
write_rtl8225(dev, 0x7, rtl8225_chan[channel]); mdelay(1);
write_rtl8225(dev, 0x8, 0x3f); mdelay(1);
write_rtl8225(dev, 0x9, 0x335); mdelay(1);
write_rtl8225(dev, 0xa, 0x9d4); mdelay(1);
write_rtl8225(dev, 0xb, 0x7bb); mdelay(1);
write_rtl8225(dev, 0xc, 0x850); mdelay(1);
write_rtl8225(dev, 0xd, 0xcdf); mdelay(1);
write_rtl8225(dev, 0xe, 0x2b); mdelay(1);
write_rtl8225(dev, 0xf, 0x114);
mdelay(100);
write_rtl8225(dev, 0x0, 0x1b7);
for (i = 0; i < 95; i++) {
write_rtl8225(dev, 0x1, (u8)(i + 1));
write_rtl8225(dev, 0x2, rtl8225z2_rxgain[i]);
}
write_rtl8225(dev, 0x3, 0x80);
write_rtl8225(dev, 0x5, 0x4);
write_rtl8225(dev, 0x0, 0xb7);
write_rtl8225(dev, 0x2, 0xc4d);
/* FIXME!! rtl8187 we have to check if calibrarion
* is successful and eventually cal. again (repeat
* the two write on reg 2)
*/
data = read_rtl8225(dev, 6);
if (!(data & 0x00000080)) {
write_rtl8225(dev, 0x02, 0x0c4d);
force_pci_posting(dev); mdelay(200);
write_rtl8225(dev, 0x02, 0x044d);
force_pci_posting(dev); mdelay(100);
data = read_rtl8225(dev, 6);
if (!(data & 0x00000080))
DMESGW("RF Calibration Failed!!!!\n");
}
mdelay(200);
write_rtl8225(dev, 0x0, 0x2bf);
for (i = 0; i < 128; i++) {
data = rtl8225_agc[i];
addr = i + 0x80; /* enable writing AGC table */
write_phy_ofdm(dev, 0xb, data);
mdelay(1);
write_phy_ofdm(dev, 0xa, addr);
mdelay(1);
}
force_pci_posting(dev);
mdelay(1);
write_phy_ofdm(dev, 0x00, 0x01); mdelay(1);
write_phy_ofdm(dev, 0x01, 0x02); mdelay(1);
write_phy_ofdm(dev, 0x02, 0x62); mdelay(1);
write_phy_ofdm(dev, 0x03, 0x00); mdelay(1);
write_phy_ofdm(dev, 0x04, 0x00); mdelay(1);
write_phy_ofdm(dev, 0x05, 0x00); mdelay(1);
write_phy_ofdm(dev, 0x06, 0x40); mdelay(1);
write_phy_ofdm(dev, 0x07, 0x00); mdelay(1);
write_phy_ofdm(dev, 0x08, 0x40); mdelay(1);
write_phy_ofdm(dev, 0x09, 0xfe); mdelay(1);
write_phy_ofdm(dev, 0x0a, 0x08); mdelay(1);
write_phy_ofdm(dev, 0x0b, 0x80); mdelay(1);
write_phy_ofdm(dev, 0x0c, 0x01); mdelay(1);
write_phy_ofdm(dev, 0x0d, 0x43);
write_phy_ofdm(dev, 0x0e, 0xd3); mdelay(1);
write_phy_ofdm(dev, 0x0f, 0x38); mdelay(1);
write_phy_ofdm(dev, 0x10, 0x84); mdelay(1);
write_phy_ofdm(dev, 0x11, 0x07); mdelay(1);
write_phy_ofdm(dev, 0x12, 0x20); mdelay(1);
write_phy_ofdm(dev, 0x13, 0x20); mdelay(1);
write_phy_ofdm(dev, 0x14, 0x00); mdelay(1);
write_phy_ofdm(dev, 0x15, 0x40); mdelay(1);
write_phy_ofdm(dev, 0x16, 0x00); mdelay(1);
write_phy_ofdm(dev, 0x17, 0x40); mdelay(1);
write_phy_ofdm(dev, 0x18, 0xef); mdelay(1);
write_phy_ofdm(dev, 0x19, 0x19); mdelay(1);
write_phy_ofdm(dev, 0x1a, 0x20); mdelay(1);
write_phy_ofdm(dev, 0x1b, 0x15); mdelay(1);
write_phy_ofdm(dev, 0x1c, 0x04); mdelay(1);
write_phy_ofdm(dev, 0x1d, 0xc5); mdelay(1);
write_phy_ofdm(dev, 0x1e, 0x95); mdelay(1);
write_phy_ofdm(dev, 0x1f, 0x75); mdelay(1);
write_phy_ofdm(dev, 0x20, 0x1f); mdelay(1);
write_phy_ofdm(dev, 0x21, 0x17); mdelay(1);
write_phy_ofdm(dev, 0x22, 0x16); mdelay(1);
write_phy_ofdm(dev, 0x23, 0x80); mdelay(1); /* FIXME maybe not needed */
write_phy_ofdm(dev, 0x24, 0x46); mdelay(1);
write_phy_ofdm(dev, 0x25, 0x00); mdelay(1);
write_phy_ofdm(dev, 0x26, 0x90); mdelay(1);
write_phy_ofdm(dev, 0x27, 0x88); mdelay(1);
rtl8225z2_set_gain(dev, 4);
write_phy_cck(dev, 0x0, 0x98); mdelay(1);
write_phy_cck(dev, 0x3, 0x20); mdelay(1);
write_phy_cck(dev, 0x4, 0x7e); mdelay(1);
write_phy_cck(dev, 0x5, 0x12); mdelay(1);
write_phy_cck(dev, 0x6, 0xfc); mdelay(1);
write_phy_cck(dev, 0x7, 0x78); mdelay(1);
write_phy_cck(dev, 0x8, 0x2e); mdelay(1);
write_phy_cck(dev, 0x10, 0x93); mdelay(1);
write_phy_cck(dev, 0x11, 0x88); mdelay(1);
write_phy_cck(dev, 0x12, 0x47); mdelay(1);
write_phy_cck(dev, 0x13, 0xd0);
write_phy_cck(dev, 0x19, 0x00);
write_phy_cck(dev, 0x1a, 0xa0);
write_phy_cck(dev, 0x1b, 0x08);
write_phy_cck(dev, 0x40, 0x86); /* CCK Carrier Sense Threshold */
write_phy_cck(dev, 0x41, 0x8d); mdelay(1);
write_phy_cck(dev, 0x42, 0x15); mdelay(1);
write_phy_cck(dev, 0x43, 0x18); mdelay(1);
write_phy_cck(dev, 0x44, 0x36); mdelay(1);
write_phy_cck(dev, 0x45, 0x35); mdelay(1);
write_phy_cck(dev, 0x46, 0x2e); mdelay(1);
write_phy_cck(dev, 0x47, 0x25); mdelay(1);
write_phy_cck(dev, 0x48, 0x1c); mdelay(1);
write_phy_cck(dev, 0x49, 0x12); mdelay(1);
write_phy_cck(dev, 0x4a, 0x09); mdelay(1);
write_phy_cck(dev, 0x4b, 0x04); mdelay(1);
write_phy_cck(dev, 0x4c, 0x05); mdelay(1);
write_nic_byte(dev, 0x5b, 0x0d); mdelay(1);
rtl8225z2_SetTXPowerLevel(dev, channel);
/* RX antenna default to A */
write_phy_cck(dev, 0x11, 0x9b); mdelay(1); /* B: 0xDB */
write_phy_ofdm(dev, 0x26, 0x90); mdelay(1); /* B: 0x10 */
rtl8185_tx_antenna(dev, 0x03); /* B: 0x00 */
/* switch to high-speed 3-wire
* last digit. 2 for both cck and ofdm
*/
write_nic_dword(dev, 0x94, 0x15c00002);
rtl8185_rf_pins_enable(dev);
rtl8225_rf_set_chan(dev, priv->chan);
}