static int stop_pmu(void)
{
u32 intenc_value;
u32 flag_value;
u32 pmnc_value;
intenc_value = 0xffffffff;
flag_value = 0xffffffff;
/* disable all counters */
pmnc_value = PJ4_Read_PMNC();
pmnc_value &= ~0x1;
PJ4_Write_PMNC(pmnc_value);
/* clear overflow flags */
PJ4_Write_FLAG(flag_value);
/* disable all interrupts */
PJ4_Write_INTENC(intenc_value);
/* We need to save the PMU counter value for calibration result before calling free_pmu()
* because free_pmu() may cause these registers be modified by IPM */
reg_value[COUNTER_PJ4_PMU_CCNT] = PJ4_ReadPMUCounter(COUNTER_PJ4_PMU_CCNT);
reg_value[COUNTER_PJ4_PMU_PMN0] = PJ4_ReadPMUCounter(COUNTER_PJ4_PMU_PMN0);
reg_value[COUNTER_PJ4_PMU_PMN1] = PJ4_ReadPMUCounter(COUNTER_PJ4_PMU_PMN1);
reg_value[COUNTER_PJ4_PMU_PMN2] = PJ4_ReadPMUCounter(COUNTER_PJ4_PMU_PMN2);
reg_value[COUNTER_PJ4_PMU_PMN3] = PJ4_ReadPMUCounter(COUNTER_PJ4_PMU_PMN3);
unregister_pmu_isr();
free_pmu();
return 0;
}
static int stop_ebs(void)
{
int ret = 0;
if (is_pmu_enabled())
{
on_each_cpu(stop_pmu, NULL, 1);
ret = unregister_pmu_isr();
if (ret != 0)
{
return ret;
}
ret = free_pmu();
if (ret != 0)
{
return ret;
}
unregister_hotcpu_notifier(&cpu_notifier_for_pmu);
}
return 0;
}
static int stop_pmu(void)
{
unsigned int inten_value;
unsigned int pmnc_value;
unsigned int flag_value;
inten_value = 0x0;
flag_value = 0x1f;
pmnc_value = ReadPMUReg(PXA2_PMU_PMNC);
/* disable the counters */
pmnc_value |= 0x10;
pmnc_value &= ~0x1;
WritePMUReg(PXA2_PMU_PMNC, pmnc_value);
WritePMUReg(PXA2_PMU_INTEN, inten_value);
WritePMUReg(PXA2_PMU_FLAG, flag_value);
/* We need to save the PMU counter value for calibration result before calling free_pmu()
* because free_pmu() may cause these registers be modified by IPM */
reg_value[COUNTER_PXA2_PMU_CCNT] = ReadPMUReg(PXA2_PMU_CCNT);
reg_value[COUNTER_PXA2_PMU_PMN0] = ReadPMUReg(PXA2_PMU_PMN0);
reg_value[COUNTER_PXA2_PMU_PMN1] = ReadPMUReg(PXA2_PMU_PMN1);
reg_value[COUNTER_PXA2_PMU_PMN2] = ReadPMUReg(PXA2_PMU_PMN2);
reg_value[COUNTER_PXA2_PMU_PMN3] = ReadPMUReg(PXA2_PMU_PMN3);
unregister_pmu_isr();
free_pmu();
return 0;
}
static int stop_pmu(void)
{
int i;
u32 cor_value[PJ1_PMN_NUM];
u32 inten_value;
u32 flag_value;
inten_value = 0x0;
flag_value = 0xf;
/* disable all counters */
cor_value[0] = PJ1_ReadCOR(PJ1_PMU_COR0);
cor_value[1] = PJ1_ReadCOR(PJ1_PMU_COR1);
cor_value[2] = PJ1_ReadCOR(PJ1_PMU_COR2);
cor_value[3] = PJ1_ReadCOR(PJ1_PMU_COR3);
for (i=0; i<PJ1_PMN_NUM; i++)
{
cor_value[i] &= ~0x1;
}
PJ1_WriteCOR(PJ1_PMU_COR0, cor_value[0]);
PJ1_WriteCOR(PJ1_PMU_COR1, cor_value[1]);
PJ1_WriteCOR(PJ1_PMU_COR2, cor_value[2]);
PJ1_WriteCOR(PJ1_PMU_COR3, cor_value[3]);
/* clear overflow flags */
PJ1_WriteFLAG(flag_value);
/* disable all interrupts */
PJ1_WriteINTEN(inten_value);
/* We need to save the PMU counter value for calibration result before calling free_pmu()
* because free_pmu() may cause these registers be modified by IPM */
reg_value[COUNTER_PJ1_PMU_PMN0] = PJ1_ReadCounter(PJ1_PMU_PMN0);
reg_value[COUNTER_PJ1_PMU_PMN1] = PJ1_ReadCounter(PJ1_PMU_PMN1);
reg_value[COUNTER_PJ1_PMU_PMN2] = PJ1_ReadCounter(PJ1_PMU_PMN2);
reg_value[COUNTER_PJ1_PMU_PMN3] = PJ1_ReadCounter(PJ1_PMU_PMN3);
/* There is no PMU interrupt in Avanta */
#if !defined(PX_SOC_AVANTA)
unregister_pmu_isr();
#endif
free_pmu();
return 0;
}
/*
* Allocate PMU resources and hook the PMU ISR
*/
int allocate_pmu(void)
{
#ifdef PX_CPU_PJ1
return 0;
#else
#ifdef PRM_SUPPORT
int ret;
int i;
ret = prm_open_session(PRI_VTUNE, prm_client_name, NULL, NULL);
if (ret < 0)
{
printk(KERN_ERR "failed to open prm open session\n");
return ret;
}
prm_client_id = ret;
for (i=0; i<PRM_ALLOC_RES_COUNT; i++)
{
ret = prm_allocate_resource(prm_client_id, prm_resource[i], 0);
if (ret != 0)
{
printk(KERN_ERR "failed to allocate prm resource %d\n",
prm_resource[i]);
printk(KERN_ERR "ret = %d\n", ret);
goto alloc_pmu_err;
}
}
/* if ((ret = pmu_register_isr(prm_client_id, cm_pmu_isr, 0)) != 0)
{
printk(KERN_ERR "failed to register ISR\n");
goto alloc_pmu_err;
}
*/
if ((ret = prm_commit_resources(prm_client_id, 0)) != 0)
{
printk(KERN_ERR "failed to commit prm resource\n");
goto alloc_pmu_err;
}
return 0;
alloc_pmu_err:
free_pmu();
return ret;
#else // PRM_SUPPORT
#if 0
if ((ret = request_irq(g_pmu_irq_num/*IRQ_PMU*/, cm_pmu_isr,
#if defined(LINUX_VERSION_CODE) && (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 21))
IRQF_DISABLED
#else
SA_INTERRUPT
#endif
, "CPA PMU", dev_id)) != 0)
{
printk(KERN_ERR "request_irq fails: ret = %d", ret);
return -EACCES;
}
#endif
return 0;
#endif // PRM_SUPPORT
#endif // PX_CPU_PJ1
}
