spi_status_t spi_setupChipReg(volatile avr32_spi_t *spi,
const spi_options_t *options,
uint32_t pb_hz)
{
u_avr32_spi_csr_t u_avr32_spi_csr;
if (options->spi_mode > 3 ||
options->stay_act > 1 ||
options->bits < 8 || options->bits > 16) {
return SPI_ERROR_ARGUMENT;
}
int baudDiv = getBaudDiv(options->baudrate, pb_hz);
if (baudDiv < 0) {
return SPI_ERROR_ARGUMENT;
}
// Will use CSR0 offsets; these are the same for CSR0 to CSR3.
u_avr32_spi_csr.csr = 0;
u_avr32_spi_csr.CSR.cpol = options->spi_mode >> 1;
u_avr32_spi_csr.CSR.ncpha = (options->spi_mode & 0x1) ^ 0x1;
u_avr32_spi_csr.CSR.csaat = options->stay_act;
u_avr32_spi_csr.CSR.bits = options->bits - 8;
u_avr32_spi_csr.CSR.scbr = baudDiv;
u_avr32_spi_csr.CSR.dlybs = options->spck_delay;
u_avr32_spi_csr.CSR.dlybct = options->trans_delay;
switch(options->reg) {
case 0:
spi->csr0 = u_avr32_spi_csr.csr;
break;
case 1:
spi->csr1 = u_avr32_spi_csr.csr;
break;
case 2:
spi->csr2 = u_avr32_spi_csr.csr;
break;
case 3:
spi->csr3 = u_avr32_spi_csr.csr;
break;
default:
return SPI_ERROR_ARGUMENT;
}
#ifdef FREERTOS_USED
if (!xSPIMutex)
{
// Create the SPI mutex.
vSemaphoreCreateBinary(xSPIMutex);
if (!xSPIMutex)
{
while(1);
}
}
#endif
return SPI_OK;
}
void spi_master_setup_device(volatile avr32_spi_t *spi,
struct spi_device *device, spi_flags_t flags, uint32_t baud_rate,
board_spi_select_id_t sel_id)
{
spi_set_chipselect_delay_bct(spi,device->id,CONFIG_SPI_MASTER_DELAY_BCT);
spi_set_chipselect_delay_bs(spi,device->id,CONFIG_SPI_MASTER_DELAY_BS);
spi_set_bits_per_transfer(spi,device->id,
CONFIG_SPI_MASTER_BITS_PER_TRANSFER);
spi_set_baudrate_register(spi,device->id,
getBaudDiv(baud_rate, sysclk_get_peripheral_bus_hz(spi)));
spi_enable_active_mode(spi,device->id);
spi_set_mode(spi,device->id,flags);
#ifdef FREERTOS_USED
if (!xSPIMutex) {
// Create the SPI mutex.
vSemaphoreCreateBinary(xSPIMutex);
if (!xSPIMutex) {
while(1);
}
}
#endif
}
