int ddk750_initHw(initchip_param_t * pInitParam)
{
unsigned int ulReg;
#if 0
//move the code to map regiter function.
if(getChipType() == SM718){
/* turn on big endian bit*/
ulReg = PEEK32(0x74);
/* now consider register definition in a big endian pattern*/
POKE32(0x74,ulReg|0x80000000);
}
#endif
if (pInitParam->powerMode != 0 )
pInitParam->powerMode = 0;
setPowerMode(pInitParam->powerMode);
/* Enable display power gate & LOCALMEM power gate*/
ulReg = PEEK32(CURRENT_GATE);
ulReg = FIELD_SET(ulReg, CURRENT_GATE, DISPLAY, ON);
ulReg = FIELD_SET(ulReg,CURRENT_GATE,LOCALMEM,ON);
setCurrentGate(ulReg);
if(getChipType() != SM750LE){
/* set panel pll and graphic mode via mmio_88 */
ulReg = PEEK32(VGA_CONFIGURATION);
ulReg = FIELD_SET(ulReg,VGA_CONFIGURATION,PLL,PANEL);
ulReg = FIELD_SET(ulReg,VGA_CONFIGURATION,MODE,GRAPHIC);
POKE32(VGA_CONFIGURATION,ulReg);
}else{
#if defined(__i386__) || defined( __x86_64__)
/* set graphic mode via IO method */
outb_p(0x88,0x3d4);
outb_p(0x06,0x3d5);
#endif
}
/* Set the Main Chip Clock */
setChipClock(MHz((unsigned int)pInitParam->chipClock));
/* Set up memory clock. */
setMemoryClock(MHz(pInitParam->memClock));
/* Set up master clock */
setMasterClock(MHz(pInitParam->masterClock));
/* Reset the memory controller. If the memory controller is not reset in SM750,
the system might hang when sw accesses the memory.
The memory should be resetted after changing the MXCLK.
*/
if (pInitParam->resetMemory == 1)
{
ulReg = PEEK32(MISC_CTRL);
ulReg = FIELD_SET(ulReg, MISC_CTRL, LOCALMEM_RESET, RESET);
POKE32(MISC_CTRL, ulReg);
ulReg = FIELD_SET(ulReg, MISC_CTRL, LOCALMEM_RESET, NORMAL);
POKE32(MISC_CTRL, ulReg);
}
if (pInitParam->setAllEngOff == 1)
{
enable2DEngine(0);
/* Disable Overlay, if a former application left it on */
ulReg = PEEK32(VIDEO_DISPLAY_CTRL);
ulReg = FIELD_SET(ulReg, VIDEO_DISPLAY_CTRL, PLANE, DISABLE);
POKE32(VIDEO_DISPLAY_CTRL, ulReg);
/* Disable video alpha, if a former application left it on */
ulReg = PEEK32(VIDEO_ALPHA_DISPLAY_CTRL);
ulReg = FIELD_SET(ulReg, VIDEO_ALPHA_DISPLAY_CTRL, PLANE, DISABLE);
POKE32(VIDEO_ALPHA_DISPLAY_CTRL, ulReg);
/* Disable alpha plane, if a former application left it on */
ulReg = PEEK32(ALPHA_DISPLAY_CTRL);
ulReg = FIELD_SET(ulReg, ALPHA_DISPLAY_CTRL, PLANE, DISABLE);
POKE32(ALPHA_DISPLAY_CTRL, ulReg);
#if 0
/* Disable LCD hardware cursor, if a former application left it on */
ulReg = PEEK32(PANEL_HWC_ADDRESS);
ulReg = FIELD_SET(ulReg, PANEL_HWC_ADDRESS, ENABLE, DISABLE);
POKE32(PANEL_HWC_ADDRESS, ulReg);
/* Disable CRT hardware cursor, if a former application left it on */
ulReg = PEEK32(CRT_HWC_ADDRESS);
ulReg = FIELD_SET(ulReg, CRT_HWC_ADDRESS, ENABLE, DISABLE);
POKE32(CRT_HWC_ADDRESS, ulReg);
/* Disable ZV Port 0, if a former application left it on */
ulReg = PEEK32(ZV0_CAPTURE_CTRL);
ulReg = FIELD_SET(ulReg, ZV0_CAPTURE_CTRL, CAP, DISABLE);
POKE32(ZV0_CAPTURE_CTRL, ulReg);
/* Disable ZV Port 1, if a former application left it on */
ulReg = PEEK32(ZV1_CAPTURE_CTRL);
ulReg = FIELD_SET(ulReg, ZV1_CAPTURE_CTRL, CAP, DISABLE);
POKE32(ZV1_CAPTURE_CTRL, ulReg);
/* Disable ZV Port Power, if a former application left it on */
enableZVPort(0);
/* Disable DMA Channel, if a former application left it on */
ulReg = PEEK32(DMA_ABORT_INTERRUPT);
ulReg = FIELD_SET(ulReg, DMA_ABORT_INTERRUPT, ABORT_1, ABORT);
POKE32(DMA_ABORT_INTERRUPT, ulReg);
/* Disable i2c */
enableI2C(0);
#endif
/* Disable DMA Channel, if a former application left it on */
ulReg = PEEK32(DMA_ABORT_INTERRUPT);
ulReg = FIELD_SET(ulReg, DMA_ABORT_INTERRUPT, ABORT_1, ABORT);
POKE32(DMA_ABORT_INTERRUPT, ulReg);
/* Disable DMA Power, if a former application left it on */
enableDMA(0);
}
/* We can add more initialization as needed. */
return 0;
}
/*
monk liu @ 4/6/2011:
re-write the calculatePLL function of ddk750.
the original version function does not use some mathematics tricks and shortcut
when it doing the calculation of the best N,M,D combination
I think this version gives a little upgrade in speed
750 pll clock formular:
Request Clock = (Input Clock * M )/(N * X)
Input Clock = 14318181 hz
X = 2 power D
D ={0,1,2,3,4,5,6}
M = {1,...,255}
N = {2,...,15}
*/
unsigned int calcPllValue(unsigned int request_orig,pll_value_t *pll)
{
/* used for primary and secondary channel pixel clock pll */
static pllcalparam xparm_PIXEL[] = {
/* 2^0 = 1*/ {0,0,0,1},
/* 2^ 1 =2*/ {1,0,1,2},
/* 2^ 2 = 4*/ {2,0,2,4},
{3,0,3,8},
{4,1,3,16},
{5,2,3,32},
/* 2^6 = 64 */ {6,3,3,64},
};
/* used for MXCLK (chip clock) */
static pllcalparam xparm_MXCLK[] = {
/* 2^0 = 1*/ {0,0,0,1},
/* 2^ 1 =2*/ {1,0,1,2},
/* 2^ 2 = 4*/ {2,0,2,4},
{3,0,3,8},
};
/* as sm750 register definition, N located in 2,15 and M located in 1,255 */
int N,M,X,d;
int xcnt;
int miniDiff;
unsigned int RN,quo,rem,fl_quo;
unsigned int input,request;
unsigned int tmpClock,ret;
pllcalparam * xparm;
#if 1
if (getChipType() == SM750LE)
{
/* SM750LE don't have prgrammable PLL and M/N values to work on.
Just return the requested clock. */
return request_orig;
}
#endif
ret = 0;
miniDiff = ~0;
request = request_orig / 1000;
input = pll->inputFreq / 1000;
/* for MXCLK register , no POD provided, so need be treated differently */
if(pll->clockType != MXCLK_PLL){
xparm = &xparm_PIXEL[0];
xcnt = sizeof(xparm_PIXEL)/sizeof(xparm_PIXEL[0]);
}else{
xparm = &xparm_MXCLK[0];
xcnt = sizeof(xparm_MXCLK)/sizeof(xparm_MXCLK[0]);
}
for(N = 15;N>1;N--)
{
/* RN will not exceed maximum long if @request <= 285 MHZ (for 32bit cpu) */
RN = N * request;
quo = RN / input;
rem = RN % input;/* rem always small than 14318181 */
fl_quo = (rem * 10000 /input);
for(d = xcnt - 1;d >= 0;d--){
X = xparm[d].value;
M = quo*X;
M += fl_quo * X / 10000;
/* round step */
M += (fl_quo*X % 10000)>5000?1:0;
if(M < 256 && M > 0)
{
unsigned int diff;
tmpClock = pll->inputFreq *M / N / X;
diff = absDiff(tmpClock,request_orig);
if(diff < miniDiff)
{
pll->M = M;
pll->N = N;
pll->OD = xparm[d].od;
pll->POD = xparm[d].pod;
miniDiff = diff;
ret = tmpClock;
}
}
}
}
//printk("Finally: pll->n[%lu],m[%lu],od[%lu],pod[%lu]\n",pll->N,pll->M,pll->OD,pll->POD);
return ret;
}
static unsigned int getPowerMode(void)
{
if (getChipType() == SM750LE)
return 0;
return PEEK32(POWER_MODE_CTRL) & POWER_MODE_CTRL_MODE_MASK;
}
