void mt6575_sleep(u32 timeout, kal_bool en_deep_idle)
{
unsigned int topmisc, pdn0;
printf("enter mt6575_sleep, timeout = %d\n", timeout);
#if MT6575_SC_DEBUG
slp_dump_pm_regs();
#endif
pdn0 = DRV_Reg32(PERI_GLOBALCON_PDN0);
if (get_chip_eco_ver() == CHIP_E1) {
/* power on UART0/1/2/3 to workaround handshake mode issue */
DRV_WriteReg32(PERI_GLOBALCON_PDN0, pdn0 & ~(0xf << 24));
}
/* keep CA9 clock when entering WFI mode in sleep */
topmisc = DRV_Reg32(TOP_MISC);
DRV_WriteReg32(TOP_MISC, topmisc & ~(1U << 0));
if (get_chip_eco_ver() != CHIP_E1) {
if (en_deep_idle) {
DRV_WriteReg32(TOPCKGEN_CON3, DRV_Reg32(TOPCKGEN_CON3) & 0x7FFF);
DRV_WriteReg32(MDPLL_CON0, DRV_Reg32(MDPLL_CON0) | 0x1);
}
}
rtc_writeif_lock();
sc_go_to_sleep(timeout, en_deep_idle);
rtc_writeif_unlock();
if (get_chip_eco_ver() != CHIP_E1) {
if (en_deep_idle) {
DRV_WriteReg32(MDPLL_CON0, DRV_Reg32(MDPLL_CON0) & 0xFFFE);
udelay(20);
DRV_WriteReg32(TOPCKGEN_CON3, DRV_Reg32(TOPCKGEN_CON3) | 0x8000);
}
}
/* restore TOP_MISC (and PERI_GLOBALCON_PDN0) */
DRV_WriteReg32(TOP_MISC, topmisc);
if (get_chip_eco_ver() == CHIP_E1)
DRV_WriteReg32(PERI_GLOBALCON_PDN0, pdn0);
return 0;
}
static ssize_t boot_show(struct kobject *kobj, struct attribute *a, char *buf)
{
if (!strncmp(a->name, MD_SYSFS_ATTR, strlen(MD_SYSFS_ATTR)) && md_show)
{
return md_show(buf);
}
else if (!strncmp(a->name, INFO_SYSFS_ATTR, strlen(INFO_SYSFS_ATTR)))
{
return sprintf(buf, "%x%x%x%X%s %X%X%X%X%s\n",
get_reg_chip_code(), get_reg_chip_hw_subcode(),
get_reg_chip_hw_ver(), get_reg_chip_sw_ver(),
get_chip_str(get_chip_eco_ver()),
get_chip_code(), get_chip_hw_subcode(),
get_chip_hw_ver(), get_chip_sw_ver(),
get_chip_str(get_chip_ver()));
}
//kaka_11_0622 add
else if(!strncmp(a->name, FACTORY_RTC_ATTR, strlen(FACTORY_RTC_ATTR)) ){
return factory_mode_show(buf);
}
//kaka_11_0622 end
else
{
return sprintf(buf, "%d\n", g_boot_mode);
}
}
void rtc_gpio_disable_32k(rtc_gpio_user_t user)
{
u16 con, pdn1;
unsigned long flags;
if (user < RTC_GPIO_USER_WIFI || user > RTC_GPIO_USER_FM)
return;
spin_lock_irqsave(&rtc_lock, flags);
pdn1 = rtc_read(RTC_PDN1) & ~(1U << user);
rtc_write(RTC_PDN1, pdn1);
rtc_write_trigger();
if (!(pdn1 & RTC_GPIO_USER_MASK)) { /* no users */
if (get_chip_eco_ver() == CHIP_E1) {
/* keep exporting 32K to avoid f32k_ck drift */
} else {
con = rtc_read(RTC_CON) | RTC_CON_F32KOB;
rtc_write(RTC_CON, con);
rtc_write_trigger();
con = rtc_read(RTC_OSC32CON) & ~RTC_OSC32CON_GPIOCKEN;
rtc_xosc_write(con, true);
}
}
spin_unlock_irqrestore(&rtc_lock, flags);
printk(RTC_SAY "RTC_GPIO user %d disables 32k (0x%x)\n", user, pdn1);
}
/*****************************************
* Routine: board_init
* Description: Early hardware init.
*****************************************/
int board_init (void)
{
/*Warning: DO NOT use "printf" before serial initialize*/
#ifdef CFG_UBOOT_PROFILING
unsigned int time_disp_init;
unsigned int time_led_init;
unsigned int time_pmic6329_init;
unsigned int time_gpio_init;
unsigned int time_wdt_init;
unsigned int time_serial_init;
#endif
mtk_serial_init();
mtk_wdt_init(); // Modify mtk_wdt.h can select dummy function.
mt6577_pinmux_init();
gd->bd->bi_arch_number = MACH_TYPE_MT6577; /* board id for linux */
gd->bd->bi_boot_params = CFG_BOOTARGS_ADDR; /* address of boot parameters */
gd->fb_base = memory_size() - mt65xx_disp_get_vram_size();
#ifdef CFG_UBOOT_PROFILING
time_led_init = get_timer(0);
#endif
leds_init();
isink0_init(); //turn on isink0, HW connection must be floating or pull low
#ifdef CFG_UBOOT_PROFILING
printf("[PROFILE] ------- led init takes %d ms -------- \n", get_timer(time_led_init));
#endif
#ifdef CFG_LCD
#ifdef CFG_UBOOT_PROFILING
time_disp_init = get_timer(0);
#endif
mt65xx_disp_init((void*)gd->fb_base);
UBOOT_TRACER;
#ifdef CFG_UBOOT_PROFILING
printf("[PROFILE] ------- disp init takes %d ms -------- \n", get_timer(time_disp_init));
#endif
#endif
#ifdef CFG_UBOOT_PROFILING
time_pmic6329_init = get_timer(0);
#endif
pmic6329_init();
#ifdef CFG_UBOOT_PROFILING
printf("[PROFILE] ------- pmic6329_init takes %d ms -------- \n", get_timer(time_pmic6329_init));
#endif
printf("[CHIP]: %x-%x\n", get_chip_eco_ver(), get_chip_ver());
return 0;
}
IMG_UINT32 SysCacheBypass(IMG_UINT32 ui32RegVal)
{
if (get_chip_eco_ver() == CHIP_E1) {
/* E1 chip */
ui32RegVal |= 0x80U;
} else {
/* E2 chip */
ui32RegVal |= 0x80U;
}
return ui32RegVal;
}
void cpu_dormant_init(void)
{
void (*restore_ptr)(void);
restore_ptr = cpu_wake_up;
reg_write(BOOTROM_BOOT_ADDR, __pa(restore_ptr));
//BootRom power down
reg_write(BOOTROM_PWR_CTRL, reg_read(BOOTROM_PWR_CTRL) | 0x1);
if (get_chip_eco_ver() == CHIP_E1) {
e1_chip = 1;
}
}
static int __init boot_mod_init(void)
{
int ret;
/* allocate device major number */
if (alloc_chrdev_region(&boot_dev_num, 0, 1, BOOT_DEV_NAME) < 0) {
printk("[%s] fail to register chrdev\n",MOD);
return -1;
}
/* add character driver */
cdev_init(&boot_cdev, &boot_fops);
ret = cdev_add(&boot_cdev, boot_dev_num, 1);
if (ret < 0) {
printk("[%s] fail to add cdev\n",MOD);
return ret;
}
/* create class (device model) */
boot_class = class_create(THIS_MODULE, BOOT_DEV_NAME);
if (IS_ERR(boot_class)) {
printk("[%s] fail to create class\n",MOD);
return (int)boot_class;
}
boot_device = device_create(boot_class, NULL, boot_dev_num, NULL, BOOT_DEV_NAME);
if (IS_ERR(boot_device)) {
printk("[%s] fail to create device\n",MOD);
return (int)boot_device;
}
/* add kobject */
ret = kobject_init_and_add(&boot_kobj, &boot_ktype, &(boot_device->kobj), BOOT_SYSFS);
if (ret < 0) {
printk("[%s] fail to add kobject\n",MOD);
return ret;
}
printk("[%s] chip hw code = 0x%x\n",MOD,get_chip_code());
printk("[%s] chip eco version = 0x%x\n",MOD,get_chip_eco_ver());
/* create proc entry at /proc/boot_mode */
create_proc_read_entry("boot_mode", S_IRUGO, NULL, boot_mode_proc, NULL);
return 0;
}
void mt6577_dcm_init(void)
{
int ret = 0;
#ifdef CONFIG_LOCAL_TIMERS
GPT_CONFIG gpt_config = {
.num = WAKEUP_GPT,
.mode = GPT_ONE_SHOT,
.clkSrc = GPT_CLK_SRC_SYS,
.clkDiv = 0x0000,
.bIrqEnable = true,
.u4CompareL = 0x0,
};
#endif
dcm_info("[%s]: enable HW dcm\n", __func__);
dcm_enable_all();
chip_ver = (get_chip_eco_ver() == CHIP_E1) ? 1 : 0;
memset(dpidle_block_mask, 0, MT65XX_CLOCK_CATEGORY_COUNT * sizeof(unsigned int));
#ifdef CONFIG_LOCAL_TIMERS
GPT_Init(gpt_config.num, NULL);
if (GPT_Config(gpt_config) == FALSE) {
dcm_err("[%s]: config GPT%d failed\n", __func__, gpt_config.num);
}
#endif
ret = sysfs_create_file(power_kobj, &dcm_state_attr.attr);
ret = sysfs_create_file(power_kobj, &idle_state_attr.attr);
ret = sysfs_create_file(power_kobj, &dpidle_state_attr.attr);
if (ret) {
dcm_err("[%s]: create sysfs failed\n", __func__);
}
}
void mt6577_dcm_exit(void)
{
dcm_info("[%s]: disable HW dcm\n", __func__);
dcm_disable_all();
}
BOOL DISP_EsdCheck(void)
{
BOOL result = FALSE;
disp_drv_init_context();
if(lcm_drv->esd_check == NULL)
{
return FALSE;
}
#if defined(CONFIG_ARCH_MT6575)
if(get_chip_eco_ver()==CHIP_E1 && lcm_params->type==LCM_TYPE_DSI)
{
///DSI read is inavailable for E1
return FALSE;
}
#endif
if (down_interruptible(&sem_update_screen)) {
DISP_LOG("ERROR: Can't get sem_update_screen in DISP_EsdCheck()\n");
return FALSE;
}
if(is_lcm_in_suspend_mode)
{
up(&sem_update_screen);
return FALSE;
}
LCD_CHECK_RET(LCD_WaitForNotBusy());
if(lcm_params->type==LCM_TYPE_DSI)
DSI_CHECK_RET(DSI_WaitForNotBusy());
result = lcm_drv->esd_check();
up(&sem_update_screen);
return result;
}
static IMG_VOID SysInitGDC(void)
{
//SysDumpGDCTag("Before");
#if USE_GDC_SHARE_MACRO
enable_clock(MT65XX_PDN_MM_GDC_SHARE_MACRO, "MFG");
enable_clock(MT65XX_PDN_MM_GDC_SHARE_MACRO_HALF, "MFG");
#endif
//DRV_WriteReg32(SMI_LARB3_BASE+0x70, 0x20FF0420);//C20C1070: Port Priority
//DRV_WriteReg32(SMI_LARB3_BASE+0x70, 0x2004FF20);//C20C1070: Port Priority
//DRV_WriteReg32(SMI_LARB3_BASE+0x70, 0x04040404);//C20C1070: Port Priority
DRV_WriteReg32(SMI_LARB3_BASE+0x70, 0x01010101);//C20C1070: Port Priority
DRV_WriteReg32(SMI_LARB3_BASE+0x74, 0x01);//C20C1074
SYSRAM_MFG_SWITCH_BANK(false);
#if ONLY_MFG_DEDICATE_BANK
DRV_WriteReg32(MFG_APB_BASE+0x08, 0xff);
#else
DRV_WriteReg32(MFG_APB_BASE+0x08, 0xffffffff);
//DRV_WriteReg32(SMI_BASE+0x30, 0x7);
#endif
if (get_chip_eco_ver() == CHIP_E1) {
DRV_WriteReg32(MFG_APB_BASE+0x50, 0x3);
} else {
DRV_WriteReg32(MFG_APB_BASE+0x50, 0x1);
}
DRV_WriteReg32(MFG_APB_BASE+0x0C, 0x0);//Set GDC SW Reset
DRV_WriteReg32(MFG_APB_BASE+0x0C, 0x1);//Set GDC SW Reset
DRV_WriteReg32(MFG_APB_BASE+0x04, 0x1);//Set GDC clear
DRV_WriteReg32(MFG_APB_BASE+0x04, 0x0);//Set GDC clear
DRV_WriteReg32(MFG_APB_BASE+0x5C, 0x400);//Set SLF_CNT
//SysDumpGDCTag("After");
//PVRSRVReleasePrintf("[SysInitGDC]MFG_APB_BASE+0x08 = 0x%08x", DRV_Reg32(MFG_APB_BASE+0x08));
//PVRSRVReleasePrintf("[SysInitGDC]MFG_APB_BASE+0x0C = 0x%08x", DRV_Reg32(MFG_APB_BASE+0x0C));
//PVRSRVReleasePrintf("MFG Init GDC");
}
void sc_dpidle_before_wfi(void)
{
#if 0
/* keep CA9 clock frequency when WFI to sleep */
topmisc = DRV_Reg32(TOP_MISC);
DRV_WriteReg32(TOP_MISC, (topmisc & ~(1U << 0)));
#endif
if (unlikely(get_chip_eco_ver() == CHIP_E1)) {
DRV_ClrReg32(WPLL_CON0, 0x1);
} else {
if (!(clk_mgr.subsys_state & 0x30) && clk_mgr.mmsys_state) {
mm_clk_pll2sq();
DRV_SetReg16(MDPLL_CON0, 0x1);
mmsys_switched_off = 1;
}
}
#ifndef CONFIG_LOCAL_TIMERS
if (mmsys_switched_off) {
dpidle_compare_update = dpidle_compare - dpidle_counter - 260;
} else {
dpidle_compare_update = dpidle_compare - dpidle_counter;
}
gpt_set_next_compare(dpidle_compare_update);
#endif
#ifdef CONFIG_LOCAL_WDT
wdt_counter_pre = mpcore_wdt_get_counter();
wdt_tick_pre = GPT_GetCounter(GPT2);
#endif
#ifdef PROFILE_DPIDLE
dpidle_tick_mid = GPT_GetCounter(GPT2);
#endif
}
void DSI_PHY_clk_setting(unsigned int div1, unsigned int div2, unsigned int lane_no)
{
unsigned int tx_ldo_en=0x1;
unsigned int tx_ldo_vocal=0x4;
unsigned int rg_pll_pr_div=0;
unsigned int rg_pll_fb_div2=0;
unsigned int po_div2_en=0x00;
if (div1>0x1e) //vco high speed mode
{
rg_pll_pr_div=1;
rg_pll_fb_div2=1;
}
else
{
rg_pll_pr_div=0;
rg_pll_fb_div2=0;
}
//mipi TX/PLL enable
mipitx_con0.PLL_EN=1;
mipitx_con0.PLL_CLKR_EN=1;
mipitx_con0.RG_LNT_LPTX_BIAS_EN=1;
if(get_chip_eco_ver()==CHIP_E1)
mipitx_con0.RG_LNT_HSTX_EDGE_SEL=1;
else
mipitx_con0.RG_LNT_HSTX_EDGE_SEL=0;
mipitx_con0.RG_DSI_PHY_CK_PSEL=0;
#if defined(MTK_HDMI_SUPPORT)
mipitx_con0.RG_DPI_EN=1;
#else
mipitx_con0.RG_DPI_EN=0;
#endif
mipitx_con0.RG_LNT_HSTX_BIAS_EN=1;
mipitx_con0.RG_LPTX_SWBYPASS=0;
mipitx_con0.RG_PRBS_EN=0;
#if defined(MTK_HDMI_SUPPORT)
mipitx_con0.RG_DPI_CKSEL=2;
#else
mipitx_con0.RG_DPI_CKSEL=3;
#endif
mipitx_con0.RG_CLK_SEL=0;
// mipitx pll setting
mipitx_con1.RG_PLL_DIV1=(div1&0x3F);
mipitx_con1.RG_PLL_DIV2=(div2&0xF);
mipitx_con1.RG_DSI_CK_SEL=(lane_no-1);
mipitx_con1.RG_DSI_CK_DSEL=0;
//mipitx pll pdiv2/prdiv
mipitx_con3.PG_PLL_PRDIV=rg_pll_pr_div;
mipitx_con3.RG_PLL_VCOCAL_CKCTL=0;
mipitx_con3.RG_PLL_FBSEL=rg_pll_fb_div2;
mipitx_con3.RG_PLL_CDIV=0;
mipitx_con3.RG_PLL_ACCEN=0;
//mipitx_con3.RG_PLL_AUTOK_LOAD=0;
//mipitx_con3.RG_PLL_LOAD_RSTB=0;
//mipitx_con3.RG_PLL_AUTOK_EN=0;
mipitx_con3.RG_PLL_PODIV2=po_div2_en;
mipitx_con8.RG_LNTC_HS_CZ=8;
mipitx_con8.RG_LNT0_HS_CZ=8;
mipitx_con8.RG_LNT1_HS_CZ=8;
mipitx_con8.RG_LNT_CIRE=2;
//unsigned int mipitx_con9=(tx_ldo_vocal<<0x0b)|(tx_ldo_en<<0x03);
mipitx_con9.RG_TXLDO_FBCAL=0;
mipitx_con9.RG_TXLDO_EN=tx_ldo_en;
mipitx_con9.RG_TXLDO_IBCAL=0;
mipitx_con9.RG_TXLDO_OCCAL=0;
mipitx_con9.RG_TXLDO_PDDOS_EN=0;
mipitx_con9.RG_TXLDO_VOCAL=tx_ldo_vocal;
DSI_PHY_REG->MIPITX_CON0=mipitx_con0;
DSI_PHY_REG->MIPITX_CON1=mipitx_con1;
DSI_PHY_REG->MIPITX_CON3=mipitx_con3;
DSI_PHY_REG->MIPITX_CON6=mipitx_con6;
DSI_PHY_REG->MIPITX_CON8=mipitx_con8;
DSI_PHY_REG->MIPITX_CON9=mipitx_con9;
// wait pll stable
mdelay(1);
}
static int __init boot_mod_init(void)
{
int ret;
/* allocate device major number */
if (alloc_chrdev_region(&boot_dev_num, 0, 1, BOOT_DEV_NAME) < 0) {
printk("[%s] fail to register chrdev\n",MOD);
return -1;
}
/* add character driver */
cdev_init(&boot_cdev, &boot_fops);
ret = cdev_add(&boot_cdev, boot_dev_num, 1);
if (ret < 0) {
printk("[%s] fail to add cdev\n",MOD);
return ret;
}
/* create class (device model) */
boot_class = class_create(THIS_MODULE, BOOT_DEV_NAME);
if (IS_ERR(boot_class)) {
printk("[%s] fail to create class\n",MOD);
return (int)boot_class;
}
boot_device = device_create(boot_class, NULL, boot_dev_num, NULL, BOOT_DEV_NAME);
if (IS_ERR(boot_device)) {
printk("[%s] fail to create device\n",MOD);
return (int)boot_device;
}
/* add kobject */
ret = kobject_init_and_add(&boot_kobj, &boot_ktype, &(boot_device->kobj), BOOT_SYSFS);
if (ret < 0) {
printk("[%s] fail to add kobject\n",MOD);
return ret;
}
/* read chip version */
ret = load_chip_desp(&g_chip_desp);
if (ret < 0) {
printk("[%s] fail to load chip verion", MOD);
return ret;
}
printk("[%s] APHW_CODE = 0x%x\n",MOD,get_chip_code());
printk("[%s] APHW_VER = 0x%x\n",MOD,get_chip_eco_ver());
/* create proc entry at /proc/boot_mode */
create_proc_read_entry("boot_mode", S_IRUGO, NULL, boot_mode_proc, NULL);
if(g_boot_mode == META_BOOT || g_boot_mode == ADVMETA_BOOT)
{
/* register driver and create sysfs files */
ret = driver_register(&meta_com_type_info);
if (ret)
{
printk("fail to register META COM TYPE driver\n");
}
ret = driver_create_file(&meta_com_type_info, &driver_attr_meta_com_type_info);
if (ret)
{
printk("[BOOT INIT] Fail to create META COM TPYE sysfs file\n");
}
ret = driver_register(&meta_com_id_info);
if (ret)
{
printk("fail to register META COM ID driver\n");
}
ret = driver_create_file(&meta_com_id_info, &driver_attr_meta_com_id_info);
if (ret)
{
printk("[BOOT INIT] Fail to create META COM ID sysfs file\n");
}
}
return 0;
}
/*!
* \brief audio control callback function for CMB_STUB on ALPS
*
* A platform function required for dynamic binding with CMB_STUB on ALPS.
*
* \param state desired audio interface state to use
* \param flag audio interface control options
*
* \retval 0 operation success
* \retval -1 invalid parameters
* \retval < 0 error for operation fail
*/
INT32 wmt_plat_audio_ctrl (CMB_STUB_AIF_X state, CMB_STUB_AIF_CTRL ctrl)
{
INT32 iRet;
UINT32 pinShare;
/* input sanity check */
if ( (CMB_STUB_AIF_MAX <= state)
|| (CMB_STUB_AIF_CTRL_MAX <= ctrl) ) {
return -1;
}
if (get_chip_eco_ver() == CHIP_E1) {
// TODO: [FixMe][GeorgeKuo] how about MT6575? The following is applied to MT6573E1 only!!
pinShare = 1;
WMT_INFO_FUNC( "ALPS MT6573 CHIP_E1 PCM/I2S pin share\n");
}
else{ //E1 later
pinShare = 0;
WMT_INFO_FUNC( "PCM/I2S pin seperate\n");
}
iRet = 0;
/* set host side first */
switch (state) {
case CMB_STUB_AIF_0:
/* BT_PCM_OFF & FM line in/out */
iRet += wmt_plat_gpio_ctrl(PIN_PCM_GRP, PIN_STA_DEINIT);
iRet += wmt_plat_gpio_ctrl(PIN_I2S_GRP, PIN_STA_DEINIT);
break;
case CMB_STUB_AIF_1:
iRet += wmt_plat_gpio_ctrl(PIN_PCM_GRP, PIN_STA_INIT);
iRet += wmt_plat_gpio_ctrl(PIN_I2S_GRP, PIN_STA_DEINIT);
break;
case CMB_STUB_AIF_2:
iRet += wmt_plat_gpio_ctrl(PIN_PCM_GRP, PIN_STA_DEINIT);
iRet += wmt_plat_gpio_ctrl(PIN_I2S_GRP, PIN_STA_INIT);
break;
case CMB_STUB_AIF_3:
iRet += wmt_plat_gpio_ctrl(PIN_PCM_GRP, PIN_STA_INIT);
iRet += wmt_plat_gpio_ctrl(PIN_I2S_GRP, PIN_STA_INIT);
break;
default:
/* FIXME: move to cust folder? */
WMT_ERR_FUNC("invalid state [%d]\n", state);
return -1;
break;
}
if (CMB_STUB_AIF_CTRL_EN == ctrl) {
WMT_INFO_FUNC("call chip aif setting \n");
/* need to control chip side GPIO */
iRet += wmt_lib_set_aif(state, (pinShare) ? MTK_WCN_BOOL_TRUE : MTK_WCN_BOOL_FALSE);
}
else {
WMT_INFO_FUNC("skip chip aif setting \n");
}
return iRet;
}
void sc_mod_init(void)
{
mt6575_init_irq();
gpt_irq_init();
mt6575_irq_set_sens(MT6575_SLEEP_IRQ_ID, MT65xx_LEVEL_SENSITIVE);
mt6575_irq_set_polarity(MT6575_SLEEP_IRQ_ID, MT65xx_POLARITY_LOW);
power_saving_init();
slp_pmic_init();
DRV_WriteReg32(CA9_SCU_CONTROL, (DRV_Reg32(CA9_SCU_CONTROL) | (1 << 5))); // enable_scu_standby
DRV_WriteReg32(CA9_SCU_CONTROL, (DRV_Reg32(CA9_SCU_CONTROL) | (1 << 6))); // enable_scu_ic_standby
/* make AP control whole-chip sleep mode */
DRV_WriteReg32(SC_MD_INTF_CON, 0x363f);
if (get_chip_eco_ver() == CHIP_E1) {
/* to workaround AP+MD sleep/wakeup issue */
DRV_WriteReg32(SC_CLK_SETTLE, (3 << 24) | (3 << 16) | 100);
DRV_WriteReg32(SC_MD_INTF_CON, DRV_Reg32(SC_MD_INTF_CON) | (1U << 2));
DRV_WriteReg32(SC_MD_INTF_CON, DRV_Reg32(SC_MD_INTF_CON) & ~(1U << 10));
} else {
/* typical values can cover MD's RM_SYSCLK_SETTLE = 3 ~ 5 ms */
DRV_WriteReg32(SC_CLK_SETTLE, SC_CLK_SETTLE_TYPICAL);
}
/* MTCMOS power-on sequence: CPUSYS(2) -> CPU(0) -> NEON(3) -> DBG(1) */
DRV_WriteReg32(SC_PWR_CON8, (1 << 20) | (3 << 16) | (0 << 12) | (2 << 8));
DRV_WriteReg32(SC_PWR_CON9, 0x000f);
/* bit 17: DVFS_SEL[0] = 1 depends on AP_SRCLKEN (from E2) */
/* bit 7: STANDBYWFI = STANDBYWFI_CPU & L2CC_IDLE & SCU_IDLE (from E2) */
/* bit 4: enable SRCLKENAI pin */
DRV_WriteReg32(SC_CLK_CON, (1U << 17) | (1U << 7) | (1U << 4));
/* if bus clock source is from 3GPLL, make AP be able to control 3GPLL */
if ((DRV_Reg32(TOP_CKMUXSEL) & 0x3) == 0x2)
DRV_WriteReg32(SC_CLK_CON, DRV_Reg32(SC_CLK_CON) | SC_CLK_CON_3GPLLON);
/* set peripheral control to handshake mode */
DRV_WriteReg32(SC_PERI_CON, 0x0081);
DRV_WriteReg32(SC_PAUSE, 0);
/* mask all wakeup sources */
DRV_WriteReg32(SC_WAKEUP_EVENT_MASK, 0xffffffff);
/* for cleaning wakeup source status */
DRV_WriteReg32(SC_DBG_WAKEUP, 0);
DRV_WriteReg32(SC_TIMER_CON, SC_TIMER_CON_DBG | SC_TIMER_CON_EN);
DRV_WriteReg32(SC_TIMER_CMD, SC_TIMER_CMD_KEY | SC_TIMER_CMD_CONWR |
SC_TIMER_CMD_CNTWR | SC_TIMER_CMD_WR);
while (!(DRV_Reg32(SC_TIMER_STA) & SC_TIMER_STA_CMDCPL));
DRV_WriteReg32(SC_ISR_MASK, 0x0007);
DRV_WriteReg32(SC_ISR_STATUS, 0x0007); /* write 1 clear */
printf("[BATTERY] sc_hw_init : Done\r\n");
}
static void slp_pmic_init(void)
{
if (get_chip_eco_ver() == CHIP_E1)
{
/* 1.175V DVS_VOL_00 */
pmic_config_interface((kal_uint8)(BANK0_VPROC_CON0+BUCK_CON8_OFFSET),
(kal_uint8)(0x13),
(kal_uint8)(BANK_0_BUCK_VOSEL_DVS00_MASK),
(kal_uint8)(BANK_0_BUCK_VOSEL_DVS00_SHIFT)
);
/* 1.25V DVS_VOL_01 */
pmic_config_interface((kal_uint8)(BANK0_VPROC_CON0+BUCK_CON9_OFFSET),
(kal_uint8)(0x16),
(kal_uint8)(BANK_0_BUCK_VOSEL_DVS01_MASK),
(kal_uint8)(BANK_0_BUCK_VOSEL_DVS01_SHIFT)
);
/* 1.175V DVS_VOL_10 */
pmic_config_interface((kal_uint8)(BANK0_VPROC_CON0+BUCK_CONA_OFFSET),
(kal_uint8)(0x13),
(kal_uint8)(BANK_0_BUCK_VOSEL_DVS10_MASK),
(kal_uint8)(BANK_0_BUCK_VOSEL_DVS10_SHIFT)
);
/* 1.25V DVS_VOL_11 */
pmic_config_interface((kal_uint8)(BANK0_VPROC_CON0+BUCK_CONB_OFFSET),
(kal_uint8)(0x16),
(kal_uint8)(BANK_0_BUCK_VOSEL_DVS11_MASK),
(kal_uint8)(BANK_0_BUCK_VOSEL_DVS11_SHIFT)
);
}
else
{
/* 0.975V DVS_VOL_00 */
pmic_config_interface((kal_uint8)(BANK0_VPROC_CON0+BUCK_CON8_OFFSET),
(kal_uint8)(0x0B),
(kal_uint8)(BANK_0_BUCK_VOSEL_DVS00_MASK),
(kal_uint8)(BANK_0_BUCK_VOSEL_DVS00_SHIFT)
);
/* 1.075V DVS_VOL_01 */
pmic_config_interface((kal_uint8)(BANK0_VPROC_CON0+BUCK_CON9_OFFSET),
(kal_uint8)(0x0F),
(kal_uint8)(BANK_0_BUCK_VOSEL_DVS01_MASK),
(kal_uint8)(BANK_0_BUCK_VOSEL_DVS01_SHIFT)
);
/* 1.175V DVS_VOL_10 */
pmic_config_interface((kal_uint8)(BANK0_VPROC_CON0+BUCK_CONA_OFFSET),
(kal_uint8)(0x13),
(kal_uint8)(BANK_0_BUCK_VOSEL_DVS10_MASK),
(kal_uint8)(BANK_0_BUCK_VOSEL_DVS10_SHIFT)
);
/* 1.25V DVS_VOL_11 */
pmic_config_interface((kal_uint8)(BANK0_VPROC_CON0+BUCK_CONB_OFFSET),
(kal_uint8)(0x16),
(kal_uint8)(BANK_0_BUCK_VOSEL_DVS11_MASK),
(kal_uint8)(BANK_0_BUCK_VOSEL_DVS11_SHIFT)
);
}
/* set VPROC to the max. DVS voltage */
DRV_WriteReg32(SC_AP_DVFS_CON, ((DRV_Reg32(SC_AP_DVFS_CON) & 0xFFFFFFFC) | 0x03)); // set VPROC to 1.25V
/* VPROC = 0.9V in sleep mode */
pmic_config_interface((kal_uint8)(BANK0_VPROC_CON0+BUCK_CON6_OFFSET),
(kal_uint8)(0x08),
(kal_uint8)(BANK_0_BUCK_VOSEL_SRCLKEN0_MASK),
(kal_uint8)(BANK_0_BUCK_VOSEL_SRCLKEN0_SHIFT)
);
pmic_config_interface((kal_uint8)(BANK0_VPROC_CON0+BUCK_CONC_OFFSET),
(kal_uint8)(0x03),
(kal_uint8)(BANK_0_RG_BUCK_CTRL_MASK),
(kal_uint8)(BANK_0_RG_BUCK_CTRL_SHIFT)
);
/* VCORE = 0.9V in sleep mode */
pmic_config_interface((kal_uint8)(BANK0_VCORE_CON0+BUCK_CON5_OFFSET),
(kal_uint8)(0x08),
(kal_uint8)(BANK_0_RG_BUCK_VOSEL_MASK),
(kal_uint8)(BANK_0_RG_BUCK_VOSEL_SHIFT)
);
pmic_config_interface((kal_uint8)(BANK0_VCORE_CON0+BUCK_CON7_OFFSET),
(kal_uint8)(0x01),
(kal_uint8)(BANK_0_RG_VCORE_CTRL_MASK),
(kal_uint8)(BANK_0_RG_VCORE_CTRL_SHIFT)
);
/* VM12_INT = 0.9V in sleep mode */
pmic_config_interface(0x8b, 0x08, 0x1f, 0x0);
pmic_config_interface((kal_uint8)(BANK0_DIGLDO_CON9),
(kal_uint8)(0x08),
(kal_uint8)(BANK_0_VM12_INT_SLEEP_MASK),
(kal_uint8)(BANK_0_VM12_INT_SLEEP_SHIFT)
);
pmic_config_interface((kal_uint8)(BANK0_DIGLDO_COND),
(kal_uint8)(0x01),
(kal_uint8)(BANK_0_VM12_INT_CTRL_SEL_MASK),
(kal_uint8)(BANK_0_VM12_INT_CTRL_SEL_SHIFT)
);
pmic_config_interface(0x8C, 0x10, 0x1F, 0x0); // VM12_INT_LOW_BOUND
pmic_config_interface(0x90, 0x1, 0x1, 0x0); // VM12_INT_LP_SEL HW control
pmic_config_interface(0x85, 0x1, 0x1, 0x0); // VM12_1_LP_SEL HW control
pmic_config_interface(0x89, 0x1, 0x1, 0x0); // VM12_2_LP_SEL HW control
pmic_config_interface(0xA9, 0x1, 0x1, 0x0); // VMC_LP_SEL HW control
pmic_config_interface(0xAD, 0x1, 0x1, 0x0); // VMCH_LP_SEL HW control
pmic_config_interface(0xC6, 0x1, 0x1, 0x0); // VA1_LP_SEL HW control
pmic_config_interface(0xC1, 0x1, 0x1, 0x1); // VTCXO_ON_CTRL HW control
/* ARMPLL DIV2 500.5Mhz */
DRV_WriteReg32(TOP_CKDIV1, 0xA);
}
int mt65xx_blink_set(enum mt65xx_led_type type, unsigned long delay_on, unsigned long delay_off)
{
//struct mt65xx_led_data *led_data = led_data_back;
static int got_wake_lock = 0;
struct nled_setting nled_tmp_setting = {0,0,0};
struct cust_mt65xx_led *cust_led_list = get_cust_led_list();
blink_led_data->cust = cust_led_list[type];
// only allow software blink when delay_on or delay_off changed
if (delay_on != blink_led_data->delay_on || delay_off != blink_led_data->delay_off ||type != blink_led_data->type )
{
blink_led_data->delay_on = delay_on;
blink_led_data->delay_off = delay_off;
blink_led_data->type = type;
if (blink_led_data->delay_on && blink_led_data->delay_off)
{ // enable blink
blink_led_data->level = 255; // when enable blink then to set the level (255)
if(blink_led_data->cust.mode == MT65XX_LED_MODE_PWM &&
(blink_led_data->cust.data != PWM3 && blink_led_data->cust.data != PWM4 && blink_led_data->cust.data != PWM5))
{
nled_tmp_setting.nled_mode = NLED_BLINK;
nled_tmp_setting.blink_off_time = blink_led_data->delay_off;
nled_tmp_setting.blink_on_time = blink_led_data->delay_on;
led_blink_pmic(blink_led_data->cust.data, &nled_tmp_setting);
return 0;
}
//#if defined (CONFIG_ARCH_MT6575) || defined (CONFIG_ARCH_MT6575T)|| defined (CONFIG_ARCH_MT6577)
else if((blink_led_data->cust.mode == MT65XX_LED_MODE_PMIC) && (blink_led_data->cust.data == MT65XX_LED_PMIC_NLED_ISINK4
|| blink_led_data->cust.data == MT65XX_LED_PMIC_NLED_ISINK5 || blink_led_data->cust.data == MT65XX_LED_PMIC_NLED_ISINK0))
{
if(get_chip_eco_ver() == CHIP_E2)
{
nled_tmp_setting.nled_mode = NLED_BLINK;
nled_tmp_setting.blink_off_time = blink_led_data->delay_off;
nled_tmp_setting.blink_on_time = blink_led_data->delay_on;
led_blink_pmic(blink_led_data->cust.data, &nled_tmp_setting);
return 0;
}
else
{
// wake_lock(&leds_suspend_lock);
}
}
//#endif
else if (!got_wake_lock)
{
// wake_lock(&leds_suspend_lock);
got_wake_lock = 1;
}
}
else if (!blink_led_data->delay_on && !blink_led_data->delay_off)
{ // disable blink
if(blink_led_data->cust.mode == MT65XX_LED_MODE_PWM &&
(blink_led_data->cust.data != PWM3 && blink_led_data->cust.data != PWM4 && blink_led_data->cust.data != PWM5))
{
brightness_set_pmic(blink_led_data->cust.data, 0);
return 0;
}
//#if defined (CONFIG_ARCH_MT6575) || defined (CONFIG_ARCH_MT6575T)|| defined (CONFIG_ARCH_MT6577)
else if((blink_led_data->cust.mode == MT65XX_LED_MODE_PMIC) && (blink_led_data->cust.data == MT65XX_LED_PMIC_NLED_ISINK4
|| blink_led_data->cust.data == MT65XX_LED_PMIC_NLED_ISINK5 || blink_led_data->cust.data == MT65XX_LED_PMIC_NLED_ISINK0))
{
if(get_chip_eco_ver() == CHIP_E2)
{
brightness_set_pmic(blink_led_data->cust.data, 0);
return 0;
}
else
{
// wake_unlock(&leds_suspend_lock);
}
}
//#endif
else if (got_wake_lock)
{
// wake_unlock(&leds_suspend_lock);
got_wake_lock = 0;
}
}
return -1;
}
// delay_on and delay_off are not changed
return 0;
}
void sc_dpidle_after_wfi(void)
{
#ifdef PROFILE_DPIDLE
dpidle_tick_pos = GPT_GetCounter(GPT2);
dpidle_wakeup_src = DRV_Reg32(SC_WAKEUP_SRC);
if (dpidle_debug_mask & DEBUG_PROFILE) {
#ifdef CONFIG_LOCAL_TIMERS
dcm_info("[%s]%5d %10u %10u %10u %10u %08x\n", __func__,
dpidle_profile_idx, dpidle_tick_pre, dpidle_tick_mid, dpidle_tick_pos,
dpidle_counter, dpidle_wakeup_src);
#else
dcm_info("[%s]%5d %10u %10u %10u %10u %10u %10u %08x\n", __func__,
dpidle_profile_idx, dpidle_tick_pre, dpidle_tick_mid, dpidle_tick_pos,
dpidle_counter, dpidle_compare, dpidle_compare_update, dpidle_wakeup_src);
#endif
dpidle_profile_idx++;
}
#endif
#ifdef CONFIG_LOCAL_WDT
wdt_tick_pos = GPT_GetCounter(GPT2);
if (wdt_counter_pre > (wdt_tick_pos - wdt_tick_pre)) {
wdt_counter_pos = wdt_counter_pre - (wdt_tick_pos - wdt_tick_pre);
mpcore_wdt_set_counter(wdt_counter_pos);
} else {
dcm_info("[%s]:wdt_counter_pre=%10lu, wdt_tick_pre=%10lu, wdt_tick_pos=%10lu\n",
__func__, wdt_counter_pre, wdt_tick_pre, wdt_tick_pos);
mpcore_wdt_set_counter(1);
}
#endif
#ifdef CONFIG_LOCAL_TIMERS
if (GPT_Get_IRQ(WAKEUP_GPT)) {
/* waked up by WAKEUP_GPT */
localtimer_set_next_event(1);
} else {
/* waked up by other wakeup source */
unsigned int temp1 = GPT_GetCompare(WAKEUP_GPT);
unsigned int temp2 = GPT_GetCounter(WAKEUP_GPT);
if (unlikely(temp1 <= temp2)) {
dcm_err("[%s]GPT%d: counter = %10u, compare = %10u\n", __func__, temp1, temp2);
BUG();
}
localtimer_set_next_event(temp1-temp2);
GPT_Stop(WAKEUP_GPT);
GPT_ClearCount(WAKEUP_GPT);
}
#endif
if (get_chip_eco_ver() == CHIP_E1) {
DRV_SetReg32(WPLL_CON0, 0x1);
} else {
if (mmsys_switched_off) {
DRV_ClrReg16(MDPLL_CON0, 0x1);
udelay(20);
mm_clk_sq2pll();
mmsys_switched_off = 0;
}
}
#if 0
/* restore TOP_MISC */
DRV_WriteReg32(TOP_MISC, topmisc);
#endif
dpidle_count++;
if ((dpidle_debug_mask & DEBUG_TRACING)) {
dpidle_single_count++;
}
}
