static ssize_t boot_show(struct kobject *kobj, struct attribute *a, char *buf) { if (!strncmp(a->name, MD_SYSFS_ATTR, strlen(MD_SYSFS_ATTR)) && md_show) { return md_show(buf); } else if (!strncmp(a->name, INFO_SYSFS_ATTR, strlen(INFO_SYSFS_ATTR))) { return sprintf(buf, "%x%x%x%X%s %X%X%X%X%s\n", get_reg_chip_code(), get_reg_chip_hw_subcode(), get_reg_chip_hw_ver(), get_reg_chip_sw_ver(), get_chip_str(get_chip_eco_ver()), get_chip_code(), get_chip_hw_subcode(), get_chip_hw_ver(), get_chip_sw_ver(), get_chip_str(get_chip_ver())); } //kaka_11_0622 add else if(!strncmp(a->name, FACTORY_RTC_ATTR, strlen(FACTORY_RTC_ATTR)) ){ return factory_mode_show(buf); } //kaka_11_0622 end else { return sprintf(buf, "%d\n", g_boot_mode); } }
/***************************************** * Routine: board_init * Description: Early hardware init. *****************************************/ int board_init (void) { /*Warning: DO NOT use "printf" before serial initialize*/ #ifdef CFG_UBOOT_PROFILING unsigned int time_disp_init; unsigned int time_led_init; unsigned int time_pmic6329_init; unsigned int time_gpio_init; unsigned int time_wdt_init; unsigned int time_serial_init; #endif mtk_serial_init(); mtk_wdt_init(); // Modify mtk_wdt.h can select dummy function. mt6577_pinmux_init(); gd->bd->bi_arch_number = MACH_TYPE_MT6577; /* board id for linux */ gd->bd->bi_boot_params = CFG_BOOTARGS_ADDR; /* address of boot parameters */ gd->fb_base = memory_size() - mt65xx_disp_get_vram_size(); #ifdef CFG_UBOOT_PROFILING time_led_init = get_timer(0); #endif leds_init(); isink0_init(); //turn on isink0, HW connection must be floating or pull low #ifdef CFG_UBOOT_PROFILING printf("[PROFILE] ------- led init takes %d ms -------- \n", get_timer(time_led_init)); #endif #ifdef CFG_LCD #ifdef CFG_UBOOT_PROFILING time_disp_init = get_timer(0); #endif mt65xx_disp_init((void*)gd->fb_base); UBOOT_TRACER; #ifdef CFG_UBOOT_PROFILING printf("[PROFILE] ------- disp init takes %d ms -------- \n", get_timer(time_disp_init)); #endif #endif #ifdef CFG_UBOOT_PROFILING time_pmic6329_init = get_timer(0); #endif pmic6329_init(); #ifdef CFG_UBOOT_PROFILING printf("[PROFILE] ------- pmic6329_init takes %d ms -------- \n", get_timer(time_pmic6329_init)); #endif printf("[CHIP]: %x-%x\n", get_chip_eco_ver(), get_chip_ver()); return 0; }
void mt6577_pmic_low_power_init(void) { unsigned int volt = 0, volt_bias = 0; /******************** * PMIC VPROC setting *********************/ upmu_buck_vosel_srclken_0(BUCK_VPROC, 0x08); // VPROC 0.9V in sleep mode if (get_chip_ver() >= CHIP_6577_E1) { upmu_buck_vosel_dvs_00(BUCK_VPROC, 0x08); // 0.900V DVS_VOL_00 upmu_buck_vosel_dvs_01(BUCK_VPROC, 0x0F); // 1.075V DVS_VOL_01 upmu_buck_vosel_dvs_10(BUCK_VPROC, 0x13); // 1.175V DVS_VOL_10 if ((DRV_Reg32(HW_RESV) & (0x1 << 23)) && ((DRV_Reg32(HW_RESV) & (0x1 << 20)) == 0)) { upmu_buck_vosel_dvs_11(BUCK_VPROC, 0x19); // P.K. DVS_VOL_11 } else { if ((DRV_Reg32(HW_RESV) & (0x1 << 21))) volt_bias = 2; else if ((DRV_Reg32(HW_RESV) & (0x1 << 22))) volt_bias = 1; else volt_bias = 0; volt = (DRV_Reg32(HW_RESV) & 0xE000) >> 13; if (volt == 0x0) upmu_buck_vosel_dvs_11(BUCK_VPROC, (0x17 + volt_bias)); else if (volt == 0x1) upmu_buck_vosel_dvs_11(BUCK_VPROC, (0x16 + volt_bias)); else if (volt == 0x2) upmu_buck_vosel_dvs_11(BUCK_VPROC, (0x15 + volt_bias)); else if (volt == 0x3) upmu_buck_vosel_dvs_11(BUCK_VPROC, (0x14 + volt_bias)); else if (volt == 0x4) upmu_buck_vosel_dvs_11(BUCK_VPROC, (0x13 + volt_bias)); else if (volt == 0x5) upmu_buck_vosel_dvs_11(BUCK_VPROC, (0x18 + volt_bias)); else if (volt == 0x6) upmu_buck_vosel_dvs_11(BUCK_VPROC, (0x19 + volt_bias)); else if (volt == 0x7) upmu_buck_vosel_dvs_11(BUCK_VPROC, (0x19 + volt_bias)); else upmu_buck_vosel_dvs_11(BUCK_VPROC, (0x13 + volt_bias)); } }
static void slp_pmic_init(void) { unsigned int volt = 0, volt_bias = 0; if (get_chip_ver() >= CHIP_6577_E1) { if ((DRV_Reg32(HW_RESV) & (0x1 << 23)) && ((DRV_Reg32(HW_RESV) & (0x1 << 20)) == 0)) { slp_pmic_dvs_vol_init(0x19); } else { if ((DRV_Reg32(HW_RESV) & (0x1 << 21))) volt_bias = 2; else if ((DRV_Reg32(HW_RESV) & (0x1 << 22))) volt_bias = 1; else volt_bias = 0; volt = (DRV_Reg32(HW_RESV) & 0xE000) >> 13; if (volt == 0x0) { slp_pmic_dvs_vol_init((0x17 + volt_bias)); } else if (volt == 0x1) { slp_pmic_dvs_vol_init((0x16 + volt_bias)); } else if (volt == 0x2) { slp_pmic_dvs_vol_init((0x15 + volt_bias)); } else if (volt == 0x3) { slp_pmic_dvs_vol_init((0x14 + volt_bias)); } else if (volt == 0x4) { slp_pmic_dvs_vol_init((0x13 + volt_bias)); } else if (volt == 0x5) { slp_pmic_dvs_vol_init((0x18 + volt_bias)); } else if (volt == 0x6) { slp_pmic_dvs_vol_init((0x19 + volt_bias)); } else if (volt == 0x7) { slp_pmic_dvs_vol_init((0x19 + volt_bias)); } else { slp_pmic_dvs_vol_init((0x13 + volt_bias)); } } } else { if ((DRV_Reg32(HW_RESV) & (0x1 << 29)))
void mt_power_management_init(void) { struct proc_dir_entry *entry = NULL; struct proc_dir_entry *pm_init_dir = NULL; #if !defined (CONFIG_MT6577_FPGA) xlog_printk(ANDROID_LOG_INFO, "Power/PM_INIT", "Chip Version = 0x%x, Bus Frequency = %d KHz\n", get_chip_ver(), mt6577_get_bus_freq()); chip_dep_init(); // set specific chip setting slp_mod_init(); // sleep controller init mt6577_clk_mgr_init(); // clock manager init, including clock gating init mt6577_pm_log_init(); // power management log init mt6577_dcm_init(); // dynamic clock management init pm_init_dir = proc_mkdir("pm_init", NULL); if (!pm_init_dir) { pr_err("[%s]: mkdir /proc/pm_init failed\n", __FUNCTION__); } else { entry = create_proc_entry("pmic_reg_dump", S_IRUGO, pm_init_dir); if (entry) { entry->read_proc = pmic_reg_dump_read; } entry = create_proc_entry("cpu_speed_dump", S_IRUGO, pm_init_dir); if (entry) { entry->read_proc = cpu_speed_dump_read; } } #endif }
void mt_pmic_low_power_init(void) { unsigned int volt = 0; /******************** * PMIC VPROC setting *********************/ upmu_buck_vosel_srclken_0(BUCK_VPROC, 0x08); // VPROC 0.9V in sleep mode if (get_chip_ver() >= CHIP_6577_E1) { volt = mt_pmic_cpu_max_volt(); if ((DRV_Reg32(HW_RESV) & (0x1 << 23)) && ((DRV_Reg32(HW_RESV) & (0x1 << 20)) == 0)) { upmu_buck_vosel_dvs_00(BUCK_VPROC, volt); upmu_buck_vosel_dvs_01(BUCK_VPROC, 0x0F); // 1.075V DVS_VOL_01 upmu_buck_vosel_dvs_10(BUCK_VPROC, 0x13); // 1.175V DVS_VOL_10 upmu_buck_vosel_dvs_11(BUCK_VPROC, 0x17); // 1.275V DVS_VOL_11 } else { if (DRV_Reg32(HW_RESV) & (0x1 << 12)) { if ((DRV_Reg32(HW_RESV) & (0x1 << 17)) && ((DRV_Reg32(HW_RESV) & (0x1 << 16)) == 0)) { upmu_buck_vosel_dvs_00(BUCK_VPROC, volt); upmu_buck_vosel_dvs_01(BUCK_VPROC, 0x0F); // 1.075V DVS_VOL_01 upmu_buck_vosel_dvs_10(BUCK_VPROC, 0x13); // 1.175V DVS_VOL_10 upmu_buck_vosel_dvs_11(BUCK_VPROC, 0x17); // 1.275V DVS_VOL_11 } else { upmu_buck_vosel_dvs_00(BUCK_VPROC, 0x08); // 0.900V DVS_VOL_00 upmu_buck_vosel_dvs_01(BUCK_VPROC, 0x0F); // 1.075V DVS_VOL_01 upmu_buck_vosel_dvs_10(BUCK_VPROC, 0x13); // 1.175V DVS_VOL_10 upmu_buck_vosel_dvs_11(BUCK_VPROC, volt); } } else { upmu_buck_vosel_dvs_00(BUCK_VPROC, 0x08); // 0.900V DVS_VOL_00 upmu_buck_vosel_dvs_01(BUCK_VPROC, 0x0F); // 1.075V DVS_VOL_01 upmu_buck_vosel_dvs_10(BUCK_VPROC, 0x13); // 1.175V DVS_VOL_10 upmu_buck_vosel_dvs_11(BUCK_VPROC, volt); } } } else if (get_chip_ver() >= CHIP_6575_E2) { upmu_buck_vosel_dvs_00(BUCK_VPROC, 0x0B); upmu_buck_vosel_dvs_01(BUCK_VPROC, 0x0F); upmu_buck_vosel_dvs_10(BUCK_VPROC, 0x13); if ((DRV_Reg32(HW_RESV) & (0x1 << 29))) { upmu_buck_vosel_dvs_11(BUCK_VPROC, 0x17); } else { upmu_buck_vosel_dvs_11(BUCK_VPROC, 0x16); } } else if (get_chip_ver() >= CHIP_6575_E1) { upmu_buck_vosel_dvs_00(BUCK_VPROC, 0x13); if ((DRV_Reg32(HW_RESV) & (0x1 << 29))) { upmu_buck_vosel_dvs_01(BUCK_VPROC, 0x17); } else { upmu_buck_vosel_dvs_01(BUCK_VPROC, 0x16); } upmu_buck_vosel_dvs_10(BUCK_VPROC, 0x13); if ((DRV_Reg32(HW_RESV) & (0x1 << 29))) { upmu_buck_vosel_dvs_11(BUCK_VPROC, 0x17); } else { upmu_buck_vosel_dvs_11(BUCK_VPROC, 0x16); } } else { upmu_buck_vosel_dvs_00(BUCK_VPROC, 0x16); upmu_buck_vosel_dvs_01(BUCK_VPROC, 0x16); upmu_buck_vosel_dvs_10(BUCK_VPROC, 0x16); upmu_buck_vosel_dvs_11(BUCK_VPROC, 0x16); } DRV_WriteReg32(SC_AP_DVFS_CON, ((DRV_Reg32(SC_AP_DVFS_CON) & 0xFFFFFFFC) | 0x03)); // set cpu to top voltage upmu_buck_ctrl(BUCK_VPROC, 0x3); // VPROC controlled by SRCLKEN and AP_DVFS_CON1/0 /******************** * PMIC VCORE setting *********************/ if ((DRV_Reg32(HW_RESV) & (0x1 << 19))) { upmu_buck_vosel(BUCK_VCORE, UPMU_VOLT_0_8_0_0_V); // VCORE 0.8V in sleep mode } else { upmu_buck_vosel(BUCK_VCORE, UPMU_VOLT_0_9_0_0_V); // VCORE 0.9V in sleep mode } /******************** * PMIC Other setting *********************/ pmic_config_interface(0x8B, 0x08, 0x1F, 0x0); // VM12_INT 0.9V in sleep mode pmic_config_interface(0x8C, 0x10, 0x1F, 0x0); // VM12_INT_LOW_BOUND pmic_config_interface(0x8F, 0x01, 0x01, 0x4); // VM12_INT Tracking VPROC pmic_config_interface(0x90, 0x01, 0x01, 0x0); // VM12_INT_LP_SEL HW control pmic_config_interface(0x85, 0x01, 0x01, 0x0); // VM12_1_LP_SEL HW control pmic_config_interface(0x89, 0x01, 0x01, 0x0); // VM12_2_LP_SEL HW control pmic_config_interface(0xA9, 0x01, 0x01, 0x0); // VMC_LP_SEL HW control pmic_config_interface(0xAD, 0x01, 0x01, 0x0); // VMCH_LP_SEL HW control pmic_config_interface(0xC6, 0x01, 0x01, 0x0); // VA1_LP_SEL HW control pmic_config_interface(0xC1, 0x01, 0x01, 0x1); // VTCXO_ON_CTRL HW control pmic_config_interface(0x4F, 0x01, 0x01, 0x6); // BUCK clock keep 2MHz select pmic_config_interface(0x4F, 0x01, 0x01, 0x7); // OSC10M and 2M auto select function enable }