/*get the pin by name*/
struct iomux_pin *iomux_get_pin(char *name)
{
int i = 0;
int chip_id = 0;
struct iomux_pin *pin = NULL;
struct iomux_pin_table *pintable = &pins_table_cs[0];
chip_id = get_chipid();
if (chip_id == CS_CHIP_ID) {
pintable = &pins_table_cs[0];
} else if (chip_id == DI_CHIP_ID) {
pintable = &pins_table[0];
} else {
pr_err("%s %d no proper chip id find.\n", __func__, __LINE__);
}
while (pintable[i].pinname) {
if (strncmp(name, pintable[i].pinname, MAX_NAME_CHARS)) {
i++;
} else {
pin = pintable[i].iomux_pin;
if (pin->init == 0) {
spin_lock_init(&pin->spinlock);
pin->init = 1;
}
break;
}
}
if (pin == NULL)
pr_err("IOMUX:%s pin get failed.\r\n", name);
return pin;
}
/* set host timing config */
static void mshci_hi_update_timing(struct mshci_host *ms_host, int bsuspend)
{
struct himci_host * hi_host = (struct himci_host *)(ms_host->private);
unsigned int config_val;
if ( get_chipid() == DI_CHIP_ID ) {
if (bsuspend) {
config_val = hi_host->suspend_timing_config;
} else {
hi_host_trace(HIMCI_TRACE_SIGNIFICANT, "current signal voltage = %d",
hi_host->old_sig_voltage);
hi_host_trace(HIMCI_TRACE_SIGNIFICANT, "current timing = %d",
hi_host->old_timing);
config_val = hi_host->timing_config[hi_host->old_timing + \
hi_host->old_sig_voltage * (MMC_TIMING_UHS_DDR50 + 1)];
}
hi_host_trace(HIMCI_TRACE_SIGNIFICANT, "current timing config = 0x%x",
config_val);
if (-1 == config_val) {
himci_error("invalid config_val");
}
writel(0xF << (hi_host->pdev->id * 4),
IO_ADDRESS(REG_BASE_SCTRL) + REG_SCPERDIS4);
writel(config_val << (hi_host->pdev->id * 4),
IO_ADDRESS(REG_BASE_SCTRL) + REG_SCPEREN4);
hi_host_trace(HIMCI_TRACE_SIGNIFICANT, "new reg val 0x%x",
readl(IO_ADDRESS(REG_BASE_SCTRL) + REG_SCPERSTAT4));
}
}
static unsigned int mshci_hi_get_max_clk(struct mshci_host *ms_host)
{
if ( get_chipid() == CS_CHIP_ID )
return MMC_CCLK_MAX_50M;
else
return MMC_CCLK_MAX;
}
static void *get_ddrtr_entry(void)
{
char *src_ptr = NULL;
char *dst_ptr;
unsigned int length = 0;
long long chipid = get_chipid();
int reg;
#ifdef CONFIG_DDR_TRAINING_HI3535
if (chipid == _HI3535_V100) {
/* reset slave cpu, make cpu stop */
reg = readl(COREX_RST_REG_BASE + COREX_RST_REG);
reg |= (7 << 4);
writel(reg, COREX_RST_REG_BASE + COREX_RST_REG);
src_ptr = hi3535_ddr_training_data_start;
dst_ptr = (char *)(STACK_TRAINING);
length = hi3535_ddr_training_data_end - src_ptr;
}
#endif
if (!src_ptr || !length) {
printf("%s DDR training is unsupport.\n", __func__);
return NULL;
}
memcpy(dst_ptr, src_ptr, length);
return (void *) dst_ptr;
}
int initialize_mcu(struct ssp_data *data)
{
int iRet = 0;
clean_pending_list(data);
iRet = get_chipid(data);
pr_info("[SSP] MCU device ID = %d, reading ID = %d\n", DEVICE_ID, iRet);
if (iRet != DEVICE_ID) {
if (iRet < 0) {
pr_err("[SSP]: %s - MCU is not working : 0x%x\n",
__func__, iRet);
} else {
pr_err("[SSP]: %s - MCU identification failed\n",
__func__);
iRet = -ENODEV;
}
goto out;
}
iRet = set_sensor_position(data);
if (iRet < 0) {
pr_err("[SSP]: %s - set_sensor_position failed\n", __func__);
goto out;
}
#ifdef CONFIG_SENSORS_MULTIPLE_GLASS_TYPE
iRet = set_glass_type(data);
if (iRet < 0) {
pr_err("[SSP]: %s - set_sensor_position failed\n", __func__);
goto out;
}
#endif
data->uSensorState = get_sensor_scanning_info(data);
if (data->uSensorState == 0) {
pr_err("[SSP]: %s - get_sensor_scanning_info failed\n",
__func__);
iRet = ERROR;
goto out;
}
iRet = initialize_magnetic_sensor(data);
if (iRet < 0)
pr_err("[SSP]: %s - initialize magnetic sensor failed\n",
__func__);
data->uCurFirmRev = get_firmware_rev(data);
pr_info("[SSP] MCU Firm Rev : New = %8u\n",
data->uCurFirmRev);
// hoi: il dan mak a
#ifndef CONFIG_SENSORS_SSP_BBD
iRet = ssp_send_cmd(data, MSG2SSP_AP_MCU_DUMP_CHECK, 0);
#endif
out:
return iRet;
}
static ssize_t config_chipid_read(struct file *filp, char __user *buffer, size_t count, loff_t *ppos)
{
int len = 0;
char idarray[32];
memset(idarray, 0, 32);
len = sprintf(idarray, "0x%08x\n", get_chipid());
return simple_read_from_buffer(buffer, count, ppos, (void *)idarray, len);
}
static void hi_mci_sys_ctrl_init(struct himci_host *host,
resource_size_t host_crg_addr)
{
unsigned int tmp_reg;
if ((SDIO_REG_BASE_CRG + PERI_CRG39) == (unsigned int)host_crg_addr) {
/* enable SDIO clock */
tmp_reg = himci_readl(host_crg_addr);
tmp_reg &= ~SDIO0_CLK_SEL_MASK;
tmp_reg &= ~SDIO0_DRV_PS_SEL_MASK;
tmp_reg &= ~SDIO0_SAP_PS_SEL_MASK;
tmp_reg |= SDIO0_CLK_SEL_50M | SDIO0_DRV_PS_SEL_135
| SDIO0_SAP_PS_SEL_90;
himci_writel(tmp_reg, host_crg_addr);
/* SDIO soft reset */
tmp_reg = himci_readl(host_crg_addr);
tmp_reg |= SDIO0_SRST_REQ;
himci_writel(tmp_reg, host_crg_addr);
udelay(1000);
tmp_reg &= ~SDIO0_SRST_REQ;
tmp_reg |= SDIO0_CKEN | SDIO0_BUS_CKEN;
himci_writel(tmp_reg, host_crg_addr);
return;
}
if ((SDIO_REG_BASE_CRG + PERI_CRG40) == (unsigned int)host_crg_addr) {
/* SDIO clock phase */
if (_HI3716CV200ES == get_chipid()) {
tmp_reg = himci_readl(host_crg_addr);
tmp_reg &= ~(SDIO1_CLK_SEL_MASK | SDIO1_DRV_PS_SEL_MASK
| SDIO1_SAP_PS_SEL_MASK);
tmp_reg |= SDIO1_CLK_SEL_50M | SDIO1_DRV_PS_SEL_45;
himci_writel(tmp_reg, host_crg_addr);
} else {
tmp_reg = himci_readl(host_crg_addr);
tmp_reg &= ~SDIO1_CLK_SEL_MASK;
tmp_reg |= SDIO1_CLK_SEL_50M;
himci_writel(tmp_reg, host_crg_addr);
}
/* SDIO soft reset */
tmp_reg |= SDIO1_SRST_REQ;
himci_writel(tmp_reg, host_crg_addr);
udelay(1000);
tmp_reg &= ~SDIO1_SRST_REQ;
tmp_reg |= SDIO1_CKEN | SDIO1_BUS_CKEN;
himci_writel(tmp_reg, host_crg_addr);
return;
}
return;
}
static int ddr_training_result(unsigned int TRAINING_ADDR)
{
long long chipid = get_chipid();
#ifdef CONFIG_DDR_TRAINING_HI3535
if (chipid == _HI3535_V100)
return hi3535_ddr_training_result(TRAINING_ADDR);
#endif
printf("DDR training is unsupport.\n");
return -1;
}
int hieth_port_reset(struct hieth_netdev_local *ld, int port)
{
long long chipid = get_chipid();
hieth_assert(port == ld->port);
/*soft reset */
if (chipid == _HI3712_V100) {
hieth_writel_bits(ld, 1, GLB_SOFT_RESET,
HI3712_BITS_ETH_SOFT_RESET);
msleep(1);
hieth_writel_bits(ld, 0, GLB_SOFT_RESET,
HI3712_BITS_ETH_SOFT_RESET);
msleep(1);
hieth_writel_bits(ld, 1, GLB_SOFT_RESET,
HI3712_BITS_ETH_SOFT_RESET);
msleep(1);
hieth_writel_bits(ld, 0, GLB_SOFT_RESET,
HI3712_BITS_ETH_SOFT_RESET);
} else {
if (ld->port == UP_PORT) {
/* Note: sf ip need reset twice */
hieth_writel_bits(ld, 1, GLB_SOFT_RESET,
BITS_ETH_SOFT_RESET_UP);
msleep(1);
hieth_writel_bits(ld, 0, GLB_SOFT_RESET,
BITS_ETH_SOFT_RESET_UP);
msleep(1);
hieth_writel_bits(ld, 1, GLB_SOFT_RESET,
BITS_ETH_SOFT_RESET_UP);
msleep(1);
hieth_writel_bits(ld, 0, GLB_SOFT_RESET,
BITS_ETH_SOFT_RESET_UP);
} else if (ld->port == DOWN_PORT) {
/* Note: sf ip need reset twice */
hieth_writel_bits(ld, 1, GLB_SOFT_RESET,
BITS_ETH_SOFT_RESET_DOWN);
msleep(1);
hieth_writel_bits(ld, 0, GLB_SOFT_RESET,
BITS_ETH_SOFT_RESET_DOWN);
msleep(1);
hieth_writel_bits(ld, 1, GLB_SOFT_RESET,
BITS_ETH_SOFT_RESET_DOWN);
msleep(1);
hieth_writel_bits(ld, 0, GLB_SOFT_RESET,
BITS_ETH_SOFT_RESET_DOWN);
} else
BUG();
}
return 0;
}
void list_chipinfo()
{
u8 i,size = sizeof(g_chipid);
get_chipid();
rt_kprintf("chip id: ");
//chip id: 05DDFF36 34305432 43254142
//chip id: 42412543 32543034 36FFDD05
//chip id: 43254142-34305432-05DDFF36
for (i=0;i<size;i++)
{
rt_kprintf("%02X",g_chipid[i]);
}
rt_kprintf("\n");
}
int initialize_mcu(struct ssp_data *data)
{
int iRet = 0;
clean_pending_list(data);
iRet = get_chipid(data);
ssp_info("MCU device ID = %d, reading ID = %d", DEVICE_ID, iRet);
if (iRet != DEVICE_ID) {
if (iRet < 0) {
ssp_errf("MCU is not working : 0x%x", iRet);
} else {
ssp_errf("MCU identification failed");
iRet = -ENODEV;
}
goto out;
}
iRet = set_sensor_position(data);
if (iRet < 0) {
ssp_errf("set_sensor_position failed");
goto out;
}
#ifdef CONFIG_SENSORS_MULTIPLE_GLASS_TYPE
iRet = set_glass_type(data);
if (iRet < 0) {
pr_err("[SSP]: %s - set_sensor_position failed\n", __func__);
goto out;
}
#endif
data->uSensorState = get_sensor_scanning_info(data);
if (data->uSensorState == 0) {
ssp_errf("get_sensor_scanning_info failed");
iRet = ERROR;
goto out;
}
iRet = initialize_magnetic_sensor(data);
if (iRet < 0)
ssp_errf("initialize magnetic sensor failed");
data->uCurFirmRev = get_firmware_rev(data);
ssp_info("MCU Firm Rev : New = %8u", data->uCurFirmRev);
out:
return iRet;
}
static int k3v2_cfgaxi_clk_enable(struct clk *clk)
{
int chip_id = 0;
void __iomem *clk_addr1 = NULL;
clk_addr1 = (void __iomem *)DIV_REG0;
/*set pll2 as source clock for axi*/
chip_id = get_chipid();
if (chip_id == CS_CHIP_ID)
writel(CFGAXI_SEL_VALUE, clk_addr1);
/*set rate*/
writel(CFGAXI_NORMAL_DIV_VALUE, clk_addr1);
clk->rate = CFGAXI_NORMAL_RATE;
return 0;
}
int initialize_mcu(struct ssp_data *data)
{
int iRet = 0;
iRet = get_chipid(data);
pr_info("[SSP] MCU device ID = %d, reading ID = %d\n", DEVICE_ID, iRet);
if (iRet != DEVICE_ID) {
if (iRet < 0) {
pr_err("[SSP]: %s - MCU is not working : 0x%x\n",
__func__, iRet);
} else {
pr_err("[SSP]: %s - MCU identification failed\n",
__func__);
iRet = -ENODEV;
}
goto out;
}
iRet = set_sensor_position(data);
if (iRet < 0) {
pr_err("[SSP]: %s - set_sensor_position failed\n", __func__);
goto out;
}
data->uSensorState = get_sensor_scanning_info(data);
if (data->uSensorState == 0) {
pr_err("[SSP]: %s - get_sensor_scanning_info failed\n",
__func__);
iRet = ERROR;
goto out;
}
iRet = ssp_send_cmd(data, MSG2SSP_AP_MCU_SET_DUMPMODE,
sec_debug_is_enabled());
if (iRet < 0) {
pr_err("[SSP]: %s - set_mcu_dump_mode failed\n", __func__);
goto out;
}
#if defined (CONFIG_SENSORS_SSP_YAS532)
iRet = set_static_matrix(data);
if (iRet < 0)
pr_err("[SSP]: %s - yas set static matrix failed\n", __func__);
#endif
iRet = SUCCESS;
out:
return iRet;
}
int initialize_mcu(struct ssp_data *data)
{
int iRet = 0;
clean_pending_list(data);
iRet = get_chipid(data);
pr_info("[SSP] MCU device ID = %d, reading ID = %d\n", DEVICE_ID, iRet);
if (iRet != DEVICE_ID) {
if (iRet < 0) {
pr_err("[SSP]: %s - MCU is not working : 0x%x\n",
__func__, iRet);
} else {
pr_err("[SSP]: %s - MCU identification failed\n",
__func__);
iRet = -ENODEV;
}
goto out;
}
iRet = set_sensor_position(data);
if (iRet < 0) {
pr_err("[SSP]: %s - set_sensor_position failed\n", __func__);
goto out;
}
iRet = get_fuserom_data(data);
if (iRet < 0)
pr_err("[SSP]: %s - get_fuserom_data failed\n", __func__);
data->uSensorState = get_sensor_scanning_info(data);
if (data->uSensorState == 0) {
pr_err("[SSP]: %s - get_sensor_scanning_info failed\n",
__func__);
iRet = ERROR;
goto out;
}
data->uCurFirmRev = get_firmware_rev(data);
pr_info("[SSP] MCU Firm Rev : New = %8u\n",
data->uCurFirmRev);
iRet = ssp_send_cmd(data, MSG2SSP_AP_MCU_DUMP_CHECK, 0);
out:
return iRet;
}
int initialize_mcu(struct ssp_data *data)
{
int iRet = 0;
iRet = get_chipid(data);
pr_info("[SSP] MCU device ID = %d, reading ID = %d\n", DEVICE_ID, iRet);
if (iRet != DEVICE_ID) {
if (iRet < 0) {
pr_err("[SSP]: %s - MCU is not working : 0x%x\n",
__func__, iRet);
} else {
pr_err("[SSP]: %s - MCU identification failed\n",
__func__);
iRet = -ENODEV;
}
goto out;
}
iRet = set_sensor_position(data);
if (iRet < 0) {
pr_err("[SSP]: %s - set_sensor_position failed\n", __func__);
goto out;
}
iRet = set_magnetic_static_matrix(data);
if (iRet < 0)
pr_err("[SSP] %s - set_magnetic_static_matrix failed\n", __func__);
iRet = get_fuserom_data(data);
if (iRet < 0)
pr_err("[SSP]: %s - get_fuserom_data failed\n", __func__);
data->uSensorState = get_sensor_scanning_info(data);
if (data->uSensorState == 0) {
pr_err("[SSP]: %s - get_sensor_scanning_info failed\n",
__func__);
iRet = ERROR;
goto out;
}
iRet = SUCCESS;
out:
return iRet;
}
/*cpu2 & cpu3 vcc*/
static int vcc_cpu23_is_enabled(struct regulator_dev *dev)
{
u32 val = 0;
u32 bit_mask = 0;
int chip_id = 0;
int regulator_id;
void __iomem *base_addr = NULL;
struct vcc_resource *vcc_resource_data = NULL;
regulator_id = rdev_get_id(dev);
vcc_resource_data = rdev_get_drvdata(dev);
base_addr = vcc_resource_data->base;
bit_mask = 0x01 << regulator_id;
lock(®_lock_mutex);
chip_id = get_chipid();
if (chip_id == CS_CHIP_ID) {
val = readl(base_addr + PWR_ACK_REG) & (bit_mask << 1);/*the final status*/
val = val >> (regulator_id + 1);
} else if (chip_id == DI_CHIP_ID) {
int initialize_mcu(struct ssp_data *data)
{
int iRet = 0;
iRet = get_chipid(data);
pr_info("[SSP] MPU device ID = %d, reading ID = %d\n", DEVICE_ID, iRet);
if (iRet != DEVICE_ID) {
if (iRet < 0)
pr_err("[SSP]: %s - i2c for reading chip id failed\n",
__func__);
else {
pr_err("[SSP]: %s - Device identification failed\n",
__func__);
iRet = -ENODEV;
}
return iRet;
}
iRet = set_sensor_position(data);
if (iRet < 0) {
pr_err("[SSP]: %s - set_sensor_position failed\n", __func__);
return iRet;
}
iRet = get_fuserom_data(data);
if (iRet < 0) {
pr_err("[SSP]: %s - get_fuserom_data failed\n", __func__);
return iRet;
}
data->uAliveSensorDebug = get_sensor_scanning_info(data);
if (data->uAliveSensorDebug == 0) {
pr_err("[SSP]: %s - get_sensor_scanning_info failed\n",
__func__);
return FAIL;
}
return SUCCESS;
}
static void * get_ddrtr_entry(void)
{
char *src_ptr = NULL;
char *dst_ptr;
unsigned int length = 0;
long long chipid = get_chipid();
#ifdef CONFIG_DDR_TRAINING_HI3716MV300
if (chipid == _HI3716M_V300) {
src_ptr = hi3716mv300_ddr_training_data_start;
dst_ptr = (char *)(0x0001000);
length = hi3716mv300_ddr_training_data_end - src_ptr;
}
#endif
if (!src_ptr || !length) {
printf("DDR training is unsupport.\n");
return NULL;
}
memcpy(dst_ptr, src_ptr, length);
return (void *) dst_ptr;
}
static void hieth_phy_reset(void)
{
long long chipid;
unsigned int val;
unsigned int old;
chipid = get_chipid();
if (_HI3712_V100 == chipid) {
/* TODO: HI3712 ASIC should config GPIO for phy reset!!. */
/* config pin re-use to miirst */
old = val = _readl(HI3712_ETH_GPIO_BASE + HI3712_ETH_GPIO_REG);
val |= 0x1;
_writel(val, HI3712_ETH_GPIO_BASE + HI3712_ETH_GPIO_REG);
/* do phy reset */
val = _readl(HIETH_SYSREG_BASE + HIETH_SYSREG_REG);
val |= HI3712_ETH_SYSREG_RST_BIT;
_writel(val, HIETH_SYSREG_BASE + HIETH_SYSREG_REG);
udelay(20000);
val = _readl(HIETH_SYSREG_BASE + HIETH_SYSREG_REG);
val &= ~HI3712_ETH_SYSREG_RST_BIT;
_writel(val, HIETH_SYSREG_BASE + HIETH_SYSREG_REG);
udelay(20000);
_writel(old, HI3712_ETH_GPIO_BASE + HI3712_ETH_GPIO_REG);
} else if (chipid == _HI3716M_V300) {
/* config pin re-use to miirst */
old = val =
_readl(HI3716MV300_ETH_GPIO_BASE +
HI3716MV300_ETH_GPIO_REG);
val |= 0x1;
_writel(val,
HI3716MV300_ETH_GPIO_BASE + HI3716MV300_ETH_GPIO_REG);
/* do phy reset */
val = _readl(HIETH_SYSREG_BASE + HIETH_SYSREG_REG);
val |= HI3716MV300_ETH_SYSREG_RST_BIT;
_writel(val, HIETH_SYSREG_BASE + HIETH_SYSREG_REG);
udelay(20000);
val = _readl(HIETH_SYSREG_BASE + HIETH_SYSREG_REG);
val &= ~HI3716MV300_ETH_SYSREG_RST_BIT;
_writel(val, HIETH_SYSREG_BASE + HIETH_SYSREG_REG);
udelay(20000);
_writel(old,
HI3716MV300_ETH_GPIO_BASE + HI3716MV300_ETH_GPIO_REG);
} else {
# ifdef HISFV_RESET_GPIO_EN
/* gpiox[x] set to reset, then delay 200ms */
val = __raw_readb(HISFV_RESET_GPIO_BASE + HISFV_RESET_GPIO_DIR);
val |= (HISFV_RESET_GPIO_DIR_OUT << HISFV_RESET_GPIO_BIT);
__raw_writeb(val, HISFV_RESET_GPIO_BASE + HISFV_RESET_GPIO_DIR);
__raw_writeb(HISFV_RESET_GPIO_DATA,
HISFV_RESET_GPIO_BASE +
(4 << HISFV_RESET_GPIO_BIT));
udelay(200000);
/* then,cancel reset,and should delay 200ms */
val = __raw_readb(HISFV_RESET_GPIO_BASE + HISFV_RESET_GPIO_DIR);
val |= (HISFV_RESET_GPIO_DIR_OUT << HISFV_RESET_GPIO_BIT);
__raw_writeb(val, HISFV_RESET_GPIO_BASE + HISFV_RESET_GPIO_DIR);
__raw_writeb(((!HISFV_RESET_GPIO_DATA) << HISFV_RESET_GPIO_BIT),
HISFV_RESET_GPIO_BASE +
(4 << HISFV_RESET_GPIO_BIT));
udelay(20000);
# endif
}
}
int arch_usb_init(void)
{
unsigned int reg;
if (_HI3712_V100 == get_chipid()) {
int timeout;
reg = readl(HI3712_USB_PERI_USB0);
reg |= HI3712_USB_ULPI_BYPASS_EN;
reg |= HI3712_USB_WORDINTERFACE;
reg &= ~(HI3712_USB_SS_BURST16_EN);
reg &= ~(HI3712_USB_ATERESET1);
reg &= ~(HI3712_USB_ATERESETX);
writel(reg, HI3712_USB_PERI_USB0);
udelay(100);
reg = readl(HI3712_USB_PREI_USB1);
reg |= HI3712_USB_FREECLK0_INV_EN;
writel(reg, HI3712_USB_PREI_USB1);
udelay(100);
reg = readl(HI3712_PERI_CRG36);
reg |= HI3712_USB_BRG_CKEN;
reg |= HI3712_USB_OTG_CKEN;
reg |= HI3712_USB_HOST_CKEN;
reg |= HI3712_USB1_CKEN;
reg |= HI3712_USB0_CKEN;
writel(reg, HI3712_PERI_CRG36);
udelay(100);
timeout = 0x10;
do {
reg = readl(HI3712_PERI_CRG36);
reg |= HI3712_USBPHY0_REQ;
reg |= HI3712_USBPHY1_REQ;
writel(reg, HI3712_PERI_CRG36);
udelay(100);
reg &= ~(HI3712_USBPHY0_REQ);
reg &= ~(HI3712_USBPHY1_REQ);
writel(reg, HI3712_PERI_CRG36);
udelay(100);
reg = readl(HI3712_PERI_USB3);
switch (get_cpu_version(NULL)) {
case _HI3712_V100A:
if (reg & HI3712_USBPHY0_CLK_TEST)
timeout = -1;
break;
default:
case _HI3712_V100I:
if ((reg & HI3712_USBPHY0_CLK_TEST)
&& (reg & HI3712_USBPHY1_CLK_TEST))
timeout = -1;
break;
}
} while (timeout-- > 0);
if (!timeout) {
DBG_BUG(("Usb phy initialize timeout.\n"));
}
udelay(100);
reg = readl(HI3712_USB_PERI_USB0);
reg |= HI3712_USB_ATERESETX;
udelay(100);
reg &= ~(HI3712_USB_ATERESETX);
writel(reg, HI3712_USB_PERI_USB0);
udelay(100);
reg = readl(HI3712_PERI_CRG36);
reg &= ~(HI3712_USB_BRG_SRST_REQ);
reg &= ~(HI3712_UTMI1_HOST_REQ);
reg &= ~(HI3712_UTMI0_HOST_REQ);
reg &= ~(HI3712_USBPHY1_TREQ);
reg &= ~(HI3712_USBPHY0_TREQ);
reg &= ~(HI3712_USB_OTG_REQ);
reg &= ~(HI3712_USB_HOST_REQ);
reg &= ~(HI3712_USB_OTG_SRST_REQ);
reg &= ~(HI3712_USB_HOST_SRST_REQ);
writel(reg, HI3712_PERI_CRG36);
udelay(100);
} else {
reg = readl(HI3716X_PERI_CRG36);
reg |= HI3716X_USB_CKEN;
reg |= HI3716X_USBPHY_REQ;
reg &= ~(HI3716X_USBPHY_PORT1_TREQ);
reg &= ~(HI3716X_USBPHY_PORT0_TREQ);
reg |= HI3716X_USB_CTRL_UTMI1_REG;
reg |= HI3716X_USB_CTRL_UTMI0_REG;
reg |= HI3716X_USB_AHB_SRST_REQ;
writel(reg, HI3716X_PERI_CRG36);
udelay(20);
reg = readl(HI3716X_USB_PERI_USB0);
reg |= HI3716X_USB_ULPI_BYPASS_EN;
reg &= ~(HI3716X_USB_WORDINTERFACE);
reg &= ~(HI3716X_USB_SS_BURST16_EN);
writel(reg, HI3716X_USB_PERI_USB0);
udelay(100);
reg = readl(HI3716X_PERI_CRG36);
reg &= ~(HI3716X_USBPHY_REQ);
writel(reg, HI3716X_PERI_CRG36);
udelay(100);
reg = readl(HI3716X_PERI_CRG36);
reg &= ~(HI3716X_USB_CTRL_UTMI1_REG);
reg &= ~(HI3716X_USB_CTRL_UTMI0_REG);
reg &= ~(HI3716X_USB_CTRL_HUB_REG);
reg &= ~(HI3716X_USB_AHB_SRST_REQ);
writel(reg, HI3716X_PERI_CRG36);
udelay(10);
WDG_ENABLE(0x5DC0);
readl(0x60070000);
WDG_DISABLE();
}
return 0;
}
static int
cpustat(void)
{
cpc_setgrp_t *accum;
cpc_set_t *start;
int c, i, retval;
int lwps = 0;
psetid_t mypset, cpupset;
char *errstr;
cpc_buf_t **data1, **data2, **scratch;
int nreqs;
kstat_ctl_t *kc;
ncpus = (int)sysconf(_SC_NPROCESSORS_CONF);
if ((gstate = calloc(ncpus, sizeof (*gstate))) == NULL) {
(void) fprintf(stderr, gettext(
"%s: out of heap\n"), opts->pgmname);
return (1);
}
max_chip_id = sysconf(_SC_CPUID_MAX);
if ((chip_designees = malloc(max_chip_id * sizeof (int))) == NULL) {
(void) fprintf(stderr, gettext(
"%s: out of heap\n"), opts->pgmname);
return (1);
}
for (i = 0; i < max_chip_id; i++)
chip_designees[i] = -1;
if (smt) {
if ((kc = kstat_open()) == NULL) {
(void) fprintf(stderr, gettext(
"%s: kstat_open() failed: %s\n"), opts->pgmname,
strerror(errno));
return (1);
}
}
if (opts->dosoaker)
if (priocntl(0, 0, PC_GETCID, &fxinfo) == -1) {
(void) fprintf(stderr, gettext(
"%s: couldn't get FX scheduler class: %s\n"),
opts->pgmname, strerror(errno));
return (1);
}
/*
* Only include processors that are participating in the system
*/
for (c = 0, i = 0; i < ncpus; c++) {
switch (p_online(c, P_STATUS)) {
case P_ONLINE:
case P_NOINTR:
if (smt) {
gstate[i].chip_id = get_chipid(kc, c);
if (gstate[i].chip_id != -1 &&
chip_designees[gstate[i].chip_id] == -1)
chip_designees[gstate[i].chip_id] = c;
}
gstate[i++].cpuid = c;
break;
case P_OFFLINE:
case P_POWEROFF:
case P_FAULTED:
case P_SPARE:
gstate[i++].cpuid = -1;
break;
default:
gstate[i++].cpuid = -1;
(void) fprintf(stderr,
gettext("%s: cpu%d in unknown state\n"),
opts->pgmname, c);
break;
case -1:
break;
}
}
/*
* Examine the processor sets; if we're in one, only attempt
* to report on the set we're in.
*/
if (pset_bind(PS_QUERY, P_PID, P_MYID, &mypset) == -1) {
errstr = strerror(errno);
(void) fprintf(stderr, gettext("%s: pset_bind - %s\n"),
opts->pgmname, errstr);
} else {
for (i = 0; i < ncpus; i++) {
struct tstate *this = &gstate[i];
if (this->cpuid == -1)
continue;
if (pset_assign(PS_QUERY,
this->cpuid, &cpupset) == -1) {
errstr = strerror(errno);
(void) fprintf(stderr,
gettext("%s: pset_assign - %s\n"),
opts->pgmname, errstr);
continue;
}
if (mypset != cpupset)
this->cpuid = -1;
}
}
if (opts->dotitle)
print_title(opts->master);
zerotime();
for (i = 0; i < ncpus; i++) {
struct tstate *this = &gstate[i];
if (this->cpuid == -1)
continue;
this->sgrp = cpc_setgrp_clone(opts->master);
if (this->sgrp == NULL) {
this->cpuid = -1;
continue;
}
if (thr_create(NULL, 0, gtick, this,
THR_BOUND|THR_NEW_LWP, &this->tid) == 0)
lwps++;
else {
(void) fprintf(stderr,
gettext("%s: cannot create thread for cpu%d\n"),
opts->pgmname, this->cpuid);
this->status = 4;
}
}
if (lwps != 0)
for (i = 0; i < ncpus; i++)
(void) thr_join(gstate[i].tid, NULL, NULL);
if ((accum = cpc_setgrp_clone(opts->master)) == NULL) {
(void) fprintf(stderr, gettext("%s: out of heap\n"),
opts->pgmname);
return (1);
}
retval = 0;
for (i = 0; i < ncpus; i++) {
struct tstate *this = &gstate[i];
if (this->cpuid == -1)
continue;
cpc_setgrp_accum(accum, this->sgrp);
cpc_setgrp_free(this->sgrp);
this->sgrp = NULL;
if (this->status != 0)
retval = 1;
}
cpc_setgrp_reset(accum);
start = cpc_setgrp_getset(accum);
do {
nreqs = cpc_setgrp_getbufs(accum, &data1, &data2, &scratch);
print_total(lwps, *data1, nreqs, cpc_setgrp_getname(accum));
} while (cpc_setgrp_nextset(accum) != start);
cpc_setgrp_free(accum);
accum = NULL;
free(gstate);
return (retval);
}
void mshci_hi_set_ios(struct mshci_host *ms_host, struct mmc_ios *ios)
{
struct himci_host * hi_host = (struct himci_host *)(ms_host->private);
int ret = -1;
hi_host_trace(HIMCI_TRACE_GEN_API, "++");
himci_assert(ios);
himci_assert(hi_host);
hi_host_trace(HIMCI_TRACE_GEN_INFO, "ios->power_mode = %d ", ios->power_mode);
hi_host_trace(HIMCI_TRACE_GEN_INFO, "ios->clock = %d ", ios->clock);
hi_host_trace(HIMCI_TRACE_GEN_INFO, "ios->bus_width = %d ", ios->bus_width);
hi_host_trace(HIMCI_TRACE_GEN_INFO, "ios->timing = %d ", ios->timing);
/* process power */
if (hi_host->old_power_mode != ios->power_mode) {
switch (ios->power_mode) {
case MMC_POWER_OFF:
hi_host_trace(HIMCI_TRACE_SIGNIFICANT, "set io to lowpower");
if (hi_host->vcc) {
regulator_disable(hi_host->vcc);
}
if (hi_host->signal_vcc) {
regulator_disable(hi_host->signal_vcc);
regulator_set_mode(hi_host->signal_vcc, REGULATOR_MODE_IDLE);
}
ret = blockmux_set(hi_host->piomux_block, hi_host->pblock_config, LOWPOWER);
if (ret) {
himci_error("failed to blockmux_set");
}
break;
case MMC_POWER_UP:
hi_host_trace(HIMCI_TRACE_SIGNIFICANT, "set io to normal");
ret = blockmux_set(hi_host->piomux_block, hi_host->pblock_config, NORMAL);
if (ret) {
himci_error("failed to blockmux_set");
}
if (hi_host->vcc) {
ret = regulator_set_voltage(hi_host->vcc, 2850000, 2850000);
if (ret != 0) {
himci_error("failed to regulator_set_voltage");
}
ret = regulator_enable(hi_host->vcc);
if (ret) {
himci_error("failed to regulator_enable");
}
}
if (hi_host->signal_vcc) {
ret = regulator_set_voltage(hi_host->signal_vcc, 2600000, 2600000);
if (ret != 0) {
himci_error("failed to regulator_set_voltage");
}
regulator_set_mode(hi_host->signal_vcc, REGULATOR_MODE_NORMAL);
ret = regulator_enable(hi_host->signal_vcc);
if (ret) {
himci_error("failed to regulator_enable");
}
}
break;
case MMC_POWER_ON:
break;
default:
himci_error("unknown power supply mode");
break;
}
hi_host->old_power_mode = ios->power_mode;
}
/* process timing */
if (hi_host->old_timing != ios->timing) {
hi_host->old_timing = ios->timing;
if ( get_chipid() == DI_CHIP_ID ) {
mshci_hi_update_timing(ms_host, 0);
switch (ios->timing) {
case MMC_TIMING_LEGACY:
if (hi_host->pdev->id == 1) {
/* 2 division, 40M */
writel((0x1<<6) | (0x7<<22),
IO_ADDRESS(REG_BASE_SCTRL) + REG_SCCLKDIV2);
ms_host->max_clk = 40*1000*1000;
ms_host->clock++;
} else if (hi_host->pdev->id == 0) {
/* 2 division, 40M */
writel((0x0<<5) | (0x1<<21),
IO_ADDRESS(REG_BASE_SCTRL) + REG_SCCLKDIV2);
ms_host->max_clk = 40*1000*1000;
ms_host->clock++;
}
hi_host_trace(HIMCI_TRACE_SIGNIFICANT, "MMC_TIMING_LEGACY");
break;
case MMC_TIMING_UHS_DDR50:
if (hi_host->pdev->id == 1) {
/* 1 division, 80M */
writel((0x0<<6) | (0x7<<22),
IO_ADDRESS(REG_BASE_SCTRL) + REG_SCCLKDIV2);
ms_host->max_clk = 80*1000*1000;
ms_host->clock++;
} else {
#if 0
/*
* m53980:
* debug purpose.
* change clock via sctrl configuration
*/
printk("clk div a:0x%x\n", readl(IO_ADDRESS(REG_BASE_SCTRL) + REG_SCCLKDIV2));
writel((0x7)|(0xF<<16), IO_ADDRESS(REG_BASE_SCTRL) + REG_SCCLKDIV2);
printk("clk div b:0x%x\n", readl(IO_ADDRESS(REG_BASE_SCTRL) + REG_SCCLKDIV2));
#endif
}
hi_host_trace(HIMCI_TRACE_SIGNIFICANT, "MMC_TIMING_UHS_DDR50");
break;
case MMC_TIMING_UHS_SDR50:
if (hi_host->pdev->id == 0) {
writel((0x1<<5) | (0x1<<21),
IO_ADDRESS(REG_BASE_SCTRL) + REG_SCCLKDIV2);
ms_host->max_clk = 80*1000*1000;
ms_host->clock++;
}
hi_host_trace(HIMCI_TRACE_SIGNIFICANT, "MMC_TIMING_UHS_SDR50");
break;
default:
break;
}
} else {
ret = clk_set_rate(hi_host->pclk,hi_host->init_tuning_config[0 + (ios->timing + 1) * TUNING_INIT_CONFIG_NUM]);
if (ret) {
himci_error("failed to clk_set_rate");
}
hi_host->tuning_init_sample =
(hi_host->init_tuning_config[3 + (ios->timing + 1) * TUNING_INIT_CONFIG_NUM] +
hi_host->init_tuning_config[4 + (ios->timing + 1) * TUNING_INIT_CONFIG_NUM]) / 2;
mshci_hi_set_timing(hi_host,
hi_host->tuning_init_sample,
hi_host->init_tuning_config[2 + (ios->timing + 1) * TUNING_INIT_CONFIG_NUM],
hi_host->init_tuning_config[1 + (ios->timing + 1) * TUNING_INIT_CONFIG_NUM]);
ms_host->max_clk = hi_host->init_tuning_config[5 + (ios->timing + 1) * TUNING_INIT_CONFIG_NUM];
ms_host->clock++;
}
}
hi_host_trace(HIMCI_TRACE_GEN_API, "--");
}
static void hieth_phy_reset(void)
{
unsigned long flags;
unsigned int val;
long long chipid;
chipid = get_chipid();
if (chipid == _HI3712_V100) {
unsigned int old;
local_irq_save(flags);
/* config pin re-use to miirst */
old = val = readl(HI3712_ETH_GPIO_BASE + HI3712_ETH_GPIO_REG);
val |= 0x1;
writel(val, HI3712_ETH_GPIO_BASE + HI3712_ETH_GPIO_REG);
/* do phy reset */
val = readl(HIETH_SYSREG_BASE + HIETH_SYSREG_REG);
val |= HI3712_ETH_SYSREG_RST_BIT;
writel(val, HIETH_SYSREG_BASE + HIETH_SYSREG_REG);
local_irq_restore(flags);
msleep(20);
local_irq_save(flags);
val = readl(HIETH_SYSREG_BASE + HIETH_SYSREG_REG);
val &= ~HI3712_ETH_SYSREG_RST_BIT;
writel(val, HIETH_SYSREG_BASE + HIETH_SYSREG_REG);
local_irq_restore(flags);
msleep(20);
/* restore pin re-use to old value */
writel(old, HI3712_ETH_GPIO_BASE + HI3712_ETH_GPIO_REG);
} else if (chipid == _HI3716M_V300) {
unsigned int old;
local_irq_save(flags);
/* config pin re-use to miirst */
old = val =
readl(HI3716MV300_ETH_GPIO_BASE + HI3716MV300_ETH_GPIO_REG);
val |= 0x1;
writel(val,
HI3716MV300_ETH_GPIO_BASE + HI3716MV300_ETH_GPIO_REG);
/* do phy reset */
val = readl(HIETH_SYSREG_BASE + HIETH_SYSREG_REG);
val |= HI3716MV300_ETH_SYSREG_RST_BIT;
writel(val, HIETH_SYSREG_BASE + HIETH_SYSREG_REG);
local_irq_restore(flags);
msleep(20);
local_irq_save(flags);
val = readl(HIETH_SYSREG_BASE + HIETH_SYSREG_REG);
val &= ~HI3716MV300_ETH_SYSREG_RST_BIT;
writel(val, HIETH_SYSREG_BASE + HIETH_SYSREG_REG);
local_irq_restore(flags);
msleep(20);
/* restore pin re-use to old value */
writel(old,
HI3716MV300_ETH_GPIO_BASE + HI3716MV300_ETH_GPIO_REG);
} else {
# ifdef CONFIG_HIETH_RESET_HELPER_EN
local_irq_save(flags);
/*gpiox[x] set to reset, then sleep 200ms */
val =
readb(IO_ADDRESS(CONFIG_HIETH_RESET_HELPER_GPIO_BASE) +
0x400);
val |= (1 << CONFIG_HIETH_RESET_HELPER_GPIO_BIT);
writeb(val,
IO_ADDRESS(CONFIG_HIETH_RESET_HELPER_GPIO_BASE) + 0x400);
writeb(0, (IO_ADDRESS(CONFIG_HIETH_RESET_HELPER_GPIO_BASE)
+ (4 << CONFIG_HIETH_RESET_HELPER_GPIO_BIT)));
local_irq_restore(flags);
msleep(200);
local_irq_save(flags);
/*then,cancel reset,and should sleep 50ms */
val =
readb(IO_ADDRESS(CONFIG_HIETH_RESET_HELPER_GPIO_BASE) +
0x400);
val |= (1 << CONFIG_HIETH_RESET_HELPER_GPIO_BIT);
writeb(val,
IO_ADDRESS(CONFIG_HIETH_RESET_HELPER_GPIO_BASE) + 0x400);
writeb((1 << (CONFIG_HIETH_RESET_HELPER_GPIO_BIT)),
(IO_ADDRESS(CONFIG_HIETH_RESET_HELPER_GPIO_BASE)
+ (4 << CONFIG_HIETH_RESET_HELPER_GPIO_BIT)));
local_irq_restore(flags);
msleep(50);
# endif
}
}
