static void enable_dev(device_t dev)
{
printk(BIOS_SPEW, "----------\n%s/%s ( %s ), type: %d\n",
__FILE__, __func__,
dev_name(dev), dev->path.type);
printk(BIOS_SPEW, "vendor: 0x%04x. device: 0x%04x\n",
pci_read_config16(dev, PCI_VENDOR_ID),
pci_read_config16(dev, PCI_DEVICE_ID));
printk(BIOS_SPEW, "class: 0x%02x %s\n"
"subclass: 0x%02x %s\n"
"prog: 0x%02x\n"
"revision: 0x%02x\n",
pci_read_config16(dev, PCI_CLASS_DEVICE) >> 8,
get_pci_class_name(dev),
pci_read_config16(dev, PCI_CLASS_DEVICE) & 0xff,
get_pci_subclass_name(dev),
pci_read_config8(dev, PCI_CLASS_PROG),
pci_read_config8(dev, PCI_REVISION_ID));
/* Set the operations if it is a special bus type */
if (dev->path.type == DEVICE_PATH_DOMAIN) {
dev->ops = &pci_domain_ops;
} else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) {
dev->ops = &cpu_bus_ops;
} else if (dev->path.type == DEVICE_PATH_PCI) {
/* Handle south cluster enablement. */
if (PCI_SLOT(dev->path.pci.devfn) > GFX_DEV &&
(dev->ops == NULL || dev->ops->enable == NULL)) {
southcluster_enable_dev(dev);
}
}
}
static void lpss_init(device_t dev)
{
struct soc_intel_braswell_config *config = dev->chip_info;
int iosf_reg, nvs_index;
printk(BIOS_SPEW, "%s/%s ( %s )\n",
__FILE__, __func__, dev_name(dev));
printk(BIOS_SPEW, "%s - %s\n",
get_pci_class_name(dev),
get_pci_subclass_name(dev));
dev_ctl_reg(dev, &iosf_reg, &nvs_index);
if (iosf_reg < 0) {
int slot = PCI_SLOT(dev->path.pci.devfn);
int func = PCI_FUNC(dev->path.pci.devfn);
printk(BIOS_DEBUG, "Could not find iosf_reg for %02x.%01x\n",
slot, func);
return;
}
i2c_disable_resets(dev);
if (config->lpss_acpi_mode)
dev_enable_acpi_mode(dev, iosf_reg, nvs_index);
}
