static void get_args(int argc, char *argv[])
{
u32 i;
if (argc != 9 && argc != 10)
fail("usage: makeself [-c] [type] [version suffix] [version] [vendor id] [auth id] [sdk type] [elf] [self]");
i = 1;
if (argc == 10) {
if (strcmp(argv[1], "-c") != 0)
fail("invalid option: %s", argv[1]);
compression = 1;
i++;
}
get_type(argv[i++]);
get_keys(argv[i++]);
get_version(argv[i++]);
get_vendor(argv[i++]);
get_auth(argv[i++]);
get_sdktype(argv[i++]);
elf_name = argv[i++];
self_name = argv[i++];
if (compression) {
if (type == KEY_ISO)
fail("no compression support for isolated modules");
if (type == KEY_LDR)
fail("no compression support for secure loaders");
}
}
/*
* Print adapter configuration information
*
* Arguments:
* si pointer to a struct air_cfg_rsp
*
* Returns:
* none
*
*/
void
print_cfg_info(struct air_cfg_rsp *si)
{
const char *adapter, *bus, *media, *vendor;
/*
* Print a header if it hasn't been done yet.
*/
if (!cfg_hdr) {
printf(CFG_HDR);
cfg_hdr = 1;
}
/*
* Format the vendor name and adapter type
*/
vendor = get_vendor(si->acp_vendor);
adapter = get_adapter(si->acp_device);
/*
* Format the communications medium
*/
media = get_media_type(si->acp_media);
bus = get_bus_type(si->acp_bustype);
/*
* Print the ARP server information
*/
printf("%-8s %-8s %-8s %-14s %-4s %ld\n",
si->acp_intf,
vendor,
adapter,
media,
bus,
si->acp_serial);
printf(" MAC address = %s\n",
format_mac_addr(&si->acp_macaddr));
printf(" Hardware version = %s\n", si->acp_hard_vers);
printf(" Firmware version = %s\n", si->acp_firm_vers);
}
static gotoblas_t *get_coretype(void){
int eax, ebx, ecx, edx;
int family, exfamily, model, vendor, exmodel;
cpuid(1, &eax, &ebx, &ecx, &edx);
family = BITMASK(eax, 8, 0x0f);
exfamily = BITMASK(eax, 20, 0xff);
model = BITMASK(eax, 4, 0x0f);
exmodel = BITMASK(eax, 16, 0x0f);
vendor = get_vendor();
if (vendor == VENDOR_INTEL){
switch (family) {
case 0x6:
switch (exmodel) {
case 0:
if (model <= 0x7) return &gotoblas_KATMAI;
if ((model == 0x8) || (model == 0xa) || (model == 0xb)) return &gotoblas_COPPERMINE;
if ((model == 0x9) || (model == 0xd)) return &gotoblas_BANIAS;
if (model == 14) return &gotoblas_BANIAS;
if (model == 15) return &gotoblas_CORE2;
return NULL;
case 1:
if (model == 6) return &gotoblas_CORE2;
if (model == 7) return &gotoblas_PENRYN;
if (model == 13) return &gotoblas_DUNNINGTON;
if ((model == 10) || (model == 11) || (model == 14) || (model == 15)) return &gotoblas_NEHALEM;
if (model == 12) return &gotoblas_ATOM;
return NULL;
case 2:
//Intel Core (Clarkdale) / Core (Arrandale)
// Pentium (Clarkdale) / Pentium Mobile (Arrandale)
// Xeon (Clarkdale), 32nm
if (model == 5) return &gotoblas_NEHALEM;
//Intel Xeon Processor 5600 (Westmere-EP)
//Xeon Processor E7 (Westmere-EX)
//Xeon E7540
if (model == 12 || model == 14 || model == 15) return &gotoblas_NEHALEM;
//Intel Core i5-2000 /i7-2000 (Sandy Bridge)
//Intel Core i7-3000 / Xeon E5
if (model == 10 || model == 13) {
if(support_avx())
return &gotoblas_SANDYBRIDGE;
else{
fprintf(stderr, "OpenBLAS : Your OS does not support AVX instructions. OpenBLAS is using Nehalem kernels as a fallback, which may give poorer performance.\n");
return &gotoblas_NEHALEM; //OS doesn't support AVX. Use old kernels.
}
}
return NULL;
case 3:
//Intel Sandy Bridge 22nm (Ivy Bridge?)
if (model == 10) {
if(support_avx())
return &gotoblas_SANDYBRIDGE;
else{
fprintf(stderr, "OpenBLAS : Your OS does not support AVX instructions. OpenBLAS is using Nehalem kernels as a fallback, which may give poorer performance.\n");
return &gotoblas_NEHALEM; //OS doesn't support AVX. Use old kernels.
}
}
//Intel Haswell
if (model == 12) {
if(support_avx())
return &gotoblas_HASWELL;
else{
fprintf(stderr, "OpenBLAS : Your OS does not support AVX instructions. OpenBLAS is using Nehalem kernels as a fallback, which may give poorer performance.\n");
return &gotoblas_NEHALEM; //OS doesn't support AVX. Use old kernels.
}
}
return NULL;
case 4:
//Intel Haswell
if (model == 5) {
if(support_avx())
return &gotoblas_HASWELL;
else{
fprintf(stderr, "OpenBLAS : Your OS does not support AVX instructions. OpenBLAS is using Nehalem kernels as a fallback, which may give poorer performance.\n");
return &gotoblas_NEHALEM; //OS doesn't support AVX. Use old kernels.
}
}
return NULL;
}
case 0xf:
if (model <= 0x2) return &gotoblas_NORTHWOOD;
return &gotoblas_PRESCOTT;
}
}
if (vendor == VENDOR_AMD){
if (family <= 0xe) return &gotoblas_ATHLON;
if (family == 0xf){
if ((exfamily == 0) || (exfamily == 2)) {
if (ecx & (1 << 0)) return &gotoblas_OPTERON_SSE3;
else return &gotoblas_OPTERON;
} else if (exfamily == 5) {
return &gotoblas_BOBCAT;
} else if (exfamily == 6) {
//AMD Bulldozer Opteron 6200 / Opteron 4200 / AMD FX-Series
if(support_avx())
return &gotoblas_BULLDOZER;
else{
fprintf(stderr, "OpenBLAS : Your OS does not support AVX instructions. OpenBLAS is using Barcelona kernels as a fallback, which may give poorer performance.\n");
return &gotoblas_BARCELONA; //OS doesn't support AVX. Use old kernels.
}
} else {
return &gotoblas_BARCELONA;
}
}
}
if (vendor == VENDOR_CENTAUR) {
switch (family) {
case 0x6:
return &gotoblas_NANO;
break;
}
}
return NULL;
}
// returns an OpenCL error num or zero
//
int boinc_get_opencl_ids_aux(
char* type, int opencl_device_index, int device_num,
cl_device_id* device, cl_platform_id* platform
) {
cl_platform_id platforms[MAX_OPENCL_PLATFORMS];
cl_uint num_platforms, platform_index, num_devices;
cl_device_id devices[MAX_COPROC_INSTANCES];
char vendor[256]; // Device vendor (NVIDIA, ATI, AMD, etc.)
int retval = 0;
cl_device_id device_id;
int device_num_for_type = -1;
int device_index;
if ((!type) || (!strlen(type))) return CL_DEVICE_NOT_FOUND;
retval = clGetPlatformIDs(MAX_OPENCL_PLATFORMS, platforms, &num_platforms);
if (num_platforms == 0) return CL_DEVICE_NOT_FOUND;
if (retval != CL_SUCCESS) return retval;
for (platform_index=0; platform_index<num_platforms; ++platform_index) {
retval = clGetDeviceIDs(
platforms[platform_index], CL_DEVICE_TYPE_GPU,
MAX_COPROC_INSTANCES, devices, &num_devices
);
if (retval != CL_SUCCESS) continue;
// Use gpu_opencl_dev_index if available
if (opencl_device_index >= 0) {
if (opencl_device_index < (int)num_devices) {
device_id = devices[opencl_device_index];
retval = get_vendor(device_id, vendor);
if (retval != CL_SUCCESS) continue;
if (!strcmp(vendor, type)) {
*device = device_id;
*platform = platforms[platform_index];
return 0;
}
}
continue;
}
// Older versions of init_data.xml don't have gpu_opencl_dev_index field
// NOTE: This may return the wrong device on older versions of BOINC if
// OpenCL does not recognize all GPU models detected by CUDA
for (device_index=0; device_index<(int)num_devices; ++device_index) {
device_id = devices[device_index];
retval = get_vendor(device_id, vendor);
if (retval != CL_SUCCESS) continue;
if (!strcmp(vendor, type)) {
if(++device_num_for_type == device_num) {
*device = device_id;
*platform = platforms[platform_index];
return 0;
}
}
}
}
return CL_DEVICE_NOT_FOUND;
}
int main(int argc, char *argv[])
{
FILE *fp;
u8 bfr[ALIGNMENT];
if (argc != 9)
fail("usage: makeself [type] [version suffix] [version] [vendor id] [auth id] [sdk type] [elf] [self]");
get_type(argv[1]);
get_keys(argv[2]);
get_version(argv[3]);
get_vendor(argv[4]);
get_auth(argv[5]);
get_sdktype(argv[6]);
elf_size = get_filesize(argv[7]);
elf = mmap_file(argv[7]);
parse_elf();
meta_header_size = 0x80 + ehdr.e_phnum * (0x30 + 0x20 + 0x60) + 0x30;
info_offset = 0x70;
elf_offset = 0x90;
phdr_offset = elf_offset + ehdr.e_ehsize;
sec_offset = round_up(phdr_offset + ehdr.e_phentsize * ehdr.e_phnum, ALIGNMENT);
version_offset = round_up(sec_offset + ehdr.e_phnum * 0x20, ALIGNMENT);
ctrl_offset = round_up(version_offset + 0x10, ALIGNMENT);
meta_offset = round_up(ctrl_offset + 0x70, ALIGNMENT);
header_size = round_up(meta_offset + meta_header_size, 0x80);
shdr_offset = ehdr.e_shoff + header_size;
build_sce_hdr();
build_info_hdr();
build_ctrl_hdr();
build_sec_hdr();
build_version_hdr();
build_meta_hdr();
self = malloc(header_size + elf_size);
memset(self, 0, header_size + elf_size);
build_hdr();
calculate_hashes();
sign_hdr();
sce_encrypt_data(self);
sce_encrypt_header(self, &ks);
fp = fopen(argv[8], "wb");
if (fp == NULL)
fail("fopen(%s) failed", argv[4]);
if (fwrite(self, header_size + elf_size, 1, fp) != 1)
fail("unable to write self");
memset(bfr, 0, sizeof bfr);
fwrite(bfr, round_up(elf_size, ALIGNMENT) - elf_size, 1, fp);
fclose(fp);
return 0;
}
/**
* find_set_nic_lib() - Match the NIC library to the NIC
* @param nic - NIC device to determine which NIC library to use
* @return 0 on success <0 on failure
*/
int find_set_nic_lib(nic_t *nic)
{
uint32_t vendor;
uint32_t subvendor;
uint32_t device;
uint32_t subdevice;
uint32_t pci_bus;
uint32_t pci_slot;
uint32_t pci_func;
int rc = 0;
nic_lib_handle_t *handle;
struct pci_device_id *pci_entry;
size_t name_size;
rc = get_vendor(nic, &vendor);
if (rc != 0) {
LOG_ERR(PFX "%s: Could not get vendor id [0x%x]",
nic->log_name, rc);
return rc;
}
rc = get_subvendor(nic, &subvendor);
if (rc != 0) {
LOG_ERR(PFX "%s: Could not get subvendor id [0x%x]",
nic->log_name, rc);
return rc;
}
rc = get_device(nic, &device);
if (rc != 0) {
LOG_ERR(PFX "%s: Could not get device id [0x%x]",
nic->log_name, rc);
return rc;
}
rc = get_subdevice(nic, &subdevice);
if (rc != 0) {
LOG_ERR(PFX "%s: Could not get subdevice id [0x%x]",
nic->log_name, rc);
return rc;
}
get_bus_slot_func_num(nic, &pci_bus, &pci_slot, &pci_func);
LOG_DEBUG(PFX "%s: Looking for device vendor: "
"0x%x subvendor: 0x%x device: 0x%x subdevice: 0x%x",
nic->log_name, vendor, subvendor, device, subdevice);
rc = find_nic_lib_using_pci_id(vendor, device, subvendor, subdevice,
&handle, &pci_entry);
if (rc != 0) {
LOG_WARN(PFX "%s: Couldn't find proper NIC library",
nic->log_name);
return rc;
}
nic->nic_library = handle;
nic->pci_id = pci_entry;
/* Prepare the NIC library op table */
nic->ops = handle->ops;
(*nic->ops->lib_ops.get_library_name) (&nic->library_name, &name_size);
return 0;
}
int get_cpuname(void){
int family, exfamily, model, vendor, exmodel;
if (!have_cpuid()) return CPUTYPE_80386;
family = get_cputype(GET_FAMILY);
exfamily = get_cputype(GET_EXFAMILY);
model = get_cputype(GET_MODEL);
exmodel = get_cputype(GET_EXMODEL);
vendor = get_vendor();
if (vendor == VENDOR_INTEL){
switch (family) {
case 0x4:
return CPUTYPE_80486;
case 0x5:
return CPUTYPE_PENTIUM;
case 0x6:
switch (exmodel) {
case 0:
switch (model) {
case 1:
case 3:
case 5:
case 6:
return CPUTYPE_PENTIUM2;
case 7:
case 8:
case 10:
case 11:
return CPUTYPE_PENTIUM3;
case 9:
case 13:
case 14:
return CPUTYPE_PENTIUMM;
case 15:
return CPUTYPE_CORE2;
}
break;
case 1:
switch (model) {
case 6:
return CPUTYPE_CORE2;
case 7:
return CPUTYPE_PENRYN;
case 10:
case 11:
case 14:
case 15:
return CPUTYPE_NEHALEM;
case 12:
return CPUTYPE_ATOM;
case 13:
return CPUTYPE_DUNNINGTON;
}
break;
case 2:
switch (model) {
case 5:
//Intel Core (Clarkdale) / Core (Arrandale)
// Pentium (Clarkdale) / Pentium Mobile (Arrandale)
// Xeon (Clarkdale), 32nm
return CPUTYPE_NEHALEM;
case 10:
//Intel Core i5-2000 /i7-2000 (Sandy Bridge)
if(support_avx())
return CPUTYPE_SANDYBRIDGE;
else
return CPUTYPE_NEHALEM; //OS doesn't support AVX
case 12:
//Xeon Processor 5600 (Westmere-EP)
return CPUTYPE_NEHALEM;
case 13:
//Intel Core i7-3000 / Xeon E5 (Sandy Bridge)
if(support_avx())
return CPUTYPE_SANDYBRIDGE;
else
return CPUTYPE_NEHALEM;
case 15:
//Xeon Processor E7 (Westmere-EX)
return CPUTYPE_NEHALEM;
}
break;
case 3:
switch (model) {
case 10:
if(support_avx())
return CPUTYPE_SANDYBRIDGE;
else
return CPUTYPE_NEHALEM;
}
break;
}
break;
case 0x7:
return CPUTYPE_ITANIUM;
case 0xf:
switch (exfamily) {
case 0 :
return CPUTYPE_PENTIUM4;
case 1 :
return CPUTYPE_ITANIUM;
}
break;
}
return CPUTYPE_INTEL_UNKNOWN;
}
if (vendor == VENDOR_AMD){
switch (family) {
case 0x4:
return CPUTYPE_AMD5X86;
case 0x5:
return CPUTYPE_AMDK6;
case 0x6:
return CPUTYPE_ATHLON;
case 0xf:
switch (exfamily) {
case 0:
case 2:
return CPUTYPE_OPTERON;
case 1:
case 10:
case 6: //AMD Bulldozer Opteron 6200 / Opteron 4200 / AMD FX-Series
return CPUTYPE_BARCELONA;
case 5:
return CPUTYPE_BOBCAT;
}
break;
}
return CPUTYPE_AMD_UNKNOWN;
}
if (vendor == VENDOR_CYRIX){
switch (family) {
case 0x4:
return CPUTYPE_CYRIX5X86;
case 0x5:
return CPUTYPE_CYRIXM1;
case 0x6:
return CPUTYPE_CYRIXM2;
}
return CPUTYPE_CYRIX_UNKNOWN;
}
if (vendor == VENDOR_NEXGEN){
switch (family) {
case 0x5:
return CPUTYPE_NEXGENNX586;
}
return CPUTYPE_NEXGEN_UNKNOWN;
}
if (vendor == VENDOR_CENTAUR){
switch (family) {
case 0x5:
return CPUTYPE_CENTAURC6;
break;
case 0x6:
return CPUTYPE_NANO;
break;
}
return CPUTYPE_VIAC3;
}
if (vendor == VENDOR_RISE){
switch (family) {
case 0x5:
return CPUTYPE_RISEMP6;
}
return CPUTYPE_RISE_UNKNOWN;
}
if (vendor == VENDOR_SIS){
switch (family) {
case 0x5:
return CPUTYPE_SYS55X;
}
return CPUTYPE_SIS_UNKNOWN;
}
if (vendor == VENDOR_TRANSMETA){
switch (family) {
case 0x5:
return CPUTYPE_CRUSOETM3X;
}
return CPUTYPE_TRANSMETA_UNKNOWN;
}
if (vendor == VENDOR_NSC){
switch (family) {
case 0x5:
return CPUTYPE_NSGEODE;
}
return CPUTYPE_NSC_UNKNOWN;
}
return CPUTYPE_UNKNOWN;
}
static gotoblas_t *get_coretype(void){
int eax, ebx, ecx, edx;
int family, exfamily, model, vendor, exmodel;
cpuid(1, &eax, &ebx, &ecx, &edx);
family = BITMASK(eax, 8, 0x0f);
exfamily = BITMASK(eax, 20, 0xff);
model = BITMASK(eax, 4, 0x0f);
exmodel = BITMASK(eax, 16, 0x0f);
vendor = get_vendor();
if (vendor == VENDOR_INTEL){
switch (family) {
case 0x6:
switch (exmodel) {
case 0:
if (model <= 0x7) return &gotoblas_KATMAI;
if ((model == 0x8) || (model == 0xa) || (model == 0xb)) return &gotoblas_COPPERMINE;
if ((model == 0x9) || (model == 0xd)) return &gotoblas_BANIAS;
if (model == 14) return &gotoblas_BANIAS;
if (model == 15) return &gotoblas_CORE2;
return NULL;
case 1:
if (model == 6) return &gotoblas_CORE2;
if (model == 7) return &gotoblas_PENRYN;
if (model == 13) return &gotoblas_DUNNINGTON;
if ((model == 10) || (model == 11) || (model == 14) || (model == 15)) return &gotoblas_NEHALEM;
if (model == 12) return &gotoblas_ATOM;
return NULL;
case 2:
//Intel Core (Clarkdale) / Core (Arrandale)
// Pentium (Clarkdale) / Pentium Mobile (Arrandale)
// Xeon (Clarkdale), 32nm
if (model == 5) return &gotoblas_NEHALEM;
//Intel Xeon Processor 5600 (Westmere-EP)
//Xeon Processor E7 (Westmere-EX)
//Xeon E7540
if (model == 12 || model == 14 || model == 15) return &gotoblas_NEHALEM;
//Intel Core i5-2000 /i7-2000 (Sandy Bridge)
//Intel Core i7-3000 / Xeon E5
if (model == 10 || model == 13) {
if(support_avx())
return &gotoblas_SANDYBRIDGE;
else{
openblas_warning(FALLBACK_VERBOSE, NEHALEM_FALLBACK);
return &gotoblas_NEHALEM; //OS doesn't support AVX. Use old kernels.
}
}
return NULL;
case 3:
//Intel Sandy Bridge 22nm (Ivy Bridge?)
if (model == 10 || model == 14) {
if(support_avx())
return &gotoblas_SANDYBRIDGE;
else{
openblas_warning(FALLBACK_VERBOSE, NEHALEM_FALLBACK);
return &gotoblas_NEHALEM; //OS doesn't support AVX. Use old kernels.
}
}
//Intel Haswell
if (model == 12 || model == 15) {
if(support_avx())
return &gotoblas_HASWELL;
else{
openblas_warning(FALLBACK_VERBOSE, NEHALEM_FALLBACK);
return &gotoblas_NEHALEM; //OS doesn't support AVX. Use old kernels.
}
}
//Intel Broadwell
if (model == 13) {
if(support_avx())
return &gotoblas_HASWELL;
else{
openblas_warning(FALLBACK_VERBOSE, NEHALEM_FALLBACK);
return &gotoblas_NEHALEM; //OS doesn't support AVX. Use old kernels.
}
}
return NULL;
case 4:
//Intel Haswell
if (model == 5 || model == 6) {
if(support_avx())
return &gotoblas_HASWELL;
else{
openblas_warning(FALLBACK_VERBOSE, NEHALEM_FALLBACK);
return &gotoblas_NEHALEM; //OS doesn't support AVX. Use old kernels.
}
}
//Intel Broadwell
if (model == 7 || model == 15) {
if(support_avx())
return &gotoblas_HASWELL;
else{
openblas_warning(FALLBACK_VERBOSE, NEHALEM_FALLBACK);
return &gotoblas_NEHALEM; //OS doesn't support AVX. Use old kernels.
}
}
//Intel Skylake
if (model == 14) {
if(support_avx())
return &gotoblas_HASWELL;
else{
openblas_warning(FALLBACK_VERBOSE, NEHALEM_FALLBACK);
return &gotoblas_NEHALEM; //OS doesn't support AVX. Use old kernels.
}
}
//Intel Avoton
if (model == 13) {
openblas_warning(FALLBACK_VERBOSE, NEHALEM_FALLBACK);
return &gotoblas_NEHALEM;
}
return NULL;
case 5:
//Intel Broadwell
if (model == 6) {
if(support_avx())
return &gotoblas_HASWELL;
else{
openblas_warning(FALLBACK_VERBOSE, NEHALEM_FALLBACK);
return &gotoblas_NEHALEM; //OS doesn't support AVX. Use old kernels.
}
}
//Intel Skylake
if (model == 14 || model == 5) {
if(support_avx())
return &gotoblas_HASWELL;
else{
openblas_warning(FALLBACK_VERBOSE, NEHALEM_FALLBACK);
return &gotoblas_NEHALEM; //OS doesn't support AVX. Use old kernels.
}
}
return NULL;
}
case 0xf:
if (model <= 0x2) return &gotoblas_NORTHWOOD;
return &gotoblas_PRESCOTT;
}
}
if (vendor == VENDOR_AMD){
if (family <= 0xe) {
// Verify that CPU has 3dnow and 3dnowext before claiming it is Athlon
cpuid(0x80000000, &eax, &ebx, &ecx, &edx);
if ( (eax & 0xffff) >= 0x01) {
cpuid(0x80000001, &eax, &ebx, &ecx, &edx);
if ((edx & (1 << 30)) == 0 || (edx & (1 << 31)) == 0)
return NULL;
}
else
return NULL;
return &gotoblas_ATHLON;
}
if (family == 0xf){
if ((exfamily == 0) || (exfamily == 2)) {
if (ecx & (1 << 0)) return &gotoblas_OPTERON_SSE3;
else return &gotoblas_OPTERON;
} else if (exfamily == 5) {
return &gotoblas_BOBCAT;
} else if (exfamily == 6) {
if(model == 1){
//AMD Bulldozer Opteron 6200 / Opteron 4200 / AMD FX-Series
if(support_avx())
return &gotoblas_BULLDOZER;
else{
openblas_warning(FALLBACK_VERBOSE, BARCELONA_FALLBACK);
return &gotoblas_BARCELONA; //OS doesn't support AVX. Use old kernels.
}
}else if(model == 2 || model == 3){
//AMD Bulldozer Opteron 6300 / Opteron 4300 / Opteron 3300
if(support_avx())
return &gotoblas_PILEDRIVER;
else{
openblas_warning(FALLBACK_VERBOSE, BARCELONA_FALLBACK);
return &gotoblas_BARCELONA; //OS doesn't support AVX. Use old kernels.
}
}else if(model == 0){
if (exmodel == 1) {
//AMD Trinity
if(support_avx())
return &gotoblas_PILEDRIVER;
else{
openblas_warning(FALLBACK_VERBOSE, BARCELONA_FALLBACK);
return &gotoblas_BARCELONA; //OS doesn't support AVX. Use old kernels.
}
}else if (exmodel == 3) {
//AMD STEAMROLLER
if(support_avx())
return &gotoblas_STEAMROLLER;
else{
openblas_warning(FALLBACK_VERBOSE, BARCELONA_FALLBACK);
return &gotoblas_BARCELONA; //OS doesn't support AVX. Use old kernels.
}
}else if (exmodel == 6) {
if(support_avx())
return &gotoblas_EXCAVATOR;
else{
openblas_warning(FALLBACK_VERBOSE, BARCELONA_FALLBACK);
return &gotoblas_BARCELONA; //OS doesn't support AVX. Use old kernels.
}
}
}
} else {
return &gotoblas_BARCELONA;
}
}
}
if (vendor == VENDOR_CENTAUR) {
switch (family) {
case 0x6:
return &gotoblas_NANO;
break;
}
}
return NULL;
}
int get_coretype(void){
int family, exfamily, model, exmodel, vendor;
if (!have_cpuid()) return CORE_80486;
family = get_cputype(GET_FAMILY);
exfamily = get_cputype(GET_EXFAMILY);
model = get_cputype(GET_MODEL);
exmodel = get_cputype(GET_EXMODEL);
vendor = get_vendor();
if (vendor == VENDOR_INTEL){
switch (family) {
case 4:
return CORE_80486;
case 5:
return CORE_P5;
case 6:
switch (exmodel) {
case 0:
switch (model) {
case 0:
case 1:
case 2:
case 3:
case 4:
case 5:
case 6:
return CORE_P6;
case 7:
return CORE_KATMAI;
case 8:
case 10:
case 11:
return CORE_COPPERMINE;
case 9:
case 13:
case 14:
return CORE_BANIAS;
case 15:
return CORE_CORE2;
}
break;
case 1:
switch (model) {
case 6:
return CORE_CORE2;
case 7:
return CORE_PENRYN;
case 10:
case 11:
case 14:
case 15:
return CORE_NEHALEM;
case 12:
return CORE_ATOM;
case 13:
return CORE_DUNNINGTON;
}
break;
case 2:
switch (model) {
case 5:
//Intel Core (Clarkdale) / Core (Arrandale)
// Pentium (Clarkdale) / Pentium Mobile (Arrandale)
// Xeon (Clarkdale), 32nm
return CORE_NEHALEM;
case 10:
//Intel Core i5-2000 /i7-2000 (Sandy Bridge)
if(support_avx())
return CORE_SANDYBRIDGE;
else
return CORE_NEHALEM; //OS doesn't support AVX
case 12:
//Xeon Processor 5600 (Westmere-EP)
return CORE_NEHALEM;
case 13:
//Intel Core i7-3000 / Xeon E5 (Sandy Bridge)
if(support_avx())
return CORE_SANDYBRIDGE;
else
return CORE_NEHALEM; //OS doesn't support AVX
case 15:
//Xeon Processor E7 (Westmere-EX)
return CORE_NEHALEM;
}
break;
case 3:
switch (model) {
case 10:
if(support_avx())
return CORE_SANDYBRIDGE;
else
return CORE_NEHALEM; //OS doesn't support AVX
}
break;
}
break;
case 15:
if (model <= 0x2) return CORE_NORTHWOOD;
else return CORE_PRESCOTT;
}
}
if (vendor == VENDOR_AMD){
if (family <= 0x5) return CORE_80486;
if (family <= 0xe) return CORE_ATHLON;
if (family == 0xf){
if ((exfamily == 0) || (exfamily == 2)) return CORE_OPTERON;
else if (exfamily == 5) return CORE_BOBCAT;
else if (exfamily == 6) return CORE_BARCELONA; //AMD Bulldozer Opteron 6200 / Opteron 4200 / AMD FX-Series
else return CORE_BARCELONA;
}
}
if (vendor == VENDOR_CENTAUR) {
switch (family) {
case 0x6:
return CORE_NANO;
break;
}
return CORE_VIAC3;
}
return CORE_UNKNOWN;
}
int get_cacheinfo(int type, cache_info_t *cacheinfo){
int eax, ebx, ecx, edx, cpuid_level;
int info[15];
int i;
cache_info_t LC1, LD1, L2, L3,
ITB, DTB, LITB, LDTB,
L2ITB, L2DTB, L2LITB, L2LDTB;
LC1.size = 0; LC1.associative = 0; LC1.linesize = 0; LC1.shared = 0;
LD1.size = 0; LD1.associative = 0; LD1.linesize = 0; LD1.shared = 0;
L2.size = 0; L2.associative = 0; L2.linesize = 0; L2.shared = 0;
L3.size = 0; L3.associative = 0; L3.linesize = 0; L3.shared = 0;
ITB.size = 0; ITB.associative = 0; ITB.linesize = 0; ITB.shared = 0;
DTB.size = 0; DTB.associative = 0; DTB.linesize = 0; DTB.shared = 0;
LITB.size = 0; LITB.associative = 0; LITB.linesize = 0; LITB.shared = 0;
LDTB.size = 0; LDTB.associative = 0; LDTB.linesize = 0; LDTB.shared = 0;
L2ITB.size = 0; L2ITB.associative = 0; L2ITB.linesize = 0; L2ITB.shared = 0;
L2DTB.size = 0; L2DTB.associative = 0; L2DTB.linesize = 0; L2DTB.shared = 0;
L2LITB.size = 0; L2LITB.associative = 0; L2LITB.linesize = 0; L2LITB.shared = 0;
L2LDTB.size = 0; L2LDTB.associative = 0; L2LDTB.linesize = 0; L2LDTB.shared = 0;
cpuid(0, &cpuid_level, &ebx, &ecx, &edx);
if (cpuid_level > 1) {
cpuid(2, &eax, &ebx, &ecx, &edx);
info[ 0] = BITMASK(eax, 8, 0xff);
info[ 1] = BITMASK(eax, 16, 0xff);
info[ 2] = BITMASK(eax, 24, 0xff);
info[ 3] = BITMASK(ebx, 0, 0xff);
info[ 4] = BITMASK(ebx, 8, 0xff);
info[ 5] = BITMASK(ebx, 16, 0xff);
info[ 6] = BITMASK(ebx, 24, 0xff);
info[ 7] = BITMASK(ecx, 0, 0xff);
info[ 8] = BITMASK(ecx, 8, 0xff);
info[ 9] = BITMASK(ecx, 16, 0xff);
info[10] = BITMASK(ecx, 24, 0xff);
info[11] = BITMASK(edx, 0, 0xff);
info[12] = BITMASK(edx, 8, 0xff);
info[13] = BITMASK(edx, 16, 0xff);
info[14] = BITMASK(edx, 24, 0xff);
for (i = 0; i < 15; i++){
switch (info[i]){
/* This table is from http://www.sandpile.org/ia32/cpuid.htm */
case 0x01 :
ITB.size = 4;
ITB.associative = 4;
ITB.linesize = 32;
break;
case 0x02 :
LITB.size = 4096;
LITB.associative = 0;
LITB.linesize = 2;
break;
case 0x03 :
DTB.size = 4;
DTB.associative = 4;
DTB.linesize = 64;
break;
case 0x04 :
LDTB.size = 4096;
LDTB.associative = 4;
LDTB.linesize = 8;
break;
case 0x05 :
LDTB.size = 4096;
LDTB.associative = 4;
LDTB.linesize = 32;
break;
case 0x06 :
LC1.size = 8;
LC1.associative = 4;
LC1.linesize = 32;
break;
case 0x08 :
LC1.size = 16;
LC1.associative = 4;
LC1.linesize = 32;
break;
case 0x09 :
LC1.size = 32;
LC1.associative = 4;
LC1.linesize = 64;
break;
case 0x0a :
LD1.size = 8;
LD1.associative = 2;
LD1.linesize = 32;
break;
case 0x0c :
LD1.size = 16;
LD1.associative = 4;
LD1.linesize = 32;
break;
case 0x0d :
LD1.size = 16;
LD1.associative = 4;
LD1.linesize = 64;
break;
case 0x0e :
LD1.size = 24;
LD1.associative = 6;
LD1.linesize = 64;
break;
case 0x10 :
LD1.size = 16;
LD1.associative = 4;
LD1.linesize = 32;
break;
case 0x15 :
LC1.size = 16;
LC1.associative = 4;
LC1.linesize = 32;
break;
case 0x1a :
L2.size = 96;
L2.associative = 6;
L2.linesize = 64;
break;
case 0x21 :
L2.size = 256;
L2.associative = 8;
L2.linesize = 64;
break;
case 0x22 :
L3.size = 512;
L3.associative = 4;
L3.linesize = 64;
break;
case 0x23 :
L3.size = 1024;
L3.associative = 8;
L3.linesize = 64;
break;
case 0x25 :
L3.size = 2048;
L3.associative = 8;
L3.linesize = 64;
break;
case 0x29 :
L3.size = 4096;
L3.associative = 8;
L3.linesize = 64;
break;
case 0x2c :
LD1.size = 32;
LD1.associative = 8;
LD1.linesize = 64;
break;
case 0x30 :
LC1.size = 32;
LC1.associative = 8;
LC1.linesize = 64;
break;
case 0x39 :
L2.size = 128;
L2.associative = 4;
L2.linesize = 64;
break;
case 0x3a :
L2.size = 192;
L2.associative = 6;
L2.linesize = 64;
break;
case 0x3b :
L2.size = 128;
L2.associative = 2;
L2.linesize = 64;
break;
case 0x3c :
L2.size = 256;
L2.associative = 4;
L2.linesize = 64;
break;
case 0x3d :
L2.size = 384;
L2.associative = 6;
L2.linesize = 64;
break;
case 0x3e :
L2.size = 512;
L2.associative = 4;
L2.linesize = 64;
break;
case 0x41 :
L2.size = 128;
L2.associative = 4;
L2.linesize = 32;
break;
case 0x42 :
L2.size = 256;
L2.associative = 4;
L2.linesize = 32;
break;
case 0x43 :
L2.size = 512;
L2.associative = 4;
L2.linesize = 32;
break;
case 0x44 :
L2.size = 1024;
L2.associative = 4;
L2.linesize = 32;
break;
case 0x45 :
L2.size = 2048;
L2.associative = 4;
L2.linesize = 32;
break;
case 0x46 :
L3.size = 4096;
L3.associative = 4;
L3.linesize = 64;
break;
case 0x47 :
L3.size = 8192;
L3.associative = 8;
L3.linesize = 64;
break;
case 0x48 :
L2.size = 3184;
L2.associative = 12;
L2.linesize = 64;
break;
case 0x49 :
if ((get_cputype(GET_FAMILY) == 0x0f) && (get_cputype(GET_MODEL) == 0x06)) {
L3.size = 4096;
L3.associative = 16;
L3.linesize = 64;
} else {
L2.size = 4096;
L2.associative = 16;
L2.linesize = 64;
}
break;
case 0x4a :
L3.size = 6144;
L3.associative = 12;
L3.linesize = 64;
break;
case 0x4b :
L3.size = 8192;
L3.associative = 16;
L3.linesize = 64;
break;
case 0x4c :
L3.size = 12280;
L3.associative = 12;
L3.linesize = 64;
break;
case 0x4d :
L3.size = 16384;
L3.associative = 16;
L3.linesize = 64;
break;
case 0x4e :
L2.size = 6144;
L2.associative = 24;
L2.linesize = 64;
break;
case 0x4f :
ITB.size = 4;
ITB.associative = 0;
ITB.linesize = 32;
break;
case 0x50 :
ITB.size = 4;
ITB.associative = 0;
ITB.linesize = 64;
LITB.size = 4096;
LITB.associative = 0;
LITB.linesize = 64;
LITB.shared = 1;
break;
case 0x51 :
ITB.size = 4;
ITB.associative = 0;
ITB.linesize = 128;
LITB.size = 4096;
LITB.associative = 0;
LITB.linesize = 128;
LITB.shared = 1;
break;
case 0x52 :
ITB.size = 4;
ITB.associative = 0;
ITB.linesize = 256;
LITB.size = 4096;
LITB.associative = 0;
LITB.linesize = 256;
LITB.shared = 1;
break;
case 0x55 :
LITB.size = 4096;
LITB.associative = 0;
LITB.linesize = 7;
LITB.shared = 1;
break;
case 0x56 :
LDTB.size = 4096;
LDTB.associative = 4;
LDTB.linesize = 16;
break;
case 0x57 :
LDTB.size = 4096;
LDTB.associative = 4;
LDTB.linesize = 16;
break;
case 0x5b :
DTB.size = 4;
DTB.associative = 0;
DTB.linesize = 64;
LDTB.size = 4096;
LDTB.associative = 0;
LDTB.linesize = 64;
LDTB.shared = 1;
break;
case 0x5c :
DTB.size = 4;
DTB.associative = 0;
DTB.linesize = 128;
LDTB.size = 4096;
LDTB.associative = 0;
LDTB.linesize = 128;
LDTB.shared = 1;
break;
case 0x5d :
DTB.size = 4;
DTB.associative = 0;
DTB.linesize = 256;
LDTB.size = 4096;
LDTB.associative = 0;
LDTB.linesize = 256;
LDTB.shared = 1;
break;
case 0x60 :
LD1.size = 16;
LD1.associative = 8;
LD1.linesize = 64;
break;
case 0x66 :
LD1.size = 8;
LD1.associative = 4;
LD1.linesize = 64;
break;
case 0x67 :
LD1.size = 16;
LD1.associative = 4;
LD1.linesize = 64;
break;
case 0x68 :
LD1.size = 32;
LD1.associative = 4;
LD1.linesize = 64;
break;
case 0x70 :
LC1.size = 12;
LC1.associative = 8;
break;
case 0x71 :
LC1.size = 16;
LC1.associative = 8;
break;
case 0x72 :
LC1.size = 32;
LC1.associative = 8;
break;
case 0x73 :
LC1.size = 64;
LC1.associative = 8;
break;
case 0x77 :
LC1.size = 16;
LC1.associative = 4;
LC1.linesize = 64;
break;
case 0x78 :
L2.size = 1024;
L2.associative = 4;
L2.linesize = 64;
break;
case 0x79 :
L2.size = 128;
L2.associative = 8;
L2.linesize = 64;
break;
case 0x7a :
L2.size = 256;
L2.associative = 8;
L2.linesize = 64;
break;
case 0x7b :
L2.size = 512;
L2.associative = 8;
L2.linesize = 64;
break;
case 0x7c :
L2.size = 1024;
L2.associative = 8;
L2.linesize = 64;
break;
case 0x7d :
L2.size = 2048;
L2.associative = 8;
L2.linesize = 64;
break;
case 0x7e :
L2.size = 256;
L2.associative = 8;
L2.linesize = 128;
break;
case 0x7f :
L2.size = 512;
L2.associative = 2;
L2.linesize = 64;
break;
case 0x81 :
L2.size = 128;
L2.associative = 8;
L2.linesize = 32;
break;
case 0x82 :
L2.size = 256;
L2.associative = 8;
L2.linesize = 32;
break;
case 0x83 :
L2.size = 512;
L2.associative = 8;
L2.linesize = 32;
break;
case 0x84 :
L2.size = 1024;
L2.associative = 8;
L2.linesize = 32;
break;
case 0x85 :
L2.size = 2048;
L2.associative = 8;
L2.linesize = 32;
break;
case 0x86 :
L2.size = 512;
L2.associative = 4;
L2.linesize = 64;
break;
case 0x87 :
L2.size = 1024;
L2.associative = 8;
L2.linesize = 64;
break;
case 0x88 :
L3.size = 2048;
L3.associative = 4;
L3.linesize = 64;
break;
case 0x89 :
L3.size = 4096;
L3.associative = 4;
L3.linesize = 64;
break;
case 0x8a :
L3.size = 8192;
L3.associative = 4;
L3.linesize = 64;
break;
case 0x8d :
L3.size = 3096;
L3.associative = 12;
L3.linesize = 128;
break;
case 0x90 :
ITB.size = 4;
ITB.associative = 0;
ITB.linesize = 64;
break;
case 0x96 :
DTB.size = 4;
DTB.associative = 0;
DTB.linesize = 32;
break;
case 0x9b :
L2DTB.size = 4;
L2DTB.associative = 0;
L2DTB.linesize = 96;
break;
case 0xb0 :
ITB.size = 4;
ITB.associative = 4;
ITB.linesize = 128;
break;
case 0xb1 :
LITB.size = 4096;
LITB.associative = 4;
LITB.linesize = 4;
break;
case 0xb2 :
ITB.size = 4;
ITB.associative = 4;
ITB.linesize = 64;
break;
case 0xb3 :
DTB.size = 4;
DTB.associative = 4;
DTB.linesize = 128;
break;
case 0xb4 :
DTB.size = 4;
DTB.associative = 4;
DTB.linesize = 256;
break;
case 0xba :
DTB.size = 4;
DTB.associative = 4;
DTB.linesize = 64;
break;
case 0xd0 :
L3.size = 512;
L3.associative = 4;
L3.linesize = 64;
break;
case 0xd1 :
L3.size = 1024;
L3.associative = 4;
L3.linesize = 64;
break;
case 0xd2 :
L3.size = 2048;
L3.associative = 4;
L3.linesize = 64;
break;
case 0xd6 :
L3.size = 1024;
L3.associative = 8;
L3.linesize = 64;
break;
case 0xd7 :
L3.size = 2048;
L3.associative = 8;
L3.linesize = 64;
break;
case 0xd8 :
L3.size = 4096;
L3.associative = 8;
L3.linesize = 64;
break;
case 0xdc :
L3.size = 2048;
L3.associative = 12;
L3.linesize = 64;
break;
case 0xdd :
L3.size = 4096;
L3.associative = 12;
L3.linesize = 64;
break;
case 0xde :
L3.size = 8192;
L3.associative = 12;
L3.linesize = 64;
break;
case 0xe2 :
L3.size = 2048;
L3.associative = 16;
L3.linesize = 64;
break;
case 0xe3 :
L3.size = 4096;
L3.associative = 16;
L3.linesize = 64;
break;
case 0xe4 :
L3.size = 8192;
L3.associative = 16;
L3.linesize = 64;
break;
}
}
}
if (get_vendor() == VENDOR_INTEL) {
cpuid(0x80000000, &cpuid_level, &ebx, &ecx, &edx);
if (cpuid_level >= 0x80000006) {
cpuid(0x80000006, &eax, &ebx, &ecx, &edx);
L2.size = BITMASK(ecx, 16, 0xffff);
L2.associative = BITMASK(ecx, 12, 0x0f);
L2.linesize = BITMASK(ecx, 0, 0xff);
}
}
if ((get_vendor() == VENDOR_AMD) || (get_vendor() == VENDOR_CENTAUR)) {
cpuid(0x80000005, &eax, &ebx, &ecx, &edx);
LDTB.size = 4096;
LDTB.associative = BITMASK(eax, 24, 0xff);
if (LDTB.associative == 0xff) LDTB.associative = 0;
LDTB.linesize = BITMASK(eax, 16, 0xff);
LITB.size = 4096;
LITB.associative = BITMASK(eax, 8, 0xff);
if (LITB.associative == 0xff) LITB.associative = 0;
LITB.linesize = BITMASK(eax, 0, 0xff);
DTB.size = 4;
DTB.associative = BITMASK(ebx, 24, 0xff);
if (DTB.associative == 0xff) DTB.associative = 0;
DTB.linesize = BITMASK(ebx, 16, 0xff);
ITB.size = 4;
ITB.associative = BITMASK(ebx, 8, 0xff);
if (ITB.associative == 0xff) ITB.associative = 0;
ITB.linesize = BITMASK(ebx, 0, 0xff);
LD1.size = BITMASK(ecx, 24, 0xff);
LD1.associative = BITMASK(ecx, 16, 0xff);
if (LD1.associative == 0xff) LD1.associative = 0;
LD1.linesize = BITMASK(ecx, 0, 0xff);
LC1.size = BITMASK(ecx, 24, 0xff);
LC1.associative = BITMASK(ecx, 16, 0xff);
if (LC1.associative == 0xff) LC1.associative = 0;
LC1.linesize = BITMASK(ecx, 0, 0xff);
cpuid(0x80000006, &eax, &ebx, &ecx, &edx);
L2LDTB.size = 4096;
L2LDTB.associative = BITMASK(eax, 24, 0xff);
if (L2LDTB.associative == 0xff) L2LDTB.associative = 0;
L2LDTB.linesize = BITMASK(eax, 16, 0xff);
L2LITB.size = 4096;
L2LITB.associative = BITMASK(eax, 8, 0xff);
if (L2LITB.associative == 0xff) L2LITB.associative = 0;
L2LITB.linesize = BITMASK(eax, 0, 0xff);
L2DTB.size = 4;
L2DTB.associative = BITMASK(ebx, 24, 0xff);
if (L2DTB.associative == 0xff) L2DTB.associative = 0;
L2DTB.linesize = BITMASK(ebx, 16, 0xff);
L2ITB.size = 4;
L2ITB.associative = BITMASK(ebx, 8, 0xff);
if (L2ITB.associative == 0xff) L2ITB.associative = 0;
L2ITB.linesize = BITMASK(ebx, 0, 0xff);
L2.size = BITMASK(ecx, 16, 0xffff);
L2.associative = BITMASK(ecx, 12, 0xf);
if (L2.associative == 0xff) L2.associative = 0;
L2.linesize = BITMASK(ecx, 0, 0xff);
L3.size = BITMASK(edx, 18, 0x3fff) * 512;
L3.associative = BITMASK(edx, 12, 0xf);
if (L3.associative == 0xff) L2.associative = 0;
L3.linesize = BITMASK(edx, 0, 0xff);
}
switch (type) {
case CACHE_INFO_L1_I :
*cacheinfo = LC1;
break;
case CACHE_INFO_L1_D :
*cacheinfo = LD1;
break;
case CACHE_INFO_L2 :
*cacheinfo = L2;
break;
case CACHE_INFO_L3 :
*cacheinfo = L3;
break;
case CACHE_INFO_L1_DTB :
*cacheinfo = DTB;
break;
case CACHE_INFO_L1_ITB :
*cacheinfo = ITB;
break;
case CACHE_INFO_L1_LDTB :
*cacheinfo = LDTB;
break;
case CACHE_INFO_L1_LITB :
*cacheinfo = LITB;
break;
case CACHE_INFO_L2_DTB :
*cacheinfo = L2DTB;
break;
case CACHE_INFO_L2_ITB :
*cacheinfo = L2ITB;
break;
case CACHE_INFO_L2_LDTB :
*cacheinfo = L2LDTB;
break;
case CACHE_INFO_L2_LITB :
*cacheinfo = L2LITB;
break;
}
return 0;
}
int get_cpuname(void){
int family, exfamily, model, vendor, exmodel;
if (!have_cpuid()) return CPUTYPE_80386;
family = get_cputype(GET_FAMILY);
exfamily = get_cputype(GET_EXFAMILY);
model = get_cputype(GET_MODEL);
exmodel = get_cputype(GET_EXMODEL);
vendor = get_vendor();
if (vendor == VENDOR_INTEL){
switch (family) {
case 0x4:
return CPUTYPE_80486;
case 0x5:
return CPUTYPE_PENTIUM;
case 0x6:
switch (exmodel) {
case 0:
switch (model) {
case 1:
case 3:
case 5:
case 6:
return CPUTYPE_PENTIUM2;
case 7:
case 8:
case 10:
case 11:
return CPUTYPE_PENTIUM3;
case 9:
case 13:
case 14:
return CPUTYPE_PENTIUMM;
case 15:
return CPUTYPE_CORE2;
}
break;
case 1:
switch (model) {
case 6:
return CPUTYPE_CORE2;
case 7:
return CPUTYPE_PENRYN;
case 10:
case 11:
case 14:
case 15:
return CPUTYPE_NEHALEM;
case 12:
return CPUTYPE_ATOM;
case 13:
return CPUTYPE_DUNNINGTON;
}
break;
case 2:
switch (model) {
case 5:
//Intel Core (Clarkdale) / Core (Arrandale)
// Pentium (Clarkdale) / Pentium Mobile (Arrandale)
// Xeon (Clarkdale), 32nm
return CPUTYPE_NEHALEM;
case 10:
//Intel Core i5-2000 /i7-2000 (Sandy Bridge)
if(support_avx())
return CPUTYPE_SANDYBRIDGE;
else
return CPUTYPE_NEHALEM; //OS doesn't support AVX
case 12:
//Xeon Processor 5600 (Westmere-EP)
return CPUTYPE_NEHALEM;
case 13:
//Intel Core i7-3000 / Xeon E5 (Sandy Bridge)
if(support_avx())
return CPUTYPE_SANDYBRIDGE;
else
return CPUTYPE_NEHALEM;
case 14:
// Xeon E7540
case 15:
//Xeon Processor E7 (Westmere-EX)
return CPUTYPE_NEHALEM;
}
break;
case 3:
switch (model) {
case 10:
case 14:
// Ivy Bridge
if(support_avx())
return CPUTYPE_SANDYBRIDGE;
else
return CPUTYPE_NEHALEM;
case 12:
case 15:
if(support_avx())
#ifndef NO_AVX2
return CPUTYPE_HASWELL;
#else
return CPUTYPE_SANDYBRIDGE;
#endif
else
return CPUTYPE_NEHALEM;
}
break;
case 4:
switch (model) {
case 5:
case 6:
if(support_avx())
#ifndef NO_AVX2
return CPUTYPE_HASWELL;
#else
return CPUTYPE_SANDYBRIDGE;
#endif
else
return CPUTYPE_NEHALEM;
}
break;
}
break;
case 0x7:
return CPUTYPE_ITANIUM;
case 0xf:
switch (exfamily) {
case 0 :
return CPUTYPE_PENTIUM4;
case 1 :
return CPUTYPE_ITANIUM;
}
break;
}
static struct sr_dev_inst *probe_device(struct sr_scpi_dev_inst *scpi)
{
struct dev_context *devc;
struct sr_dev_inst *sdi;
struct sr_scpi_hw_info *hw_info;
struct sr_channel_group *cg;
struct sr_channel *ch;
const struct scpi_pps *device;
struct pps_channel *pch;
struct channel_spec *channels;
struct channel_group_spec *channel_groups, *cgs;
struct pps_channel_group *pcg;
GRegex *model_re;
GMatchInfo *model_mi;
GSList *l;
uint64_t mask;
unsigned int num_channels, num_channel_groups, ch_num, ch_idx, i, j;
int ret;
const char *vendor;
char ch_name[16];
if (sr_scpi_get_hw_id(scpi, &hw_info) != SR_OK) {
sr_info("Couldn't get IDN response.");
return NULL;
}
device = NULL;
for (i = 0; i < num_pps_profiles; i++) {
vendor = get_vendor(hw_info->manufacturer);
if (strcasecmp(vendor, pps_profiles[i].vendor))
continue;
model_re = g_regex_new(pps_profiles[i].model, 0, 0, NULL);
if (g_regex_match(model_re, hw_info->model, 0, &model_mi))
device = &pps_profiles[i];
g_match_info_unref(model_mi);
g_regex_unref(model_re);
if (device)
break;
}
if (!device) {
sr_scpi_hw_info_free(hw_info);
return NULL;
}
sdi = g_malloc0(sizeof(struct sr_dev_inst));
sdi->status = SR_ST_ACTIVE;
sdi->vendor = g_strdup(vendor);
sdi->model = g_strdup(hw_info->model);
sdi->version = g_strdup(hw_info->firmware_version);
sdi->conn = scpi;
sdi->driver = di;
sdi->inst_type = SR_INST_SCPI;
sdi->serial_num = g_strdup(hw_info->serial_number);
devc = g_malloc0(sizeof(struct dev_context));
devc->device = device;
sdi->priv = devc;
if (device->num_channels) {
/* Static channels and groups. */
channels = device->channels;
num_channels = device->num_channels;
channel_groups = device->channel_groups;
num_channel_groups = device->num_channel_groups;
} else {
/* Channels and groups need to be probed. */
ret = device->probe_channels(sdi, hw_info, &channels, &num_channels,
&channel_groups, &num_channel_groups);
if (ret != SR_OK) {
sr_err("Failed to probe for channels.");
return NULL;
}
/*
* Since these were dynamically allocated, we'll need to free them
* later.
*/
devc->channels = channels;
devc->channel_groups = channel_groups;
}
ch_idx = 0;
for (ch_num = 0; ch_num < num_channels; ch_num++) {
/* Create one channel per measurable output unit. */
for (i = 0; i < ARRAY_SIZE(pci); i++) {
if (!scpi_cmd_get(sdi, pci[i].command))
continue;
g_snprintf(ch_name, 16, "%s%s", pci[i].prefix,
channels[ch_num].name);
ch = sr_channel_new(ch_idx++, SR_CHANNEL_ANALOG, TRUE, ch_name);
pch = g_malloc0(sizeof(struct pps_channel));
pch->hw_output_idx = ch_num;
pch->hwname = channels[ch_num].name;
pch->mq = pci[i].mq;
ch->priv = pch;
sdi->channels = g_slist_append(sdi->channels, ch);
}
}
for (i = 0; i < num_channel_groups; i++) {
cgs = &channel_groups[i];
cg = g_malloc0(sizeof(struct sr_channel_group));
cg->name = g_strdup(cgs->name);
for (j = 0, mask = 1; j < 64; j++, mask <<= 1) {
if (cgs->channel_index_mask & mask) {
for (l = sdi->channels; l; l = l->next) {
ch = l->data;
pch = ch->priv;
if (pch->hw_output_idx == j)
cg->channels = g_slist_append(cg->channels, ch);
}
}
}
pcg = g_malloc0(sizeof(struct pps_channel_group));
pcg->features = cgs->features;
cg->priv = pcg;
sdi->channel_groups = g_slist_append(sdi->channel_groups, cg);
}
sr_scpi_hw_info_free(hw_info);
hw_info = NULL;
scpi_cmd(sdi, SCPI_CMD_LOCAL);
sr_scpi_close(scpi);
return sdi;
}
int get_cpuname(void){
int family, exfamily, model, vendor, exmodel;
if (!have_cpuid()) return CPUTYPE_80386;
family = get_cputype(GET_FAMILY);
exfamily = get_cputype(GET_EXFAMILY);
model = get_cputype(GET_MODEL);
exmodel = get_cputype(GET_EXMODEL);
vendor = get_vendor();
if (vendor == VENDOR_INTEL){
switch (family) {
case 0x4:
return CPUTYPE_80486;
case 0x5:
return CPUTYPE_PENTIUM;
case 0x6:
switch (exmodel) {
case 0:
switch (model) {
case 1:
case 3:
case 5:
case 6:
return CPUTYPE_PENTIUM2;
case 7:
case 8:
case 10:
case 11:
return CPUTYPE_PENTIUM3;
case 9:
case 13:
case 14:
return CPUTYPE_PENTIUMM;
case 15:
return CPUTYPE_CORE2;
}
break;
case 1:
switch (model) {
case 6:
return CPUTYPE_CORE2;
case 7:
return CPUTYPE_PENRYN;
case 10:
case 11:
case 14:
case 15:
return CPUTYPE_NEHALEM;
case 12:
return CPUTYPE_ATOM;
case 13:
return CPUTYPE_DUNNINGTON;
break;
}
}
break;
case 0x7:
return CPUTYPE_ITANIUM;
case 0xf:
switch (exfamily) {
case 0 :
return CPUTYPE_PENTIUM4;
case 1 :
return CPUTYPE_ITANIUM;
}
break;
}
return CPUTYPE_INTEL_UNKNOWN;
}
if (vendor == VENDOR_AMD){
switch (family) {
case 0x4:
return CPUTYPE_AMD5X86;
case 0x5:
return CPUTYPE_AMDK6;
case 0x6:
return CPUTYPE_ATHLON;
case 0xf:
switch (exfamily) {
case 0:
case 2:
return CPUTYPE_OPTERON;
case 1:
case 10:
return CPUTYPE_BARCELONA;
}
break;
}
return CPUTYPE_AMD_UNKNOWN;
}
if (vendor == VENDOR_CYRIX){
switch (family) {
case 0x4:
return CPUTYPE_CYRIX5X86;
case 0x5:
return CPUTYPE_CYRIXM1;
case 0x6:
return CPUTYPE_CYRIXM2;
}
return CPUTYPE_CYRIX_UNKNOWN;
}
if (vendor == VENDOR_NEXGEN){
switch (family) {
case 0x5:
return CPUTYPE_NEXGENNX586;
}
return CPUTYPE_NEXGEN_UNKNOWN;
}
if (vendor == VENDOR_CENTAUR){
switch (family) {
case 0x5:
return CPUTYPE_CENTAURC6;
break;
case 0x6:
return CPUTYPE_NANO;
break;
}
return CPUTYPE_VIAC3;
}
if (vendor == VENDOR_RISE){
switch (family) {
case 0x5:
return CPUTYPE_RISEMP6;
}
return CPUTYPE_RISE_UNKNOWN;
}
if (vendor == VENDOR_SIS){
switch (family) {
case 0x5:
return CPUTYPE_SYS55X;
}
return CPUTYPE_SIS_UNKNOWN;
}
if (vendor == VENDOR_TRANSMETA){
switch (family) {
case 0x5:
return CPUTYPE_CRUSOETM3X;
}
return CPUTYPE_TRANSMETA_UNKNOWN;
}
if (vendor == VENDOR_NSC){
switch (family) {
case 0x5:
return CPUTYPE_NSGEODE;
}
return CPUTYPE_NSC_UNKNOWN;
}
return CPUTYPE_UNKNOWN;
}
int get_coretype(void){
int family, exfamily, model, exmodel, vendor;
if (!have_cpuid()) return CORE_80486;
family = get_cputype(GET_FAMILY);
exfamily = get_cputype(GET_EXFAMILY);
model = get_cputype(GET_MODEL);
exmodel = get_cputype(GET_EXMODEL);
vendor = get_vendor();
if (vendor == VENDOR_INTEL){
switch (family) {
case 4:
return CORE_80486;
case 5:
return CORE_P5;
case 6:
switch (exmodel) {
case 0:
switch (model) {
case 0:
case 1:
case 2:
case 3:
case 4:
case 5:
case 6:
return CORE_P6;
case 7:
return CORE_KATMAI;
case 8:
case 10:
case 11:
return CORE_COPPERMINE;
case 9:
case 13:
case 14:
return CORE_BANIAS;
case 15:
return CORE_CORE2;
}
break;
case 1:
switch (model) {
case 6:
return CORE_CORE2;
case 7:
return CORE_PENRYN;
case 10:
case 11:
case 14:
case 15:
return CORE_NEHALEM;
case 12:
return CORE_ATOM;
case 13:
return CORE_DUNNINGTON;
break;
}
}
case 15:
if (model <= 0x2) return CORE_NORTHWOOD;
return CORE_PRESCOTT;
}
}
if (vendor == VENDOR_AMD){
if (family <= 0x5) return CORE_80486;
if (family <= 0xe) return CORE_ATHLON;
if (family == 0xf){
if ((exfamily == 0) || (exfamily == 2)) return CORE_OPTERON; else return CORE_BARCELONA;
}
}
if (vendor == VENDOR_CENTAUR) {
switch (family) {
case 0x6:
return CORE_NANO;
break;
}
return CORE_VIAC3;
}
return CORE_UNKNOWN;
}
int cpu_detect()
{
int eax, ebx, ecx, edx;
int vendor, family, extend_family, model, extend_model;
if (!have_cpuid()) return CPUNAME_REFERENCE;
vendor=get_vendor();
cpuid(1, &eax, &ebx, &ecx, &edx);
extend_family = BITMASK(eax, 20, 0xff);
extend_model=BITMASK(eax, 16, 0x0f);
family=BITMASK(eax, 8, 0x0f);
model=BITMASK(eax, 4, 0x0f);
if (vendor == VENDOR_INTEL){
switch (family) {
case 0x6:
switch (extend_model) {
case 1:
switch (model) {
case 7:
//penryn uses dunnington config.
return CPUNAME_DUNNINGTON;
case 13:
return CPUNAME_DUNNINGTON;
}
break;
case 2:
switch (model) {
case 10:
case 13:
if(support_avx()) {
return CPUNAME_SANDYBRIDGE;
}else{
return CPUNAME_REFERENCE; //OS doesn't support AVX
}
}
break;
case 3:
switch (model) {
case 10:
case 14:
//Ivy Bridge
if(support_avx()) {
return CPUNAME_SANDYBRIDGE;
}else{
return CPUNAME_REFERENCE; //OS doesn't support AVX
}
case 12:
case 15:
//Haswell. Temp use Sandy Brdige
if(support_avx()) {
return CPUNAME_SANDYBRIDGE;
}else{
return CPUNAME_REFERENCE; //OS doesn't support AVX
}
}
break;
case 4:
switch (model) {
case 5:
case 6:
//Haswell. Temp use Sandy Brdige
if(support_avx()) {
return CPUNAME_SANDYBRIDGE;
}else{
return CPUNAME_REFERENCE; //OS doesn't support AVX
}
}
break;
}
break;
}
}else if (vendor == VENDOR_AMD){
switch (family) {
case 0xf:
switch (extend_family) {
case 6:
switch (model) {
case 1:
if(support_avx())
return CPUNAME_BULLDOZER;
else
return CPUNAME_REFERENCE; //OS don't support AVX.
case 2:
if(support_avx())
return CPUNAME_PILEDRIVER;
else
return CPUNAME_REFERENCE; //OS don't support AVX.
case 0:
//Steamroller. Temp use Piledriver.
if(support_avx())
return CPUNAME_PILEDRIVER;
else
return CPUNAME_REFERENCE; //OS don't support AVX.
}
}
break;
}
}
return CPUNAME_REFERENCE;
}