/*******************************************************************************
* Helper function to configure secure G0 SPIs.
******************************************************************************/
void gicv2_secure_spis_configure(uintptr_t gicd_base,
unsigned int num_ints,
const unsigned int *sec_intr_list)
{
unsigned int index, irq_num;
/* If `num_ints` is not 0, ensure that `sec_intr_list` is not NULL */
assert(num_ints ? (uintptr_t)sec_intr_list : 1);
for (index = 0; index < num_ints; index++) {
irq_num = sec_intr_list[index];
if (irq_num >= MIN_SPI_ID) {
/* Configure this interrupt as a secure interrupt */
gicd_clr_igroupr(gicd_base, irq_num);
/* Set the priority of this interrupt */
gicd_write_ipriorityr(gicd_base,
irq_num,
GIC_HIGHEST_SEC_PRIORITY);
/* Target the secure interrupts to primary CPU */
gicd_set_itargetsr(gicd_base, irq_num,
gicv2_get_cpuif_id(gicd_base));
/* Enable this interrupt */
gicd_set_isenabler(gicd_base, irq_num);
}
}
}
static void tbase_triggerSgiDump(void)
{
uint64_t mpidr = read_mpidr();
uint32_t linear_id = platform_get_core_pos(mpidr);
uint32_t SGITargets;
/* Configure SGI */
gicd_clr_igroupr(get_plat_config()->gicd_base, FIQ_SMP_CALL_SGI);
gicd_set_ipriorityr(get_plat_config()->gicd_base, FIQ_SMP_CALL_SGI, GIC_HIGHEST_SEC_PRIORITY);
/* Enable SGI */
gicd_set_isenabler(get_plat_config()->gicd_base, FIQ_SMP_CALL_SGI);
/* Send SGIs to all cores except the current one
(current will directly branch to the dump handler) */
SGITargets = 0xFF;
SGITargets &= ~(1 << linear_id);
/* Trigger SGI */
irq_raise_softirq(SGITargets, FIQ_SMP_CALL_SGI);
/* Current core directly branches to dump handler */
plat_tbase_dump();
}
static void gic_set_secure(unsigned int gicd_base, unsigned id)
{
/* Set interrupt as Group 0 */
gicd_clr_igroupr(gicd_base, id);
/* Set priority to max */
gicd_set_ipriorityr(gicd_base, id, GIC_HIGHEST_SEC_PRIORITY);
}
