void govw_reg_dump(void)
{
auto_pll_divisor(DEV_GOVW,CLK_ENABLE,0,0);
DPRINT("========== GOVW register dump ==========\n");
vpp_reg_dump(REG_GOVW_BEGIN,REG_GOVW_END-REG_GOVW_BEGIN);
DPRINT("GOVW enable %d\n",vppif_reg32_read(GOVW_HD_MIF_ENABLE));
DPRINT("color mode %s\n",vpp_colfmt_str[govw_get_color_format()]);
DPRINT("Y addr 0x%x,C addr 0x%x\n",vppif_reg32_in(REG_GOVW_HD_YSA),vppif_reg32_in(REG_GOVW_HD_CSA));
DPRINT("Y width %d,fb width %d\n",vppif_reg32_read(GOVW_HD_YPXLWID),vppif_reg32_read(GOVW_HD_YBUFWID));
DPRINT("C width %d,fb width %d\n",vppif_reg32_read(GOVW_HD_CPXLWID),vppif_reg32_read(GOVW_HD_CBUFWID));
DPRINT("---------- GOVW TG ----------\n");
DPRINT("TG enable %d, wait ready enable %d\n",vppif_reg32_read(GOVW_TG_ENABLE),vppif_reg32_read(GOVW_TG_WATCHDOG_ENABLE));
DPRINT("clk %d,Read cyc %d\n",vpp_get_base_clock(VPP_MOD_GOVW),vppif_reg32_read(GOVW_TG_RDCYC));
DPRINT("H total %d, beg %d, end %d\n",vppif_reg32_read(GOVW_TG_H_ALLPIXEL),
vppif_reg32_read(GOVW_TG_H_ACTBG),vppif_reg32_read(GOVW_TG_H_ACTEND));
DPRINT("V total %d, beg %d, end %d\n",vppif_reg32_read(GOVW_TG_V_ALLLINE),
vppif_reg32_read(GOVW_TG_V_ACTBG),vppif_reg32_read(GOVW_TG_V_ACTEND));
DPRINT("VBIE %d,PVBI %d\n",vppif_reg32_read(GOVW_TG_VBIE),vppif_reg32_read(GOVW_TG_PVBI));
DPRINT("Watch dog 0x%x\n",vppif_reg32_read(GOVW_TG_WATCHDOG_VALUE));
DPRINT("INT MIF C err %d,Y err %d,TG err %d\n",vppif_reg32_read(GOVW_INT_MIFCERR_ENABLE),
vppif_reg32_read(GOVW_INT_MIFYERR_ENABLE),vppif_reg32_read(GOVW_INT_TGERR_ENABLE));
auto_pll_divisor(DEV_GOVW,CLK_DISABLE,0,0);
}
/*----------------------- GOVW CSC --------------------------------------*/
void govw_set_csc_mode(vpp_csc_t mode)
{
vdo_color_fmt src_fmt,dst_fmt;
src_fmt = VDO_COL_FMT_YUV444;
dst_fmt = govw_get_color_format();
mode = vpp_check_csc_mode(mode,src_fmt,dst_fmt,0);
if (mode >= VPP_CSC_MAX) {
vppif_reg32_out(REG_GOVW_CSC_COEF1, 0x400); //CSC1
vppif_reg32_out(REG_GOVW_CSC_COEF2, 0x0); //CSC2
vppif_reg32_out(REG_GOVW_CSC_COEF3, 0x400); //CSC3
vppif_reg32_out(REG_GOVW_CSC_COEF4, 0x0); //CSC4
vppif_reg32_out(REG_GOVW_CSC_COEF5, 0x400); //CSC5
vppif_reg32_out(REG_GOVW_CSC_COEF6, 0x0); //CSC6
vppif_reg32_out(REG_GOVW_CSC_MODE, 0x0); //CSC_CTL
vppif_reg32_write(GOVW_CSC_ENABLE,0);
} else {
vppif_reg32_out(REG_GOVW_CSC_COEF1, vpp_csc_parm[mode][0]); //CSC1
vppif_reg32_out(REG_GOVW_CSC_COEF2, vpp_csc_parm[mode][1]); //CSC2
vppif_reg32_out(REG_GOVW_CSC_COEF3, vpp_csc_parm[mode][2]); //CSC3
vppif_reg32_out(REG_GOVW_CSC_COEF4, vpp_csc_parm[mode][3]); //CSC4
vppif_reg32_out(REG_GOVW_CSC_COEF5, vpp_csc_parm[mode][4]); //CSC5
vppif_reg32_out(REG_GOVW_CSC_COEF6, vpp_csc_parm[mode][5]); //CSC6
vppif_reg32_out(REG_GOVW_CSC_MODE, vpp_csc_parm[mode][6]); //CSC_CTL
vppif_reg32_write(GOVW_CSC_ENABLE,1);
}
}
void govw_set_width(U32 width, U32 fb_width)
{
vdo_color_fmt colfmt;
DBG_DETAIL("w %d,fbw %d\n",width,fb_width);
colfmt = govw_get_color_format();
vppif_reg32_write(GOVW_HD_YPXLWID, width);
vppif_reg32_write(GOVW_HD_YBUFWID, fb_width);
if( colfmt == VDO_COL_FMT_YUV444 ){
vppif_reg32_write(GOVW_HD_CBUFWID, fb_width * 2);
vppif_reg32_write(GOVW_HD_CPXLWID, width);
}
else {
vppif_reg32_write(GOVW_HD_CBUFWID, fb_width);
vppif_reg32_write(GOVW_HD_CPXLWID, width/2);
}
}
void scl_set_csc_mode(vpp_csc_t mode)
{
vdo_color_fmt src_fmt,dst_fmt;
src_fmt = sclr_get_color_format();
dst_fmt = ( scl_get_timing_master() == VPP_MOD_SCL )? sclw_get_color_format():govw_get_color_format();
mode = vpp_check_csc_mode(mode,src_fmt,dst_fmt,0);
if (mode >= VPP_CSC_MAX) {
vppif_reg32_write(SCL_CSC_ENABLE, VPP_FLAG_DISABLE);
} else {
vppif_reg32_out(REG_SCL_CSC1, vpp_csc_parm[mode][0]); //CSC1
vppif_reg32_out(REG_SCL_CSC2, vpp_csc_parm[mode][1]); //CSC2
vppif_reg32_out(REG_SCL_CSC3, vpp_csc_parm[mode][2]); //CSC3
vppif_reg32_out(REG_SCL_CSC4, vpp_csc_parm[mode][3]); //CSC4
vppif_reg32_out(REG_SCL_CSC5, vpp_csc_parm[mode][4]); //CSC5
vppif_reg32_out(REG_SCL_CSC6, vpp_csc_parm[mode][5]); //CSC6
vppif_reg32_out(REG_SCL_CSC_CTL, vpp_csc_parm[mode][6]); //CSC_CTL
vppif_reg32_write(SCL_CSC_ENABLE, VPP_FLAG_ENABLE);
}
}
