void govw_set_timing(vpp_clock_t *timing,unsigned int pixel_clock)
{
timing->read_cycle = ( timing->read_cycle < 2 )? 2:timing->read_cycle;
timing->read_cycle = ( timing->read_cycle > 255 )? 0xFF:timing->read_cycle;
govw_set_tg_enable(VPP_FLAG_DISABLE);
vppif_reg32_write(GOVW_TG_RDCYC,timing->read_cycle);
vppif_reg32_write(GOVW_TG_H_ALLPIXEL,timing->total_pixel_of_line);
vppif_reg32_write(GOVW_TG_H_ACTBG,timing->begin_pixel_of_active);
vppif_reg32_write(GOVW_TG_H_ACTEND,timing->end_pixel_of_active);
vppif_reg32_write(GOVW_TG_V_ALLLINE,timing->total_line_of_frame);
vppif_reg32_write(GOVW_TG_V_ACTBG,timing->begin_line_of_active);
vppif_reg32_write(GOVW_TG_V_ACTEND,timing->end_line_of_active);
vppif_reg32_write(GOVW_TG_VBIE,timing->line_number_between_VBIS_VBIE);
//vppif_reg32_write(GOVW_TG_PVBI,timing->line_number_between_PVBI_VBIS);
vppif_reg32_write(GOVW_TG_PVBI,10);
govw_set_tg_enable(VPP_FLAG_ENABLE);
}
void govw_init(void *base)
{
govw_mod_t *mod_p;
mod_p = (govw_mod_t *) base;
// vppif_reg32_write(0xd8130254,BIT29,29,1); // GOVW clock enable
//disable
govw_set_reg_level(VPP_REG_LEVEL_1);
govw_set_int_enable(VPP_FLAG_DISABLE, VPP_INT_ALL);
govw_set_hd_mif_enable(VPP_FLAG_DISABLE);
govw_set_tg_enable(VPP_FLAG_DISABLE);
//register
govw_set_hd_framebuffer(&mod_p->fb_p->fb);
govw_set_watchdog(mod_p->fb_p->wait_ready);
//enable
//govw_set_int_enable(VPP_FLAG_ENABLE, mod_p->int_catch);
govw_set_hd_mif_enable(VPP_FLAG_ENABLE);
govw_set_reg_update(VPP_FLAG_ENABLE);
govw_set_tg_enable(VPP_FLAG_ENABLE);
}
void govw_init(void *base)
{
govw_mod_t *mod_p;
mod_p = (govw_mod_t *) base;
//disable
govw_set_reg_level(VPP_REG_LEVEL_1);
govw_set_int_enable(VPP_FLAG_DISABLE, VPP_INT_ALL);
govw_set_mif_enable(VPP_FLAG_DISABLE);
govw_set_tg_enable(VPP_FLAG_DISABLE);
//register
govw_set_framebuffer(&mod_p->fb_p->fb);
govw_set_watchdog(mod_p->fb_p->wait_ready);
//enable
govw_set_int_enable(VPP_FLAG_ENABLE, mod_p->int_catch);
govw_set_reg_update(VPP_FLAG_ENABLE);
// govw_set_tg_enable(VPP_FLAG_ENABLE);
}
