void __sramfunc board_pmu_suspend(void)
{
cru_writel(CRU_CLKGATE5_GRFCLK_ON,CRU_CLKGATE5_CON_ADDR); //open grf clk
grf_writel(GPIO6_PB1_DIR_OUT, GRF_GPIO6L_DIR_ADDR);
grf_writel(GPIO6_PB1_DO_HIGH, GRF_GPIO6L_DO_ADDR); //set gpio6_b1 output low
grf_writel(GPIO6_PB1_EN_MASK, GRF_GPIO6L_EN_ADDR);
}
__maybe_unused
void rk_iomux_sdcard_restore(void)
{
debug("rk restore sdcard iomux config.\n");
grf_writel((3 << 28) | (3 << 30) | grf_gpio1b_iomux, GRF_GPIO1B_IOMUX);
grf_writel((0xFFF << 16) | grf_gpio1c_iomux, GRF_GPIO1C_IOMUX);
debug("grf gpio1b iomux = 0x%08x\n", grf_readl(GRF_GPIO1B_IOMUX) & ((3<<12) | (3<<14)));
debug("grf gpio1c iomux = 0x%08x\n", grf_readl(GRF_GPIO1C_IOMUX) & 0xFFF);
}
static int rk30_vmac_speed_switch(int speed)
{
// printk("%s--speed=%d\n", __FUNCTION__, speed);
if (10 == speed) {
grf_writel(grf_readl(GRF_SOC_CON1) | (2<<16) & (~BIT_EMAC_SPEED), GRF_SOC_CON1);
} else {
grf_writel(grf_readl(GRF_SOC_CON1) | (2<<16) | BIT_EMAC_SPEED, GRF_SOC_CON1);
}
}
static void SET_RMII_100M(int type)
{
if (type == RK3288_GMAC) {
grf_writel(GMAC_RMII_CLK_25M, RK3288_GRF_SOC_CON1);
grf_writel(GMAC_SPEED_100M, RK3288_GRF_SOC_CON1);
} else if (type == RK312X_GMAC) {
// grf_writel(GMAC_RMII_CLK_25M, RK312X_GRF_MAC_CON1);
// grf_writel(GMAC_SPEED_100M, RK312X_GRF_MAC_CON1);
}
}
static void SET_RMII(int type)
{
if (type == RK3288_GMAC) {
grf_writel(GMAC_PHY_INTF_SEL_RMII, RK3288_GRF_SOC_CON1);
grf_writel(GMAC_RMII_MODE, RK3288_GRF_SOC_CON1);
} else if (type == RK312X_GMAC) {
// grf_writel(GMAC_PHY_INTF_SEL_RMII, RK312X_GRF_MAC_CON1);
// grf_writel(GMAC_RMII_MODE, RK312X_GRF_MAC_CON1);
}
}
void __sramfunc board_pmu_tps65910_resume(void)
{
grf_writel(GPIO6_PB1_DIR_OUT, GRF_GPIO6L_DIR_ADDR);
grf_writel(GPIO6_PB1_DO_LOW, GRF_GPIO6L_DO_ADDR); //set gpio6_b1 output low
grf_writel(GPIO6_PB1_EN_MASK, GRF_GPIO6L_EN_ADDR);
#ifdef CONFIG_CLK_SWITCH_TO_32K //switch clk to 24M
sram_32k_udelay(10000);
#else
sram_udelay(2000);
#endif
}
void __sramfunc board_pmu_resume(void)
{
grf_writel(GPIO6_PB1_DIR_OUT, GRF_GPIO6L_DIR_ADDR);
grf_writel(GPIO6_PB1_DO_LOW, GRF_GPIO6L_DO_ADDR); //set gpio6_b1 output high
grf_writel(GPIO6_PB1_EN_MASK, GRF_GPIO6L_EN_ADDR);
#ifdef CONFIG_CLK_SWITCH_TO_32K
sram_32k_udelay(10000);
#else
sram_udelay(10000);
#endif
}
void * stmmc_pltfr_fix_mac_speed(void *priv, unsigned int speed) {
printk("enter func %s...\n", __func__);
struct bsp_priv * bsp_priv = priv;
int interface;
printk("fix speed to %d\n", speed);
if (bsp_priv) {
interface = bsp_priv->phy_iface;
}
if (interface & PHY_INTERFACE_MODE_RGMII) {
printk("fix speed for RGMII\n");
switch (speed) {
case 10: {
grf_writel(GMAC_CLK_2_5M, RK3288_GRF_SOC_CON1);
break;
}
case 100: {
grf_writel(GMAC_CLK_25M, RK3288_GRF_SOC_CON1);
break;
}
case 1000: {
grf_writel(GMAC_CLK_125M, RK3288_GRF_SOC_CON1);
break;
}
default: {
printk("ERROR: speed %d is not defined!\n");
}
}
} else if (interface & PHY_INTERFACE_MODE_RMII) {
printk("fix speed for RMII\n");
switch (speed) {
case 10: {
grf_writel(GMAC_RMII_CLK_2_5M, RK3288_GRF_SOC_CON1);
break;
}
case 100: {
grf_writel(GMAC_RMII_CLK_25M, RK3288_GRF_SOC_CON1);
break;
}
default: {
printk("ERROR: speed %d is not defined!\n");
}
}
} else {
printk("ERROR: NO interface defined!\n");
}
return NULL;
}
void __sramfunc board_pmu_wm8326_suspend(void)
{
#ifdef CONFIG_DWC_REMOTE_WAKEUP
cru_writel(CRU_CLKGATE5_GRFCLK_ON|0x60000000,CRU_CLKGATE5_CON_ADDR); //open grf clk
#else
cru_writel(CRU_CLKGATE5_GRFCLK_ON,CRU_CLKGATE5_CON_ADDR); //open grf clk
grf_writel(GPIO6_PB1_DIR_OUT, GRF_GPIO6L_DIR_ADDR);
grf_writel(GPIO6_PB1_DO_HIGH, GRF_GPIO6L_DO_ADDR); //set gpio6_b1 output low
grf_writel(GPIO6_PB1_EN_MASK, GRF_GPIO6L_EN_ADDR);
#endif
}
static void rk_emmc_iomux_config(int emmc_id)
{
switch (emmc_id) {
case RK_EMMC_IOMUX:
grf_writel((0xFFFF << 16) | 0xAAAA, GRF_GPIO3A_IOMUX); // emmc data0-7
grf_writel((0x000C << 16) | 0x0008, GRF_GPIO3B_IOMUX); // emmc pwren
grf_writel((0x003F << 16) | 0x002A, GRF_GPIO3C_IOMUX); // emmc cmd, emmc rstn out, emmc clkout
break;
default:
debug("RK have not this emmc iomux id!\n");
break;
}
}
static void rk_spi_iomux_config(int spi_id)
{
switch (spi_id) {
case RK_SPI0_CS0_IOMUX:
grf_writel((((0x3<<14)|(0x3<<12)|(0x3<<10)|(0x3<<8))<<16)|(0x1<<14)|(0x1<<12)|(0x1<<10)|(0x1<<8), GRF_GPIO5B_IOMUX);
break;
case RK_SPI0_CS1_IOMUX:
grf_writel((((0x3<<14)|(0x3<<12)|(0x3<<8))<<16)|(0x1<<14)|(0x1<<12)|(0x1<<8), GRF_GPIO5B_IOMUX);
grf_writel(((0x3)<<16)|(0x1), GRF_GPIO5C_IOMUX);
break;
case RK_SPI1_CS0_IOMUX:
grf_writel((((0x3<<14)|(0x3<<12)|((0x3<<10))|(0x3<<8))<<16)|(0x2<<14)|(0x2<<12)|((0x2<<10))|(0x2<<8), GRF_GPIO7B_IOMUX);
break;
case RK_SPI1_CS1_IOMUX:
debug("rkspi: bus=1 cs=1 not support");
break;
case RK_SPI2_CS0_IOMUX:
grf_writel(((0xf<<12)<<16) | (0x5<<12), GRF_GPIO8A_IOMUX);
grf_writel((((0x3<<2)|(0x3))<<16)|(0x1<<2)|(0x1), GRF_GPIO8B_IOMUX);
break;
case RK_SPI2_CS1_IOMUX:
grf_writel((((0x3<<12)|(0x3<<6))<<16)|(0x1<<12)|(0x1<<6), GRF_GPIO8A_IOMUX);
grf_writel((((0x3<<2)|(0x3))<<16)|(0x1<<2)|(0x1), GRF_GPIO8B_IOMUX);
break;
default :
debug("RK have not this spi iomux id!\n");
break;
}
}
static void rk_sdcard_iomux_config(int sdcard_id)
{
switch (sdcard_id) {
case RK_SDCARD_IOMUX:
// iomux sdcard pwren, cmd
grf_writel((3 << 28) | (3 << 30)| (1<<12) | (1<<14), GRF_GPIO1B_IOMUX);
// iomux sdcard d0 - d3, detn, clkout
grf_writel((0xFFF << 16) | 0x555, GRF_GPIO1C_IOMUX);
break;
default:
debug("sdcard id = %d iomux error!\n", sdcard_id);
break;
}
}
static void rk_hdmi_iomux_config(int hdmi_id)
{
switch (hdmi_id) {
case RK_HDMI_IOMUX:
//i2c_hdmi_sda GRF_GPIO7CL_IOMUX[13:12]=10
grf_writel((0x2 << 12) | ((0x3 << 12) << 16), GRF_GPIO7CL_IOMUX);
//i2c_hdmi_scl GRF_GPIO7CH_IOMUX[1:0]=10
grf_writel((0x2 << 0) | ((0x3 << 0) << 16), GRF_GPIO7CH_IOMUX);
break;
default:
debug("hdmi id = %d iomux error!\n", hdmi_id);
break;
}
}
static void rk_emmc_iomux_config(int emmc_id)
{
switch (emmc_id) {
case RK_EMMC_IOMUX:
// emmc data0-7
grf_writel((0xFFFF << 16) | 0xAAAA, GRF_GPIO1D_IOMUX);
// emmc emmc rstn out, pwren, emmc clkout
// note: here no iomux emmc cmd for maskrom has do it for rk3126 or rk3128
grf_writel((3<<18) | (3<<26) | (3<<30) | (2<<2) | (2<<10) | (2<<14), GRF_GPIO2A_IOMUX);
break;
default:
debug("emmc id = %d iomux error!\n", emmc_id);
break;
}
}
static int rk30_rmii_io_init(void)
{
int err;
printk("enter %s ",__func__);
iomux_set(GPIO0_C0);//power pwr
iomux_set(GPIO3_D2);//int
iomux_set(RMII_MD);//IO3_D0
iomux_set(RMII_MDCLK);//IO3_D1
iomux_set(RMII_RXD0);
iomux_set(RMII_RXD1);
iomux_set(RMII_CRS);
iomux_set(RMII_RXERR);
iomux_set(RMII_TXD0);
iomux_set(RMII_TXD1);
iomux_set(RMII_TXEN);
iomux_set(RMII_CLKOUT);
//rk3188 gpio3 and sdio drive strength ,
grf_writel(0x0f<<16|0x0f,GRF_IO_CON3);
//phy power gpio
err = gpio_request(PHY_PWR_EN_GPIO, "phy_power_en");
if (err) {
printk("request phy power en pin faile ! \n");
return -1;
}
//phy power down
gpio_direction_output(PHY_PWR_EN_GPIO, !PHY_PWR_EN_VALUE);
gpio_set_value(PHY_PWR_EN_GPIO, !PHY_PWR_EN_VALUE);
return 0;
}
static void rk_hdmi_iomux_config(int hdmi_id)
{
switch (hdmi_id) {
case RK_HDMI_IOMUX:
/*iomux scl/ada/*/
grf_writel((0xa000 | (0xa000 << 16)), GRF_GPIO0A_IOMUX);
/*iomux hpd*/
grf_writel((0x4000 | (0x4000 << 16)), GRF_GPIO0B_IOMUX);
/*iomux cec*/
grf_writel((0x0100 | (0x0100 << 16)), GRF_GPIO0C_IOMUX);
break;
default:
debug("hdmi id = %d iomux error!\n", hdmi_id);
break;
}
}
int rk_lcdc_init(int lcdc_id)
{
struct lcdc_device *lcdc_dev = &rk32_lcdc;
u32 msk, val;
lcdc_dev->soc_type = gd->arch.chiptype;
lcdc_dev->id = lcdc_id;
#ifdef CONFIG_OF_LIBFDT
if (!lcdc_dev->node)
rk32_lcdc_parse_dt(lcdc_dev, gd->fdt_blob);
#endif
if (lcdc_dev->node <= 0) {
if (lcdc_dev->id == 0)
lcdc_dev->regs = RKIO_VOP_BIG_PHYS;
else
lcdc_dev->regs = RKIO_VOP_LIT_PHYS;
}
grf_writel(1<<16, GRF_IO_VSEL); /*LCDCIOdomain 3.3 Vvoltageselectio*/
msk = m_AUTO_GATING_EN | m_STANDBY_EN |
m_DMA_STOP | m_MMU_EN;
val = v_AUTO_GATING_EN(1) | v_STANDBY_EN(0) |
v_DMA_STOP(0) | v_MMU_EN(0);
lcdc_msk_reg(lcdc_dev, SYS_CTRL, msk, val);
msk = m_DSP_LAYER3_SEL | m_DSP_LAYER2_SEL|
m_DSP_LAYER1_SEL | m_DSP_LAYER0_SEL;
val = v_DSP_LAYER3_SEL(3) | v_DSP_LAYER2_SEL(2) |
v_DSP_LAYER1_SEL(1) | v_DSP_LAYER0_SEL(0);
lcdc_msk_reg(lcdc_dev, DSP_CTRL1, msk, val);
lcdc_cfg_done(lcdc_dev);
return 0;
}
__maybe_unused
void rk_iomux_sdcard_restore(void)
{
debug("rk restore sdcard iomux config.\n");
grf_writel((0x1FFFF << 16) | grf_gpio6c_iomux, GRF_GPIO6C_IOMUX);
debug("grf gpio6c iomux = 0x%08x\n", grf_readl(GRF_GPIO6C_IOMUX) & 0x1FFFF);
}
static void dac_enable(bool enable)
{
u32 mask, val;
u32 grfreg = 0;
TVEDBG("%s enable %d\n", __func__, enable);
if (enable) {
mask = m_VBG_EN | m_DAC_EN | m_DAC_GAIN;
if (rk3036_tve->soctype == SOC_RK312X) {
val = m_VBG_EN | m_DAC_EN | v_DAC_GAIN(0x3a);
grfreg = RK312X_GRF_TVE_CON;
} else if (rk3036_tve->soctype == SOC_RK3036) {
val = m_VBG_EN | m_DAC_EN | v_DAC_GAIN(0x3e);
grfreg = RK3036_GRF_SOC_CON3;
}
} else {
mask = m_VBG_EN | m_DAC_EN;
val = 0;
if (rk3036_tve->soctype == SOC_RK312X)
grfreg = RK312X_GRF_TVE_CON;
else if (rk3036_tve->soctype == SOC_RK3036)
grfreg = RK3036_GRF_SOC_CON3;
}
if (grfreg)
grf_writel(grfreg, (mask << 16) | val);
}
static int rk32_lvds_disable(void)
{
grf_writel(0x80008000, GRF_SOC_CON7);
writel(0x00, lvds_regs + LVDS_CFG_REG_21); /*disable tx*/
writel(0xff, lvds_regs + LVDS_CFG_REG_c); /*disable pll*/
return 0;
}
static void SET_RGMII_10M(int type)
{
if (type == RK3288_GMAC) {
grf_writel(GMAC_CLK_2_5M, RK3288_GRF_SOC_CON1);
} else if (type == RK312X_GMAC) {
// grf_writel(GMAC_CLK_2_5M, RK312X_GRF_MAC_CON1);
}
}
static void rk_uart_iomux_config(int uart_id)
{
switch (uart_id) {
case RK_UART0_IOMUX:
grf_writel((3<<22)|(3<<20)|(2<<6)|(2<<4), GRF_GPIO2D_IOMUX);
break;
case RK_UART1_IOMUX:
grf_writel((3<<20)|(3<<18)|(2<<4)|(2<<2), GRF_GPIO1B_IOMUX);
break;
case RK_UART2_IOMUX:
grf_writel((3<<22)|(3<<20)|(2<<6)|(2<<4), GRF_GPIO1C_IOMUX);
break;
default:
debug("uart id = %d iomux error!\n", uart_id);
break;
}
}
static int rk32_lvds_disable(void)
{
struct rk32_lvds *lvds = rk32_lvds;
grf_writel(0xffff8000, RK3288_GRF_SOC_CON7);
writel_relaxed(0x00, lvds->regs + LVDS_CFG_REG_21); /*disable tx*/
writel_relaxed(0xff, lvds->regs + LVDS_CFG_REG_c); /*disable pll*/
rk32_lvds_clk_disable(lvds);
return 0;
}
/*0 core, 1 gpu, 2 func*/
static u32 rk312x_pvtm_get_value(u32 ch , u32 time_us)
{
u32 val = 0, clk_cnt, check_cnt, pvtm_done_bit;
if (ch > 2)
return 0;
/*24m clk ,24cnt=1us*/
clk_cnt = time_us*24;
grf_writel(clk_cnt, RK312X_PVTM_CON0+(ch+1)*4);
if ((ch == 0) || (ch == 1))
grf_writel(wr_msk_bit(3, ch*8, 0x3), RK312X_PVTM_CON0);
else if (ch == 2)
grf_writel(wr_msk_bit(3, 12, 0x3), RK312X_PVTM_CON0);
if (time_us >= 1000)
mdelay(time_us / 1000);
udelay(time_us % 1000);
if (ch == 0)
pvtm_done_bit = 1;
else if (ch == 1)
pvtm_done_bit = 0;
else if (ch == 2)
pvtm_done_bit = 2;
check_cnt = 100;
while (!(grf_readl(RK312X_PVTM_STATUS0) & (1 << pvtm_done_bit))) {
udelay(4);
check_cnt--;
if (!check_cnt)
break;
}
if (check_cnt)
val = grf_readl(RK312X_PVTM_STATUS0+(ch+1)*4);
if ((ch == 0) || (ch == 1))
grf_writel(wr_msk_bit(0, ch*8, 0x3), RK312X_PVTM_CON0);
else if (ch == 2)
grf_writel(wr_msk_bit(0, 12, 0x3), RK312X_PVTM_CON0);
return val;
}
static void __sramfunc rk29_pwm_set_core_voltage(unsigned int uV)
{
u32 clk_gate2;
char id = 3;
//sram_printch('y');
#if 1
gate_save_soc_clk(0
| (1 << CLK_GATE_ACLK_PEIRPH % 16)
| (1 << CLK_GATE_HCLK_PEIRPH % 16)
| (1 << CLK_GATE_PCLK_PEIRPH % 16)
, clk_gate2, CRU_CLKGATES_CON(2), 0
| (1 << ((CLK_GATE_ACLK_PEIRPH % 16) + 16))
| (1 << ((CLK_GATE_HCLK_PEIRPH % 16) + 16))
| (1 << ((CLK_GATE_PCLK_PEIRPH % 16) + 16)));
#endif
/* iomux pwm3 */
writel_relaxed((readl_relaxed(RK30_GRF_BASE + 0xB4) & ~(0x1<<14)) | (0x1<<14) |(0x1<<30), RK30_GRF_BASE + 0xB4);//PWM
if (uV) {
pwm_lrc = pwm_read_reg(id,PWM_REG_LRC);
pwm_hrc = pwm_read_reg(id,PWM_REG_HRC);
writel_relaxed((readl_relaxed(RK30_GRF_BASE + 0xB4) & ~(0x1<<14)) | (0x1<<30), RK30_GRF_BASE + 0xB4);//GPIO
grf_writel(GPIO0_PD7_DIR_OUT, GRF_GPIO0H_DIR_ADDR);
grf_writel(GPIO0_PD7_DO_HIGH, GRF_GPIO0H_DO_ADDR);
grf_writel(GPIO0_PD7_EN_MASK, GRF_GPIO0H_EN_ADDR);
}else
{
pwm_write_reg(id,PWM_REG_CTRL, PWM_DIV|PWM_RESET);
pwm_write_reg(id,PWM_REG_LRC, pwm_lrc);
pwm_write_reg(id,PWM_REG_HRC, pwm_hrc);
pwm_write_reg(id,PWM_REG_CNTR, 0);
pwm_write_reg(id,PWM_REG_CTRL, PWM_DIV|PWM_ENABLE|PWM_TimeEN);
}
LOOP(10 * 1000 * LOOPS_PER_USEC); /* delay 10ms */
cru_writel(clk_gate2, CRU_CLKGATES_CON(2));
}
static void rk_lcdc_iomux_config(int lcd_id)
{
switch (lcd_id) {
case RK_LCDC0_IOMUX:
grf_writel(0x00550055, GRF_GPIO2B_IOMUX); //lcdc0 iomux
break;
default :
debug("lcdc id = %d iomux error!\n", lcd_id);
break;
}
}
static void rk_lcdc_iomux_config(int lcd_id)
{
switch (lcd_id) {
case RK_LCDC0_IOMUX:
grf_writel(0x00550055, GRF_GPIO1D_IOMUX); //lcdc0 iomux
break;
default :
debug("RK have not this lcdc iomux id!\n");
break;
}
}
static void rk_pwm_iomux_config(int pwm_id)
{
switch (pwm_id) {
case RK_PWM0_IOMUX:
grf_writel((3<<16)|1, GRF_GPIO7A_IOMUX);
break;
case RK_PWM1_IOMUX:
grf_writel((1<<18)|(1<<2), GRF_GPIO7A_IOMUX);
break;
case RK_PWM2_IOMUX:
grf_writel((1<<24)|(1<<8), GRF_GPIO7CH_IOMUX);
break;
case RK_PWM3_IOMUX:
grf_writel((1<<16)|1, GRF_GPIO7CH_IOMUX);
break;
default :
debug("RK have not this pwm iomux id!\n");
break;
}
}
static void rk_i2c_iomux_config(int i2c_id)
{
switch (i2c_id) {
case RK_I2C0_IOMUX:
grf_writel((1<<18)|(1<<16)|(1<<2)|(1<<0), GRF_GPIO0A_IOMUX);
break;
case RK_I2C1_IOMUX:
grf_writel((3<<22)|(1<<20)|(1<<6)|(1<<4), GRF_GPIO0A_IOMUX);
break;
case RK_I2C2_IOMUX:
grf_writel((7<<20)|(7<<16)|(3<<4)|(3<<0), GRF_GPIO2C_IOMUX2);
break;
case RK_I2C3_IOMUX:
grf_writel((3<<30)|(3<<28)|(1<<14)|(1<<12), GRF_GPIO0A_IOMUX);
break;
default :
debug("i2c id = %d iomux error!\n", i2c_id);
break;
}
}
static void rk_spi_iomux_config(int spi_id)
{
switch (spi_id) {
case RK_SPI0_CS0_IOMUX:
grf_writel((3<<28)|(3<<26)|(3<<22)|(3<<18)|(2<<12)|(2<<10)|(2<<6)|(2<<2), GRF_GPIO0B_IOMUX);
break;
default :
debug("spi id = %d iomux error!\n", spi_id);
break;
}
}
