/*
* gt_comm_intr_init - enable GT-64260 Comm Unit interrupts
*/
static void
gt_comm_intr_enb(struct gt_softc *gt)
{
u_int32_t cause;
cause = gt_read(gt, GT_CommUnitIntr_Cause);
if (cause)
gt_write(gt, GT_CommUnitIntr_Cause, ~cause);
gt_write(gt, GT_CommUnitIntr_Mask, GT_CommUnitIntr_DFLT);
(void)gt_read(gt, GT_CommUnitIntr_ErrAddr);
intr_establish(IRQ_COMM, IST_LEVEL, IPL_GTERR, gt_comm_intr, gt);
printf("%s: Comm Unit irpt at %d\n", gt->gt_dev.dv_xname, IRQ_COMM);
}
/******************************************************************************
** Function : i2c_word_write
** Description : This routine does page write in to AT24C02A
** serial EEPROM at a specified offset
** Inputs : devAdd - EEPROM hardware address
** writeoffset - page offset
** noBytes - Number of bytes to be written
** regFile1 - Array of data to be written
** Outputs : true - If successful
** false - If not successful
******************************************************************************/
bool i2c_word_write( u_char devAdd, uint writeoffset,
uint noBytes, u_char *regFile1 )
{
u_char regFile2[34];
uint i = 0, j = 0;
bool ret = true;
/* 13-bit address for 64k EEPROM*/
writeoffset = writeoffset & 0x1fff;
if(( noBytes < 0 ) || ( noBytes > 8192 )){
DBG("Only 0-8192 Bytes can be written.\n");
return( false );
}
gt_write( I2C_SOFT_RESET, 0x0 );
udelay( I2C_DELAY );
for( i = 0,j = 2; i < noBytes; i++ ){
regFile2[j]=regFile1[i];
if(( j == ( 33 - ( writeoffset % 32 ))) ||
( i == (noBytes-1))){
udelay( I2C_DELAY );
regFile2[0] = ( writeoffset & 0xff00 ) >> 8;
regFile2[1] = writeoffset & 0x00ff;
gt_write( I2C_SOFT_RESET, 0x0 );
udelay( I2C_DELAY );
if( i2c_write( devAdd, regFile2, j + 1 )){
DBG("Burning of a Page over\n");
}
else {
DBG("Page burning Failed...\n");
ret = false;
break;
}
j = 1;
writeoffset = writeoffset + 0x0020;
writeoffset = writeoffset & 0xffffffe0;
}
j++;
}
/******************************************************************************
** Function : i2c_byte_write
** Description : This routine does page write in to AT24C02A serial EEPROM at
** a specified offset
** Inputs : devAdd - EEPROM hardware address
** writeoffset - page offset
** noBytes - Number of bytes to be written
** regFile1 - Array of data to be written
** Outputs : true - If successful
** false - If not successful
******************************************************************************/
bool i2c_byte_write( u_char devAdd, u_char writeoffset,
uint noBytes, u_char *regFile1 )
{
u_char regFile2[9];
uint i = 0, j = 0;
bool ret = true;
if(( noBytes < 0 ) || ( noBytes > 256 )){
DBG("Only 0-256 Bytes can be written.\n");
return( false );
}
gt_write( I2C_SOFT_RESET, 0x0 );
udelay( I2C_DELAY );
for( i = 0, j = 1; i < noBytes; i++ ){
regFile2[j]=regFile1[i];
if(( j == 8 - ( writeoffset % 8 )) ||
( i == ( noBytes - 1 ))){
udelay( I2C_DELAY );
regFile2[0] = writeoffset;
gt_write( I2C_SOFT_RESET, 0x0 );
udelay( I2C_DELAY );
if( i2c_write ( devAdd, regFile2, j + 1 )){
DBG("Burning of a Page over\n");
}
else{
DBG("Page burning Failed...\n");
ret = false;
break;
}
j = 0;
writeoffset = writeoffset + 8;
/* To go to the next page*/
writeoffset = writeoffset & 0xfffffff8;
}
j++;
}/* End for ... */
return( ret );
}
static int
gt_ecc_intr(void *arg)
{
struct gt_softc *gt = (struct gt_softc *)arg;
u_int32_t addr;
u_int32_t dlo;
u_int32_t dhi;
u_int32_t rec;
u_int32_t calc;
u_int32_t count;
int err;
count = gt_read(gt, GT_ECC_Count);
dlo = gt_read(gt, GT_ECC_Data_Lo);
dhi = gt_read(gt, GT_ECC_Data_Hi);
rec = gt_read(gt, GT_ECC_Rec);
calc = gt_read(gt, GT_ECC_Calc);
addr = gt_read(gt, GT_ECC_Addr); /* read last! */
gt_write(gt, GT_ECC_Addr, 0); /* clear irpt */
err = addr & 0x3;
printf("%s: ECC error: %s: "
"addr %#x data %#x.%#x rec %#x calc %#x cnt %#x\n",
gt->gt_dev.dv_xname, gt_ecc_intr_str[err],
addr, dhi, dlo, rec, calc, count);
if (err == 2)
panic("ecc");
return (err == 1);
}
/******************************************************************************
** Function : clearIntFlag
******************************************************************************/
void clearIntFlag( )
{
uint temp;
temp = gt_read( I2C_CONTROL );
gt_write( I2C_CONTROL, temp & 0xfffffff7 );
}
/*
* gt_ecc_intr_enb - enable GT-64260 ECC interrupts
*/
static void
gt_ecc_intr_enb(struct gt_softc *gt)
{
u_int32_t ctl;
ctl = gt_read(gt, GT_ECC_Ctl);
ctl |= 1 << 16; /* XXX 1-bit threshold == 1 */
gt_write(gt, GT_ECC_Ctl, ctl);
(void)gt_read(gt, GT_ECC_Data_Lo);
(void)gt_read(gt, GT_ECC_Data_Hi);
(void)gt_read(gt, GT_ECC_Rec);
(void)gt_read(gt, GT_ECC_Calc);
(void)gt_read(gt, GT_ECC_Addr); /* read last! */
gt_write(gt, GT_ECC_Addr, 0); /* clear irpt */
intr_establish(IRQ_ECC, IST_LEVEL, IPL_GTERR, gt_ecc_intr, gt);
printf("%s: ECC irpt at %d\n", gt->gt_dev.dv_xname, IRQ_ECC);
}
void
gt_init_interrupt(struct gt_softc *gt)
{
u_int32_t mppirpts = GT_MPP_INTERRUPTS; /* from config */
u_int32_t r;
u_int32_t mppbit;
u_int32_t mask;
u_int32_t mppsel;
u_int32_t regoff;
gt_write(gt, ICR_CIM_LO, 0);
gt_write(gt, ICR_CIM_HI, 0);
/*
* configure the GPP interrupts:
* - set the configured MPP pins in GPP mode
* - set the configured GPP pins to input, active low, interrupt enbl
*/
#ifdef DEBUG
printf("%s: mpp cfg ", gt->gt_dev.dv_xname);
for (regoff = GT_MPP_Control0; regoff <= GT_MPP_Control3; regoff += 4)
printf("%#x ", gt_read(gt, regoff));
printf(", mppirpts 0x%x\n", mppirpts);
#endif
mppbit = 0x1;
for (regoff = GT_MPP_Control0; regoff <= GT_MPP_Control3; regoff += 4) {
mask = 0;
for (mppsel = 0xf; mppsel; mppsel <<= 4) {
if (mppirpts & mppbit)
mask |= mppsel;
mppbit <<= 1;
}
if (mask) {
r = gt_read(gt, regoff);
r &= ~mask;
gt_write(gt, regoff, r);
}
}
r = gt_read(gt, GT_GPP_IO_Control);
r &= ~mppirpts;
gt_write(gt, GT_GPP_IO_Control, r);
r = gt_read(gt, GT_GPP_Level_Control);
r |= mppirpts;
gt_write(gt, GT_GPP_Level_Control, r);
r = gt_read(gt, GT_GPP_Interrupt_Mask);
r |= mppirpts;
gt_write(gt, GT_GPP_Interrupt_Mask, r);
}
static int
gt_comm_intr(void *arg)
{
struct gt_softc *gt = (struct gt_softc *)arg;
u_int32_t cause;
u_int32_t addr;
unsigned int mask;
int i;
cause = gt_read(gt, GT_CommUnitIntr_Cause);
gt_write(gt, GT_CommUnitIntr_Cause, ~cause);
addr = gt_read(gt, GT_CommUnitIntr_ErrAddr);
printf("%s: Comm Unit irpt, cause %#x addr %#x\n",
gt->gt_dev.dv_xname, cause, addr);
cause &= GT_CommUnitIntr_DFLT;
if (cause == 0)
return 0;
mask = 0x7;
for (i=0; i<7; i++) {
if (cause & mask) {
printf("%s: Comm Unit %s:", gt->gt_dev.dv_xname,
gt_comm_subunit_name[i]);
if (cause & 1)
printf(" AddrMiss");
if (cause & 2)
printf(" AccProt");
if (cause & 4)
printf(" WrProt");
printf("\n");
}
cause >>= 4;
}
return 1;
}
void
gt_watchdog_init(struct gt_softc *gt)
{
u_int32_t mpp_watchdog = GT_MPP_WATCHDOG; /* from config */
u_int32_t r;
u_int32_t cfgbits;
u_int32_t mppbits;
u_int32_t mppmask=0;
u_int32_t regoff;
unsigned int omsr;
printf("%s: watchdog", gt->gt_dev.dv_xname);
if (mpp_watchdog == 0) {
printf(" not configured\n");
return;
}
#if 0
if (afw_wdog_ctl == 1) {
printf(" admin disabled\n");
return;
}
#endif
omsr = extintr_disable();
/*
* if firmware started watchdog, we disable and start
* from scratch to get it in a known state.
*
* on GT-64260A we always see 0xffffffff
* in both the GT_WDOG_Config_Enb and GT_WDOG_Value regsiters.
* Use AFW-supplied flag to determine run state.
*/
r = gt_read(gt, GT_WDOG_Config);
if (r != ~0) {
if ((r & GT_WDOG_Config_Enb) != 0) {
gt_write(gt, GT_WDOG_Config,
(GT_WDOG_Config_Ctl1a | GT_WDOG_Preset_DFLT));
gt_write(gt, GT_WDOG_Config,
(GT_WDOG_Config_Ctl1b | GT_WDOG_Preset_DFLT));
}
} else {
#if 0
if (afw_wdog_state == 1) {
gt_write(gt, GT_WDOG_Config,
(GT_WDOG_Config_Ctl1a | GT_WDOG_Preset_DFLT));
gt_write(gt, GT_WDOG_Config,
(GT_WDOG_Config_Ctl1b | GT_WDOG_Preset_DFLT));
}
#endif
}
/*
* "the watchdog timer can be activated only after
* configuring two MPP pins to act as WDE and WDNMI"
*/
mppbits = 0;
cfgbits = 0x3;
for (regoff = GT_MPP_Control0; regoff <= GT_MPP_Control3; regoff += 4) {
if ((mpp_watchdog & cfgbits) == cfgbits) {
mppbits = 0x99;
mppmask = 0xff;
break;
}
cfgbits <<= 2;
if ((mpp_watchdog & cfgbits) == cfgbits) {
mppbits = 0x9900;
mppmask = 0xff00;
break;
}
cfgbits <<= 6; /* skip unqualified bits */
}
if (mppbits == 0) {
printf(" config error\n");
extintr_restore(omsr);
return;
}
r = gt_read(gt, regoff);
r &= ~mppmask;
r |= mppbits;
gt_write(gt, regoff, r);
printf(" mpp %#x %#x", regoff, mppbits);
gt_write(gt, GT_WDOG_Value, GT_WDOG_NMI_DFLT);
gt_write(gt, GT_WDOG_Config,
(GT_WDOG_Config_Ctl1a | GT_WDOG_Preset_DFLT));
gt_write(gt, GT_WDOG_Config,
(GT_WDOG_Config_Ctl1b | GT_WDOG_Preset_DFLT));
r = gt_read(gt, GT_WDOG_Config),
printf(" status %#x,%#x: %s",
r, gt_read(gt, GT_WDOG_Value),
((r & GT_WDOG_Config_Enb) != 0) ? "enabled" : "botch");
if ((r & GT_WDOG_Config_Enb) != 0) {
register_t hid0;
gt_watchdog_sc = gt; /* enabled */
gt_watchdog_state = 1;
/*
* configure EMCP in HID0 in case it's not already set
*/
__asm __volatile("sync":::"memory");
hid0 = mfspr(SPR_HID0);
if ((hid0 & HID0_EMCP) == 0) {
hid0 |= HID0_EMCP;
__asm __volatile("sync":::"memory"); mtspr(SPR_HID0, hid0);
__asm __volatile("sync":::"memory"); hid0 = mfspr(SPR_HID0);
printf(", EMCP set");
}
void
gt_attach_common(struct gt_softc *gt)
{
uint32_t cpucfg, cpumode, cpumstr;
#ifdef DEBUG
uint32_t loaddr, hiaddr;
#endif
gtfound = 1;
cpumode = gt_read(gt, GT_CPU_Mode);
aprint_normal(": id %d", GT_CPUMode_MultiGTID_GET(cpumode));
if (cpumode & GT_CPUMode_MultiGT)
aprint_normal (" (multi)");
switch (GT_CPUMode_CPUType_GET(cpumode)) {
case 4: aprint_normal(", 60x bus"); break;
case 5: aprint_normal(", MPX bus"); break;
default: aprint_normal(", %#x(?) bus", GT_CPUMode_CPUType_GET(cpumode)); break;
}
cpumstr = gt_read(gt, GT_CPU_Master_Ctl);
cpumstr &= ~(GT_CPUMstrCtl_CleanBlock|GT_CPUMstrCtl_FlushBlock);
#if 0
cpumstr |= GT_CPUMstrCtl_CleanBlock|GT_CPUMstrCtl_FlushBlock;
#endif
gt_write(gt, GT_CPU_Master_Ctl, cpumstr);
switch (cpumstr & (GT_CPUMstrCtl_CleanBlock|GT_CPUMstrCtl_FlushBlock)) {
case 0: break;
case GT_CPUMstrCtl_CleanBlock: aprint_normal(", snoop=clean"); break;
case GT_CPUMstrCtl_FlushBlock: aprint_normal(", snoop=flush"); break;
case GT_CPUMstrCtl_CleanBlock|GT_CPUMstrCtl_FlushBlock:
aprint_normal(", snoop=clean&flush"); break;
}
aprint_normal(" wdog=%#x,%#x\n",
gt_read(gt, GT_WDOG_Config),
gt_read(gt, GT_WDOG_Value));
#if DEBUG
loaddr = GT_LowAddr_GET(gt_read(gt, GT_SCS0_Low_Decode));
hiaddr = GT_HighAddr_GET(gt_read(gt, GT_SCS0_High_Decode));
aprint_normal("%s: scs[0]=%#10x-%#10x\n", gt->gt_dev.dv_xname, loaddr, hiaddr);
loaddr = GT_LowAddr_GET(gt_read(gt, GT_SCS1_Low_Decode));
hiaddr = GT_HighAddr_GET(gt_read(gt, GT_SCS1_High_Decode));
aprint_normal("%s: scs[1]=%#10x-%#10x\n", gt->gt_dev.dv_xname, loaddr, hiaddr);
loaddr = GT_LowAddr_GET(gt_read(gt, GT_SCS2_Low_Decode));
hiaddr = GT_HighAddr_GET(gt_read(gt, GT_SCS2_High_Decode));
aprint_normal("%s: scs[2]=%#10x-%#10x\n", gt->gt_dev.dv_xname, loaddr, hiaddr);
loaddr = GT_LowAddr_GET(gt_read(gt, GT_SCS3_Low_Decode));
hiaddr = GT_HighAddr_GET(gt_read(gt, GT_SCS3_High_Decode));
aprint_normal("%s: scs[3]=%#10x-%#10x\n", gt->gt_dev.dv_xname, loaddr, hiaddr);
loaddr = GT_LowAddr_GET(gt_read(gt, GT_CS0_Low_Decode));
hiaddr = GT_HighAddr_GET(gt_read(gt, GT_CS0_High_Decode));
aprint_normal("%s: cs[0]=%#10x-%#10x\n", gt->gt_dev.dv_xname, loaddr, hiaddr);
loaddr = GT_LowAddr_GET(gt_read(gt, GT_CS1_Low_Decode));
hiaddr = GT_HighAddr_GET(gt_read(gt, GT_CS1_High_Decode));
aprint_normal("%s: cs[1]=%#10x-%#10x\n", gt->gt_dev.dv_xname, loaddr, hiaddr);
loaddr = GT_LowAddr_GET(gt_read(gt, GT_CS2_Low_Decode));
hiaddr = GT_HighAddr_GET(gt_read(gt, GT_CS2_High_Decode));
aprint_normal("%s: cs[2]=%#10x-%#10x\n", gt->gt_dev.dv_xname, loaddr, hiaddr);
loaddr = GT_LowAddr_GET(gt_read(gt, GT_CS3_Low_Decode));
hiaddr = GT_HighAddr_GET(gt_read(gt, GT_CS3_High_Decode));
aprint_normal("%s: cs[3]=%#10x-%#10x\n", gt->gt_dev.dv_xname, loaddr, hiaddr);
loaddr = GT_LowAddr_GET(gt_read(gt, GT_BootCS_Low_Decode));
hiaddr = GT_HighAddr_GET(gt_read(gt, GT_BootCS_High_Decode));
aprint_normal("%s: bootcs=%#10x-%#10x\n", gt->gt_dev.dv_xname, loaddr, hiaddr);
loaddr = GT_LowAddr_GET(gt_read(gt, GT_PCI0_IO_Low_Decode));
hiaddr = GT_HighAddr_GET(gt_read(gt, GT_PCI0_IO_High_Decode));
aprint_normal("%s: pci0io=%#10x-%#10x ", gt->gt_dev.dv_xname, loaddr, hiaddr);
loaddr = gt_read(gt, GT_PCI0_IO_Remap);
aprint_normal("remap=%#010x\n", loaddr);
loaddr = GT_LowAddr_GET(gt_read(gt, GT_PCI0_Mem0_Low_Decode));
hiaddr = GT_HighAddr_GET(gt_read(gt, GT_PCI0_Mem0_High_Decode));
aprint_normal("%s: pci0mem[0]=%#10x-%#10x ", gt->gt_dev.dv_xname, loaddr, hiaddr);
loaddr = gt_read(gt, GT_PCI0_Mem0_Remap_Low);
hiaddr = gt_read(gt, GT_PCI0_Mem0_Remap_High);
aprint_normal("remap=%#010x.%#010x\n", hiaddr, loaddr);
loaddr = GT_LowAddr_GET(gt_read(gt, GT_PCI0_Mem1_Low_Decode));
hiaddr = GT_HighAddr_GET(gt_read(gt, GT_PCI0_Mem1_High_Decode));
aprint_normal("%s: pci0mem[1]=%#10x-%#10x ", gt->gt_dev.dv_xname, loaddr, hiaddr);
loaddr = gt_read(gt, GT_PCI0_Mem1_Remap_Low);
hiaddr = gt_read(gt, GT_PCI0_Mem1_Remap_High);
aprint_normal("remap=%#010x.%#010x\n", hiaddr, loaddr);
loaddr = GT_LowAddr_GET(gt_read(gt, GT_PCI0_Mem2_Low_Decode));
hiaddr = GT_HighAddr_GET(gt_read(gt, GT_PCI0_Mem2_High_Decode));
aprint_normal("%s: pci0mem[2]=%#10x-%#10x ", gt->gt_dev.dv_xname, loaddr, hiaddr);
loaddr = gt_read(gt, GT_PCI0_Mem2_Remap_Low);
hiaddr = gt_read(gt, GT_PCI0_Mem2_Remap_High);
aprint_normal("remap=%#010x.%#010x\n", hiaddr, loaddr);
loaddr = GT_LowAddr_GET(gt_read(gt, GT_PCI0_Mem3_Low_Decode));
hiaddr = GT_HighAddr_GET(gt_read(gt, GT_PCI0_Mem3_High_Decode));
aprint_normal("%s: pci0mem[3]=%#10x-%#10x ", gt->gt_dev.dv_xname, loaddr, hiaddr);
loaddr = gt_read(gt, GT_PCI0_Mem3_Remap_Low);
hiaddr = gt_read(gt, GT_PCI0_Mem3_Remap_High);
aprint_normal("remap=%#010x.%#010x\n", hiaddr, loaddr);
loaddr = GT_LowAddr_GET(gt_read(gt, GT_PCI1_IO_Low_Decode));
hiaddr = GT_HighAddr_GET(gt_read(gt, GT_PCI1_IO_High_Decode));
aprint_normal("%s: pci1io=%#10x-%#10x ", gt->gt_dev.dv_xname, loaddr, hiaddr);
loaddr = gt_read(gt, GT_PCI1_IO_Remap);
aprint_normal("remap=%#010x\n", loaddr);
loaddr = GT_LowAddr_GET(gt_read(gt, GT_PCI1_Mem0_Low_Decode));
hiaddr = GT_HighAddr_GET(gt_read(gt, GT_PCI1_Mem0_High_Decode));
aprint_normal("%s: pci1mem[0]=%#10x-%#10x ", gt->gt_dev.dv_xname, loaddr, hiaddr);
loaddr = gt_read(gt, GT_PCI1_Mem0_Remap_Low);
hiaddr = gt_read(gt, GT_PCI1_Mem0_Remap_High);
aprint_normal("remap=%#010x.%#010x\n", hiaddr, loaddr);
loaddr = GT_LowAddr_GET(gt_read(gt, GT_PCI1_Mem1_Low_Decode));
hiaddr = GT_HighAddr_GET(gt_read(gt, GT_PCI1_Mem1_High_Decode));
aprint_normal("%s: pci1mem[1]=%#10x-%#10x ", gt->gt_dev.dv_xname, loaddr, hiaddr);
loaddr = gt_read(gt, GT_PCI1_Mem1_Remap_Low);
hiaddr = gt_read(gt, GT_PCI1_Mem1_Remap_High);
aprint_normal("remap=%#010x.%#010x\n", hiaddr, loaddr);
loaddr = GT_LowAddr_GET(gt_read(gt, GT_PCI1_Mem2_Low_Decode));
hiaddr = GT_HighAddr_GET(gt_read(gt, GT_PCI1_Mem2_High_Decode));
aprint_normal("%s: pci1mem[2]=%#10x-%#10x ", gt->gt_dev.dv_xname, loaddr, hiaddr);
loaddr = gt_read(gt, GT_PCI1_Mem2_Remap_Low);
hiaddr = gt_read(gt, GT_PCI1_Mem2_Remap_High);
aprint_normal("remap=%#010x.%#010x\n", hiaddr, loaddr);
loaddr = GT_LowAddr_GET(gt_read(gt, GT_PCI1_Mem3_Low_Decode));
hiaddr = GT_HighAddr_GET(gt_read(gt, GT_PCI1_Mem3_High_Decode));
aprint_normal("%s: pci1mem[3]=%#10x-%#10x ", gt->gt_dev.dv_xname, loaddr, hiaddr);
loaddr = gt_read(gt, GT_PCI1_Mem3_Remap_Low);
hiaddr = gt_read(gt, GT_PCI1_Mem3_Remap_High);
aprint_normal("remap=%#010x.%#010x\n", hiaddr, loaddr);
loaddr = GT_LowAddr_GET(gt_read(gt, GT_Internal_Decode));
aprint_normal("%s: internal=%#10x-%#10x\n", gt->gt_dev.dv_xname,
loaddr, loaddr+256*1024);
loaddr = GT_LowAddr_GET(gt_read(gt, GT_CPU0_Low_Decode));
hiaddr = GT_HighAddr_GET(gt_read(gt, GT_CPU0_High_Decode));
aprint_normal("%s: cpu0=%#10x-%#10x\n", gt->gt_dev.dv_xname, loaddr, hiaddr);
loaddr = GT_LowAddr_GET(gt_read(gt, GT_CPU1_Low_Decode));
hiaddr = GT_HighAddr_GET(gt_read(gt, GT_CPU1_High_Decode));
aprint_normal("%s: cpu1=%#10x-%#10x", gt->gt_dev.dv_xname, loaddr, hiaddr);
#endif
aprint_normal("%s:", gt->gt_dev.dv_xname);
cpucfg = gt_read(gt, GT_CPU_Cfg);
cpucfg |= GT_CPUCfg_ConfSBDis; /* per errata #46 */
cpucfg |= GT_CPUCfg_AACKDelay; /* per restriction #18 */
gt_write(gt, GT_CPU_Cfg, cpucfg);
if (cpucfg & GT_CPUCfg_Pipeline)
aprint_normal(" pipeline");
if (cpucfg & GT_CPUCfg_AACKDelay)
aprint_normal(" aack-delay");
if (cpucfg & GT_CPUCfg_RdOOO)
aprint_normal(" read-ooo");
if (cpucfg & GT_CPUCfg_IOSBDis)
aprint_normal(" io-sb-dis");
if (cpucfg & GT_CPUCfg_ConfSBDis)
aprint_normal(" conf-sb-dis");
if (cpucfg & GT_CPUCfg_ClkSync)
aprint_normal(" clk-sync");
aprint_normal("\n");
gt_init_hostid(gt);
gt_watchdog_init(gt);
gt_init_interrupt(gt);
#ifdef GT_ECC
gt_ecc_intr_enb(gt);
#endif
gt_comm_intr_enb(gt);
gt_devbus_intr_enb(gt);
gt_watchdog_disable();
config_search(gt_cfsearch, >->gt_dev, NULL);
gt_watchdog_service();
gt_watchdog_enable();
}
