static void h4_block_received(void){
read_pos += bytes_to_read;
// act
switch (h4_state) {
case H4_W4_PACKET_TYPE:
switch (hci_packet[0]) {
case HCI_ACL_DATA_PACKET:
h4_state = H4_W4_ACL_HEADER;
bytes_to_read = HCI_ACL_HEADER_SIZE;
break;
case HCI_EVENT_PACKET:
h4_state = H4_W4_EVENT_HEADER;
bytes_to_read = HCI_EVENT_HEADER_SIZE;
break;
default:
log_error("h4_process: invalid packet type 0x%02x", hci_packet[0]);
read_pos = 0;
h4_state = H4_W4_PACKET_TYPE;
bytes_to_read = 1;
break;
}
break;
case H4_W4_EVENT_HEADER:
bytes_to_read = hci_packet[2];
if (bytes_to_read == 0) {
h4_state = H4_PACKET_RECEIVED;
break;
}
h4_state = H4_W4_PAYLOAD;
break;
case H4_W4_ACL_HEADER:
bytes_to_read = READ_BT_16( hci_packet, 3);
if (bytes_to_read == 0) {
h4_state = H4_PACKET_RECEIVED;
break;
}
h4_state = H4_W4_PAYLOAD;
break;
case H4_W4_PAYLOAD:
h4_state = H4_PACKET_RECEIVED;
bytes_to_read = 0;
// trigger run loop
embedded_trigger();
break;
default:
bytes_to_read = 0;
break;
}
// read next block
if (bytes_to_read) {
hal_uart_dma_receive_block(&hci_packet[read_pos], bytes_to_read);
}
}
void ehcill_uart_dma_receive_block(uint8_t *buffer, uint16_t size){
if (!ehcill_sleep_mode_active()){
ehcill_defer_rx_size = 0;
hal_uart_dma_receive_block(buffer, size);
return;
}
// store receive request for later
ehcill_defer_rx_buffer = buffer;
ehcill_defer_rx_size = size;
}
static void ehcill_reactivate_rx(void){
if (!ehcill_defer_rx_size){
log_error("EHCILL: NO RX REQUEST PENDING");
return;
}
#ifdef LOG_EHCILL
log_info ("EHCILL: Re-activate rx");
#endif
// receive request, clears RTS
int rx_size = ehcill_defer_rx_size;
ehcill_defer_rx_size = 0;
hal_uart_dma_receive_block(ehcill_defer_rx_buffer, rx_size);
}
static void h4_init_sm(void){
h4_state = H4_W4_PACKET_TYPE;
read_pos = 0;
bytes_to_read = 1;
hal_uart_dma_receive_block(hci_packet, bytes_to_read);
}
static void h4_block_received(void){
read_pos += bytes_to_read;
// act
switch (h4_state) {
case H4_W4_PACKET_TYPE:
switch (hci_packet[0]) {
case HCI_EVENT_PACKET:
h4_state = H4_W4_EVENT_HEADER;
bytes_to_read = HCI_EVENT_HEADER_SIZE;
break;
case HCI_ACL_DATA_PACKET:
h4_state = H4_W4_ACL_HEADER;
bytes_to_read = HCI_ACL_HEADER_SIZE;
break;
case HCI_SCO_DATA_PACKET:
h4_state = H4_W4_SCO_HEADER;
bytes_to_read = HCI_SCO_HEADER_SIZE;
break;
default:
log_error("h4_process: invalid packet type 0x%02x", hci_packet[0]);
h4_init_sm();
return;
}
break;
case H4_W4_EVENT_HEADER:
bytes_to_read = hci_packet[2];
if (bytes_to_read == 0) {
h4_state = H4_PACKET_RECEIVED;
break;
}
h4_state = H4_W4_PAYLOAD;
break;
case H4_W4_ACL_HEADER:
bytes_to_read = little_endian_read_16( hci_packet, 3);
// check ACL length
if (HCI_ACL_HEADER_SIZE + bytes_to_read > HCI_PACKET_BUFFER_SIZE){
log_error("h4_process: invalid ACL payload len %u - only space for %u", bytes_to_read, HCI_PACKET_BUFFER_SIZE - HCI_ACL_HEADER_SIZE);
h4_init_sm();
return;
}
if (bytes_to_read == 0) {
h4_state = H4_PACKET_RECEIVED;
break;
}
h4_state = H4_W4_PAYLOAD;
break;
case H4_W4_SCO_HEADER:
bytes_to_read = hci_packet[3];
if (bytes_to_read == 0) {
h4_state = H4_PACKET_RECEIVED;
break;
}
h4_state = H4_W4_PAYLOAD;
break;
case H4_W4_PAYLOAD:
h4_state = H4_PACKET_RECEIVED;
bytes_to_read = 0;
// trigger run loop
btstack_run_loop_embedded_trigger();
break;
default:
bytes_to_read = 0;
break;
}
// read next block
if (bytes_to_read) {
hal_uart_dma_receive_block(&hci_packet[read_pos], bytes_to_read);
}
}
