Exemplos de hi6220_clk_register_divider em C++ (Cpp)

Exemplo n.º 1

Arquivo: clk-hi6220.c Projeto: 020gzh/linux

static void __init hi6220_clk_power_init(struct device_node *np)
{
	struct hisi_clock_data *clk_data;

	clk_data = hisi_clk_init(np, HI6220_POWER_NR_CLKS);
	if (!clk_data)
		return;

	hisi_clk_register_gate(hi6220_gate_clks_power,
				ARRAY_SIZE(hi6220_gate_clks_power), clk_data);

	hi6220_clk_register_divider(hi6220_div_clks_power,
				ARRAY_SIZE(hi6220_div_clks_power), clk_data);
}

Exemplo n.º 2

Arquivo: clk-hi6220.c Projeto: 020gzh/linux

static void __init hi6220_clk_media_init(struct device_node *np)
{
	struct hisi_clock_data *clk_data;

	clk_data = hisi_clk_init(np, HI6220_MEDIA_NR_CLKS);
	if (!clk_data)
		return;

	hisi_clk_register_gate_sep(hi6220_separated_gate_clks_media,
				ARRAY_SIZE(hi6220_separated_gate_clks_media), clk_data);

	hisi_clk_register_mux(hi6220_mux_clks_media,
				ARRAY_SIZE(hi6220_mux_clks_media), clk_data);

	hi6220_clk_register_divider(hi6220_div_clks_media,
				ARRAY_SIZE(hi6220_div_clks_media), clk_data);
}

Exemplo n.º 3

Arquivo: clk-hi6220.c Projeto: imikushin/estuary-kernel

static void __init hi6220_clk_sys_init(struct device_node *np)
{
	struct hisi_clock_data *clk_data;

	clk_data = hisi_clk_init(np, HI6220_SYS_NR_CLKS);
	if (!clk_data)
		return;

	hisi_clk_register_gate(hi6220_reset_clks,
			ARRAY_SIZE(hi6220_reset_clks), clk_data);

	hisi_clk_register_gate_sep(hi6220_separated_gate_clks_sys,
			ARRAY_SIZE(hi6220_separated_gate_clks_sys), clk_data);

	hisi_clk_register_mux(hi6220_mux_clks_sys,
			ARRAY_SIZE(hi6220_mux_clks_sys), clk_data);

	hi6220_clk_register_divider(hi6220_div_clks_sys,
			ARRAY_SIZE(hi6220_div_clks_sys), clk_data);
}

Exemplo n.º 4

Arquivo: clk-hi6220.c Projeto: joyxu/linux

static void __init hi6220_clk_sys_init(struct device_node *np)
{
	struct hisi_clock_data *clk_data;

	clk_data = hisi_clk_init(np, HI6220_SYS_NR_CLKS);
	if (!clk_data)
		return;

	hisi_clk_register_gate_sep(hi6220_separated_gate_clks_sys,
			ARRAY_SIZE(hi6220_separated_gate_clks_sys), clk_data);

	hisi_clk_register_mux(hi6220_mux_clks_sys,
			ARRAY_SIZE(hi6220_mux_clks_sys), clk_data);

	hi6220_clk_register_divider(hi6220_div_clks_sys,
			ARRAY_SIZE(hi6220_div_clks_sys), clk_data);

	if (!clk_data_ao)
		return;

	/* enable high speed clock on UART1 mux */
	clk_set_parent(clk_data->clk_data.clks[HI6220_UART1_SRC],
			clk_data_ao->clk_data.clks[HI6220_150M]);
}