void free_initmem(void)
{
const unsigned long text_delta = MEM_SV_START - PAGE_OFFSET;
/*
* Evict the cache on all cores to avoid incoherence.
* We are guaranteed that no one will touch the init pages any more.
*/
homecache_evict(&cpu_cacheable_map);
/* Free the data pages that we won't use again after init. */
free_init_pages("unused kernel data",
(unsigned long)__init_begin,
(unsigned long)__init_end);
/*
* Free the pages mapped from 0xc0000000 that correspond to code
* pages from MEM_SV_START that we won't use again after init.
*/
free_init_pages("unused kernel text",
(unsigned long)_sinittext - text_delta,
(unsigned long)_einittext - text_delta);
/* Do a global TLB flush so everyone sees the changes. */
flush_tlb_all();
}
SYSCALL_DEFINE3(cacheflush, unsigned long, addr, unsigned long, len,
unsigned long, flags)
{
if (flags & DCACHE)
homecache_evict(cpumask_of(smp_processor_id()));
if (flags & ICACHE)
flush_remote(0, HV_FLUSH_EVICT_L1I, mm_cpumask(current->mm),
0, 0, 0, NULL, NULL, 0);
return 0;
}
void free_initmem(void)
{
const unsigned long text_delta = MEM_SV_INTRPT - PAGE_OFFSET;
/*
* Evict the dirty initdata on the boot cpu, evict the w1data
* wherever it's homed, and evict all the init code everywhere.
* We are guaranteed that no one will touch the init pages any
* more, and although other cpus may be touching the w1data,
* we only actually change the caching on tile64, which won't
* be keeping local copies in the other tiles' caches anyway.
*/
homecache_evict(&cpu_cacheable_map);
/* Free the data pages that we won't use again after init. */
free_init_pages("unused kernel data",
(unsigned long)_sinitdata,
(unsigned long)_einitdata);
/*
* Free the pages mapped from 0xc0000000 that correspond to code
* pages from MEM_SV_INTRPT that we won't use again after init.
*/
free_init_pages("unused kernel text",
(unsigned long)_sinittext - text_delta,
(unsigned long)_einittext - text_delta);
#if !CHIP_HAS_COHERENT_LOCAL_CACHE()
/*
* Upgrade the .w1data section to globally cached.
* We don't do this on tilepro, since the cache architecture
* pretty much makes it irrelevant, and in any case we end
* up having racing issues with other tiles that may touch
* the data after we flush the cache but before we update
* the PTEs and flush the TLBs, causing sharer shootdowns
* later. Even though this is to clean data, it seems like
* an unnecessary complication.
*/
mark_w1data_ro();
#endif
/* Do a global TLB flush so everyone sees the changes. */
flush_tlb_all();
}
