static sw_error_t
horus_hw_init(a_uint32_t dev_id, ssdk_init_cfg *cfg)
{
hsl_dev_t *pdev = NULL;
a_uint32_t port_id;
a_uint32_t data;
sw_error_t rv;
pdev = hsl_dev_ptr_get(dev_id);
if (NULL == pdev)
{
return SW_NOT_INITIALIZED;
}
for (port_id = 0; port_id < pdev->nr_ports; port_id++)
{
if (port_id == pdev->cpu_port_nr)
{
continue;
}
HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
(a_uint8_t *) (&data), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 1, data);
HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
(a_uint8_t *) (&data), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
}
return SW_OK;
}
static sw_error_t
isis_dev_init(a_uint32_t dev_id, hsl_init_mode cpu_mode)
{
a_uint32_t entry;
sw_error_t rv;
hsl_dev_t *pdev = NULL;
pdev = hsl_dev_ptr_get(dev_id);
if (pdev == NULL)
return SW_NOT_INITIALIZED;
HSL_REG_FIELD_GET(rv, dev_id, MASK_CTL, 0, DEVICE_ID,
(a_uint8_t *) (&entry), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
if (S17_DEVICE_ID == entry) {
pdev->nr_ports = 7;
pdev->nr_phy = 5;
pdev->cpu_port_nr = 0;
pdev->nr_vlans = 4096;
pdev->hw_vlan_query = A_TRUE;
pdev->nr_queue = 6;
pdev->cpu_mode = cpu_mode;
} else {
pdev->nr_ports = 6;
pdev->nr_phy = 5;
pdev->cpu_port_nr = 0;
pdev->nr_vlans = 4096;
pdev->hw_vlan_query = A_TRUE;
pdev->nr_queue = 6;
pdev->cpu_mode = cpu_mode;
}
return SW_OK;
}
static sw_error_t
garuda_dev_init(a_uint32_t dev_id, hsl_init_mode cpu_mode)
{
hsl_dev_t *pdev = NULL;
pdev = hsl_dev_ptr_get(dev_id);
if (pdev == NULL)
return SW_NOT_INITIALIZED;
pdev->nr_ports = 6;
pdev->nr_phy = 5;
pdev->cpu_port_nr = 0;
pdev->nr_vlans = 4096;
pdev->hw_vlan_query = A_TRUE;
pdev->nr_queue = 4;
pdev->cpu_mode = cpu_mode;
return SW_OK;
}
static sw_error_t
_shiva_igmp_mld_entry_queue_set(a_uint32_t dev_id, a_bool_t enable, a_uint32_t queue)
{
sw_error_t rv;
a_uint32_t entry;
hsl_dev_t *p_dev;
HSL_DEV_ID_CHECK(dev_id);
HSL_REG_ENTRY_GET(rv, dev_id, QM_CTL, 0,
(a_uint8_t *) (&entry), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
if (A_TRUE == enable)
{
SW_SET_REG_BY_FIELD(QM_CTL, IGMP_PRI_EN, 1, entry);
SW_RTN_ON_NULL(p_dev = hsl_dev_ptr_get(dev_id));
if (queue >= p_dev->nr_queue)
{
return SW_BAD_PARAM;
}
SW_SET_REG_BY_FIELD(QM_CTL, IGMP_PRI, queue, entry);
}
else if (A_FALSE == enable)
{
SW_SET_REG_BY_FIELD(QM_CTL, IGMP_PRI_EN, 0, entry);
SW_SET_REG_BY_FIELD(QM_CTL, IGMP_PRI, 0, entry);
}
else
{
return SW_BAD_PARAM;
}
HSL_REG_ENTRY_SET(rv, dev_id, QM_CTL, 0,
(a_uint8_t *) (&entry), sizeof (a_uint32_t));
return rv;
}
static sw_error_t
isis_hw_init(a_uint32_t dev_id, ssdk_init_cfg *cfg)
{
hsl_dev_t *pdev = NULL;
a_uint32_t port_id;
a_uint32_t data;
sw_error_t rv;
pdev = hsl_dev_ptr_get(dev_id);
if (NULL == pdev) {
return SW_NOT_INITIALIZED;
}
/* Set default FDB hash mode as CRC10 */
data = 1;
HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL0, 0, HASH_MODE,
(a_uint8_t *) (&data), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
for (port_id = 0; port_id < pdev->nr_ports; port_id++) {
if (port_id == pdev->cpu_port_nr) {
continue;
}
HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
(a_uint8_t *) (&data), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 1, data);
HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
(a_uint8_t *) (&data), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
}
return SW_OK;
}
/* For isis there are five internal PHY devices and seven MAC devices.
MAC0 always connect to external MAC device.
PHY4 can connect to MAC5 or external MAC device.
MAC6 always connect to external devices.
MAC1..MAC4 connect to internal PHY0..PHY3.
*/
static sw_error_t
isis_portproperty_init(a_uint32_t dev_id, hsl_init_mode mode)
{
hsl_port_prop_t p_type;
hsl_dev_t *pdev = NULL;
fal_port_t port_id;
pdev = hsl_dev_ptr_get(dev_id);
if (pdev == NULL)
return SW_NOT_INITIALIZED;
/* for port property set, SSDK should not generate some limitations */
for (port_id = 0; port_id < pdev->nr_ports; port_id++)
{
hsl_port_prop_portmap_set(dev_id, port_id);
for (p_type = HSL_PP_PHY; p_type < HSL_PP_BUTT; p_type++)
{
if (HSL_NO_CPU == mode)
{
SW_RTN_ON_ERROR(hsl_port_prop_set(dev_id, port_id, p_type));
continue;
}
switch (p_type)
{
case HSL_PP_PHY:
/* Only port0/port6 without PHY device */
if ((port_id != pdev->cpu_port_nr)
&& (port_id != pdev->nr_ports - 1))
{
SW_RTN_ON_ERROR(hsl_port_prop_set(dev_id, port_id, p_type));
}
break;
case HSL_PP_INCL_CPU:
/* include cpu port but exclude wan port in some cases */
/* but which port is wan port, we are no meaning */
SW_RTN_ON_ERROR(hsl_port_prop_set(dev_id, port_id, p_type));
break;
case HSL_PP_EXCL_CPU:
/* exclude cpu port and wan port in some cases */
/* which port is wan port, we are no meaning but port0 is
always CPU port */
if (port_id != pdev->cpu_port_nr)
{
SW_RTN_ON_ERROR(hsl_port_prop_set(dev_id, port_id, p_type));
}
break;
default:
break;
}
}
if (HSL_NO_CPU == mode)
{
SW_RTN_ON_ERROR(hsl_port_prop_set_phyid
(dev_id, port_id, port_id + 1));
}
else
{
if (port_id != pdev->cpu_port_nr)
{
SW_RTN_ON_ERROR(hsl_port_prop_set_phyid
(dev_id, port_id, port_id - 1));
}
}
}
return SW_OK;
}
static sw_error_t
garuda_portproperty_init(a_uint32_t dev_id, hsl_init_mode mode)
{
hsl_port_prop_t p_type;
hsl_dev_t *pdev = NULL;
fal_port_t port_id;
pdev = hsl_dev_ptr_get(dev_id);
if (pdev == NULL)
return SW_NOT_INITIALIZED;
for (port_id = 0; port_id < pdev->nr_ports; port_id++)
{
hsl_port_prop_portmap_set(dev_id, port_id);
for (p_type = HSL_PP_PHY; p_type < HSL_PP_BUTT; p_type++)
{
if (HSL_NO_CPU == mode)
{
SW_RTN_ON_ERROR(hsl_port_prop_set(dev_id, port_id, p_type));
continue;
}
switch (p_type)
{
case HSL_PP_PHY:
if (HSL_CPU_1 != mode)
{
if ((port_id != pdev->cpu_port_nr)
&& (port_id != (pdev->nr_ports -1)))
{
SW_RTN_ON_ERROR(hsl_port_prop_set(dev_id, port_id, p_type));
}
}
else
{
if (port_id != pdev->cpu_port_nr)
{
SW_RTN_ON_ERROR(hsl_port_prop_set(dev_id, port_id, p_type));
}
}
break;
case HSL_PP_INCL_CPU:
/* include cpu port but exclude wan port in some cases */
if (!((HSL_CPU_2 == mode) && (port_id == (pdev->nr_ports - 1))))
SW_RTN_ON_ERROR(hsl_port_prop_set(dev_id, port_id, p_type));
break;
case HSL_PP_EXCL_CPU:
/* exclude cpu port and wan port in some cases */
if ((port_id != pdev->cpu_port_nr)
&& (!((HSL_CPU_2 == mode) && (port_id == (pdev->nr_ports - 1)))))
SW_RTN_ON_ERROR(hsl_port_prop_set(dev_id, port_id, p_type));
break;
default:
break;
}
}
if (HSL_NO_CPU == mode)
{
SW_RTN_ON_ERROR(hsl_port_prop_set_phyid
(dev_id, port_id, port_id + 1));
}
else
{
if (port_id != pdev->cpu_port_nr)
{
SW_RTN_ON_ERROR(hsl_port_prop_set_phyid
(dev_id, port_id, port_id - 1));
}
}
}
return SW_OK;
}
static sw_error_t
garuda_hw_init(a_uint32_t dev_id, ssdk_init_cfg *cfg)
{
garuda_init_spec_cfg *garuda_init_cfg = NULL;
hsl_dev_t *pdev = NULL;
hsl_init_mode cpu_mode;
a_uint32_t port_id;
a_uint32_t data;
sw_error_t rv;
pdev = hsl_dev_ptr_get(dev_id);
if (NULL == pdev)
{
return SW_NOT_INITIALIZED;
}
cpu_mode = cfg->cpu_mode;
HSL_REG_ENTRY_GET(rv, dev_id, POSTRIP, 0,
(a_uint8_t *) (&data), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
/* phy pll on */
SW_SET_REG_BY_FIELD(POSTRIP, PHY_PLL_ON, 1, data);
garuda_init_cfg = (garuda_init_spec_cfg* )(cfg->chip_spec_cfg);
if (!garuda_init_cfg)
{
return SW_BAD_PARAM;
}
/* delay */
if (A_TRUE == garuda_init_cfg->rx_delay_s1)
{
SW_SET_REG_BY_FIELD(POSTRIP, RXDELAY_S1, 1, data);
}
else
{
SW_SET_REG_BY_FIELD(POSTRIP, RXDELAY_S1, 0, data);
}
if (A_TRUE == garuda_init_cfg->rx_delay_s0)
{
SW_SET_REG_BY_FIELD(POSTRIP, RXDELAY_S0, 1, data);
}
else
{
SW_SET_REG_BY_FIELD(POSTRIP, RXDELAY_S0, 0, data);
}
if (A_TRUE == garuda_init_cfg->tx_delay_s1)
{
SW_SET_REG_BY_FIELD(POSTRIP, TXDELAY_S1, 1, data);
}
else
{
SW_SET_REG_BY_FIELD(POSTRIP, TXDELAY_S1, 0, data);
}
if (A_TRUE == garuda_init_cfg->tx_delay_s0)
{
SW_SET_REG_BY_FIELD(POSTRIP, TXDELAY_S0, 1, data);
}
else
{
SW_SET_REG_BY_FIELD(POSTRIP, TXDELAY_S0, 0, data);
}
/* tx/rx delay enable */
if (A_TRUE == garuda_init_cfg->rgmii_txclk_delay)
{
SW_SET_REG_BY_FIELD(POSTRIP, RGMII_TXCLK_DELAY_EN, 1, data);
}
else
{
SW_SET_REG_BY_FIELD(POSTRIP, RGMII_TXCLK_DELAY_EN, 0, data);
}
/* tx/rx delay enable */
if (A_TRUE == garuda_init_cfg->rgmii_rxclk_delay)
{
SW_SET_REG_BY_FIELD(POSTRIP, RGMII_RXCLK_DELAY_EN, 1, data);
}
else
{
SW_SET_REG_BY_FIELD(POSTRIP, RGMII_RXCLK_DELAY_EN, 0, data);
}
/* mac5 default mode */
/*SW_SET_REG_BY_FIELD(POSTRIP, MAC5_PHY_MODE, 0, data);
SW_SET_REG_BY_FIELD(POSTRIP, MAC5_MAC_MODE, 0, data);*/
/* mac0 default phy mode */
SW_SET_REG_BY_FIELD(POSTRIP, MAC0_MAC_MODE, 0, data);
/* mac0 default rgmii mode */
SW_SET_REG_BY_FIELD(POSTRIP, MAC0_RGMII_EN, 1, data);
SW_SET_REG_BY_FIELD(POSTRIP, MAC0_GMII_EN, 0, data);
/* mac5 default disable mode */
SW_SET_REG_BY_FIELD(POSTRIP, MAC5_PHY_MODE, 0, data);
SW_SET_REG_BY_FIELD(POSTRIP, MAC5_MAC_MODE, 0, data);
/* phy default mode */
SW_SET_REG_BY_FIELD(POSTRIP, PHY4_RGMII_EN, 0, data);
SW_SET_REG_BY_FIELD(POSTRIP, PHY4_GMII_EN, 0, data);
/* modify default mode */
if (A_FALSE == garuda_init_cfg->mac0_rgmii)
{
SW_SET_REG_BY_FIELD(POSTRIP, MAC0_RGMII_EN, 0, data);
SW_SET_REG_BY_FIELD(POSTRIP, MAC0_GMII_EN, 1, data);
/*invert clock output for port0 gmii pad.*/
a_uint32_t temp;
HSL_REG_ENTRY_GET(rv, dev_id, MASK_CTL, 0,
(a_uint8_t *) (&temp), sizeof (a_uint32_t));
temp |= 1<<MASK_CTL_MII_CLK0_SEL_BOFFSET;
HSL_REG_ENTRY_SET(rv, dev_id, MASK_CTL, 0,
(a_uint8_t *) (&temp), sizeof (a_uint32_t));
}
if(HSL_CPU_2 == cpu_mode)
{
if (A_TRUE == garuda_init_cfg->mac5_rgmii)
{
SW_SET_REG_BY_FIELD(POSTRIP, PHY4_RGMII_EN, 1, data);
SW_SET_REG_BY_FIELD(POSTRIP, PHY4_GMII_EN, 0, data);
a_uint32_t phy_id = 4;
/* phy4 rgmii mode enable */
phy_dport_set(dev_id, phy_id, F1_DEBUG_PORT_RGMII_MODE, F1_DEBUG_PORT_RGMII_MODE_EN);
/* Rx delay enable */
if (A_TRUE == garuda_init_cfg->phy4_rx_delay)
{
phy_dport_set(dev_id, phy_id, F1_DEBUG_PORT_RX_DELAY, F1_DEBUG_PORT_RX_DELAY_EN);
}
else
{
phy_dport_clear(dev_id, phy_id, F1_DEBUG_PORT_RX_DELAY, F1_DEBUG_PORT_RX_DELAY_EN);
}
/* Tx delay enable */
if (A_TRUE == garuda_init_cfg->phy4_tx_delay)
{
phy_dport_set(dev_id, phy_id, F1_DEBUG_PORT_TX_DELAY, F1_DEBUG_PORT_TX_DELAY_EN);
}
else
{
phy_dport_clear(dev_id, phy_id, F1_DEBUG_PORT_TX_DELAY, F1_DEBUG_PORT_TX_DELAY_EN);
}
}
else
{
SW_SET_REG_BY_FIELD(POSTRIP, PHY4_RGMII_EN, 0, data);
SW_SET_REG_BY_FIELD(POSTRIP, PHY4_GMII_EN, 1, data);
}
}
else if (HSL_CPU_1 == cpu_mode)
{
//SW_SET_REG_BY_FIELD(POSTRIP, TXDELAY_S0, 0, data);
}
else if (HSL_CPU_1_PLUS == cpu_mode)
{
SW_SET_REG_BY_FIELD(POSTRIP, MAC5_MAC_MODE, 1, data);
}
else if (HSL_NO_CPU == cpu_mode)
{
}
HSL_REG_ENTRY_SET(rv, dev_id, POSTRIP, 0,
(a_uint8_t *) (&data), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
for (port_id = 0; port_id < pdev->nr_ports; port_id++)
{
if (port_id == pdev->cpu_port_nr)
{
continue;
}
HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
(a_uint8_t *) (&data), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 1, data);
HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
(a_uint8_t *) (&data), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
}
return SW_OK;
}
static sw_error_t
shiva_atu_sw_to_hw(a_uint32_t dev_id, const fal_fdb_entry_t * entry,
a_uint32_t reg[])
{
a_uint32_t port;
if (A_FALSE == entry->portmap_en)
{
if (A_TRUE !=
hsl_port_prop_check(dev_id, entry->port.id, HSL_PP_INCL_CPU))
{
return SW_BAD_PARAM;
}
port = 0x1UL << entry->port.id;
}
else
{
if (A_FALSE ==
hsl_mports_prop_check(dev_id, entry->port.map, HSL_PP_INCL_CPU))
{
return SW_BAD_PARAM;
}
port = entry->port.map;
}
if (FAL_MAC_CPY_TO_CPU == entry->dacmd)
{
SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, COPY_TO_CPU, 1, reg[2]);
}
else if (FAL_MAC_RDT_TO_CPU == entry->dacmd)
{
SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, REDRCT_TO_CPU, 1, reg[2]);
}
else if (FAL_MAC_FRWRD != entry->dacmd)
{
return SW_NOT_SUPPORTED;
}
if (FAL_MAC_DROP == entry->sacmd)
{
SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, SA_DROP_EN, 1, reg[2]);
}
else if (FAL_MAC_FRWRD != entry->sacmd)
{
return SW_NOT_SUPPORTED;
}
if (A_TRUE == entry->leaky_en)
{
SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, LEAKY_EN, 1, reg[2]);
}
else
{
SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, LEAKY_EN, 0, reg[2]);
}
if (A_TRUE == entry->static_en)
{
SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_STATUS, 15, reg[2]);
}
else
{
SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_STATUS, 7, reg[2]);
}
if (A_TRUE == entry->mirror_en)
{
SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, MIRROR_EN, 1, reg[2]);
}
if (A_TRUE == entry->clone_en)
{
SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, CLONE_EN, 1, reg[2]);
}
if (A_TRUE == entry->cross_pt_state)
{
SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, CROSS_PT, 1, reg[2]);
}
if (A_TRUE == entry->da_pri_en)
{
hsl_dev_t *p_dev;
SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_PRI_EN, 1, reg[2]);
SW_RTN_ON_NULL(p_dev = hsl_dev_ptr_get(dev_id));
if (entry->da_queue > (p_dev->nr_queue - 1))
return SW_BAD_PARAM;
SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_PRI, entry->da_queue, reg[2]);
}
SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, DES_PORT, port, reg[2]);
shiva_fdb_fill_addr(entry->addr, ®[0], ®[1]);
return SW_OK;
}
static sw_error_t
dess_dev_init(a_uint32_t dev_id, ssdk_init_cfg *cfg)
{
a_uint32_t entry;
sw_error_t rv;
hsl_dev_t *pdev = NULL;
pdev = hsl_dev_ptr_get(dev_id);
if (pdev == NULL)
return SW_NOT_INITIALIZED;
HSL_REG_FIELD_GET(rv, dev_id, MASK_CTL, 0, DEVICE_ID,
(a_uint8_t *) (&entry), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
/*linchen: force as dess*/
#if 0
if (S17C_DEVICE_ID == entry)
{
pdev->nr_ports = 7;
pdev->nr_phy = 5;
pdev->cpu_port_nr = 0;
pdev->nr_vlans = 4096;
pdev->hw_vlan_query = A_TRUE;
pdev->nr_queue = 6;
pdev->cpu_mode = cpu_mode;
}
else
#endif
if (DESS_DEVICE_ID == entry)
{
#if 0
pdev->nr_ports = 6;
pdev->nr_phy = 5;
pdev->cpu_port_nr = 0;
pdev->nr_vlans = 4096;
pdev->hw_vlan_query = A_TRUE;
pdev->nr_queue = 6;
pdev->cpu_mode = cpu_mode;
#endif
a_uint32_t i = 0, port_nr = 0, tmp = 0;
tmp = cfg->port_cfg.lan_bmp | cfg->port_cfg.wan_bmp;
for(i = 0; i < SW_MAX_NR_PORT; i++) {
if(tmp & (1 << i)) {
port_nr++;
}
}
pdev->nr_phy = port_nr;
for(i = 0; i < SW_MAX_NR_PORT; i++) {
if(cfg->port_cfg.cpu_bmp & (1 << i)) {
port_nr++;
pdev->cpu_port_nr = i;
break;
}
}
if(i >= SW_MAX_NR_PORT)
return SW_BAD_VALUE;
pdev->nr_ports = port_nr;
pdev->nr_vlans = 4096;
pdev->hw_vlan_query = A_TRUE;
pdev->nr_queue = port_nr;
pdev->cpu_mode = cfg->cpu_mode;
pdev->wan_bmp = cfg->port_cfg.wan_bmp;
}
return SW_OK;
}
static sw_error_t
dess_portproperty_init(a_uint32_t dev_id)
{
hsl_port_prop_t p_type;
hsl_dev_t *pdev = NULL;
fal_port_t port_id;
enum ssdk_port_wrapper_cfg cfg;
a_uint32_t bitmap = 0;
a_uint32_t phy_id;
pdev = hsl_dev_ptr_get(dev_id);
if (pdev == NULL)
return SW_NOT_INITIALIZED;
cfg = dess_get_port_config();
phy_id = dess_get_port_phy_id();
if (phy_id == MALIBU_1_1_2PORT)
bitmap = dess_pbmp_2[cfg];
else {
bitmap = dess_pbmp_5[cfg];
}
/* for port property set, SSDK should not generate some limitations */
for (port_id = 0; port_id < pdev->nr_ports; port_id++)
{
hsl_port_prop_portmap_set(dev_id, port_id);
for (p_type = HSL_PP_PHY; p_type < HSL_PP_BUTT; p_type++)
{
switch (p_type)
{
case HSL_PP_PHY:
/* Only port0 without PHY device */
if (port_id != pdev->cpu_port_nr)
{
if(SW_IS_PBMP_MEMBER(bitmap, port_id))
SW_RTN_ON_ERROR(hsl_port_prop_set(dev_id, port_id, p_type));
}
break;
case HSL_PP_INCL_CPU:
/* include cpu port but exclude wan port in some cases */
/* but which port is wan port, we are no meaning */
if (port_id == pdev->cpu_port_nr)
SW_RTN_ON_ERROR(hsl_port_prop_set(dev_id, port_id, p_type));
if(SW_IS_PBMP_MEMBER(bitmap, port_id))
SW_RTN_ON_ERROR(hsl_port_prop_set(dev_id, port_id, p_type));
break;
case HSL_PP_EXCL_CPU:
/* exclude cpu port and wan port in some cases */
/* which port is wan port, we are no meaning but port0 is
always CPU port */
if (port_id != pdev->cpu_port_nr)
{
if(SW_IS_PBMP_MEMBER(bitmap, port_id))
SW_RTN_ON_ERROR(hsl_port_prop_set(dev_id, port_id, p_type));
}
break;
default:
break;
}
}
if (port_id != pdev->cpu_port_nr)
{
SW_RTN_ON_ERROR(hsl_port_prop_set_phyid
(dev_id, port_id, port_id - 1));
}
}
return SW_OK;
}
