/**
* @brief Init hsl layer.
* @details Comments:
* This operation will init hsl layer and hsl layer
* @param[in] dev_id device id
* @param[in] cfg configuration for initialization
* @return SW_OK or error code
*/
sw_error_t
garuda_init(a_uint32_t dev_id, ssdk_init_cfg *cfg)
{
a_uint8_t *p_mem;
HSL_DEV_ID_CHECK(dev_id);
p_mem = (a_uint8_t *)garuda_cfg[dev_id];
if (NULL == p_mem)
{
p_mem = aos_mem_alloc(sizeof (ssdk_init_cfg)
+ sizeof(garuda_init_spec_cfg));
garuda_cfg[dev_id] = (ssdk_init_cfg *)p_mem;
garuda_cfg[dev_id]->chip_spec_cfg = (garuda_init_spec_cfg *)
(p_mem + sizeof (ssdk_init_cfg));
}
if (NULL == p_mem)
{
return SW_OUT_OF_MEM;
}
aos_mem_copy(garuda_cfg[dev_id]->chip_spec_cfg,
cfg->chip_spec_cfg, sizeof (garuda_init_spec_cfg));
aos_mem_copy(garuda_cfg[dev_id], cfg, sizeof (ssdk_init_cfg));
garuda_cfg[dev_id]->chip_spec_cfg = (garuda_init_spec_cfg *)
(p_mem + sizeof (ssdk_init_cfg));
SW_RTN_ON_ERROR(garuda_reg_access_init(dev_id, cfg->reg_mode));
SW_RTN_ON_ERROR(garuda_dev_init(dev_id, cfg->cpu_mode));
#if !(defined(KERNEL_MODULE) && defined(USER_MODE))
{
a_uint32_t i, entry;
sw_error_t rv;
if(HSL_MDIO == cfg->reg_mode)
{
SW_RTN_ON_ERROR(garuda_bist_test(dev_id));
entry = 0x1;
HSL_REG_FIELD_SET(rv, dev_id, MASK_CTL, 0, SOFT_RST,
(a_uint8_t *) (&entry), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
i = 0x10;
do
{
HSL_REG_FIELD_GET(rv, dev_id, MASK_CTL, 0, SOFT_RST,
(a_uint8_t *) (&entry), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
aos_mdelay(10);
}
while (entry && --i);
if (0 == i)
{
return SW_INIT_ERROR;
}
}
SW_RTN_ON_ERROR(hsl_port_prop_init());
SW_RTN_ON_ERROR(hsl_port_prop_init_by_dev(dev_id));
SW_RTN_ON_ERROR(garuda_portproperty_init(dev_id, cfg->cpu_mode));
GARUDA_MIB_INIT(rv, dev_id);
GARUDA_PORT_CTRL_INIT(rv, dev_id);
GARUDA_PORTVLAN_INIT(rv, dev_id);
GARUDA_VLAN_INIT(rv, dev_id);
GARUDA_FDB_INIT(rv, dev_id);
GARUDA_QOS_INIT(rv, dev_id);
GARUDA_STP_INIT(rv, dev_id);
GARUDA_MIRR_INIT(rv, dev_id);
GARUDA_RATE_INIT(rv, dev_id);
GARUDA_MISC_INIT(rv, dev_id);
GARUDA_LEAKY_INIT(rv, dev_id);
GARUDA_IGMP_INIT(rv, dev_id);
GARUDA_ACL_INIT(rv, dev_id);
GARUDA_LED_INIT(rv, dev_id);
{
hsl_api_t *p_api;
SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
p_api->dev_reset = garuda_reset;
p_api->dev_clean = garuda_cleanup;
}
if(cfg->reg_mode == HSL_MDIO)
{
SW_RTN_ON_ERROR(garuda_hw_init(dev_id, cfg));
}
}
#endif
return SW_OK;
}
/**
* @brief Init hsl layer.
* @details Comments:
* This operation will init hsl layer and hsl layer
* @param[in] dev_id device id
* @param[in] cfg configuration for initialization
* @return SW_OK or error code
*/
sw_error_t
isis_init(a_uint32_t dev_id, ssdk_init_cfg *cfg)
{
HSL_DEV_ID_CHECK(dev_id);
if (NULL == isis_cfg[dev_id])
{
isis_cfg[dev_id] = aos_mem_alloc(sizeof (ssdk_init_cfg));
}
if (NULL == isis_cfg[dev_id])
{
return SW_OUT_OF_MEM;
}
aos_mem_copy(isis_cfg[dev_id], cfg, sizeof (ssdk_init_cfg));
SW_RTN_ON_ERROR(isis_reg_access_init(dev_id, cfg->reg_mode));
SW_RTN_ON_ERROR(isis_dev_init(dev_id, cfg->cpu_mode));
#if !(defined(KERNEL_MODULE) && defined(USER_MODE))
{
sw_error_t rv;
SW_RTN_ON_ERROR(hsl_port_prop_init());
SW_RTN_ON_ERROR(hsl_port_prop_init_by_dev(dev_id));
SW_RTN_ON_ERROR(isis_portproperty_init(dev_id, cfg->cpu_mode));
ISIS_MIB_INIT(rv, dev_id);
ISIS_PORT_CTRL_INIT(rv, dev_id);
ISIS_PORTVLAN_INIT(rv, dev_id);
ISIS_VLAN_INIT(rv, dev_id);
ISIS_FDB_INIT(rv, dev_id);
ISIS_QOS_INIT(rv, dev_id);
ISIS_STP_INIT(rv, dev_id);
ISIS_MIRR_INIT(rv, dev_id);
ISIS_RATE_INIT(rv, dev_id);
ISIS_MISC_INIT(rv, dev_id);
ISIS_LEAKY_INIT(rv, dev_id);
ISIS_IGMP_INIT(rv, dev_id);
ISIS_ACL_INIT(rv, dev_id);
ISIS_LED_INIT(rv, dev_id);
ISIS_COSMAP_INIT(rv, dev_id);
ISIS_IP_INIT(rv, dev_id);
ISIS_NAT_INIT(rv, dev_id);
ISIS_TRUNK_INIT(rv, dev_id);
ISIS_SEC_INIT(rv, dev_id);
ISIS_INTERFACE_CTRL_INIT(rv, dev_id);
{
hsl_api_t *p_api;
SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
p_api->dev_reset = isis_reset;
p_api->dev_clean = isis_cleanup;
}
SW_RTN_ON_ERROR(isis_hw_init(dev_id, cfg));
#if defined(IN_NAT_HELPER)
ISIS_NAT_HELPER_INIT(rv, dev_id);
#endif
}
#endif
return SW_OK;
}
/**
* @brief Init hsl layer.
* @details Comments:
* This operation will init hsl layer and hsl layer
* @param[in] dev_id device id
* @param[in] cfg configuration for initialization
* @return SW_OK or error code
*/
sw_error_t
horus_init(a_uint32_t dev_id, ssdk_init_cfg *cfg)
{
HSL_DEV_ID_CHECK(dev_id);
if (NULL == horus_cfg[dev_id])
{
horus_cfg[dev_id] = aos_mem_alloc(sizeof (ssdk_init_cfg));
}
if (NULL == horus_cfg[dev_id])
{
return SW_OUT_OF_MEM;
}
aos_mem_copy(horus_cfg[dev_id], cfg, sizeof (ssdk_init_cfg));
SW_RTN_ON_ERROR(horus_reg_access_init(dev_id, cfg->reg_mode));
SW_RTN_ON_ERROR(horus_dev_init(dev_id, cfg->cpu_mode));
#if !(defined(KERNEL_MODULE) && defined(USER_MODE))
{
a_uint32_t i, entry;
sw_error_t rv;
SW_RTN_ON_ERROR(horus_bist_test(dev_id));
entry = 0x1;
HSL_REG_FIELD_SET(rv, dev_id, MASK_CTL, 0, SOFT_RST,
(a_uint8_t *) (&entry), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
i = 0x10;
do
{
HSL_REG_FIELD_GET(rv, dev_id, MASK_CTL, 0, SOFT_RST,
(a_uint8_t *) (&entry), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
aos_mdelay(10);
}
while (entry && --i);
if (0 == i)
{
return SW_INIT_ERROR;
}
SW_RTN_ON_ERROR(hsl_port_prop_init());
SW_RTN_ON_ERROR(hsl_port_prop_init_by_dev(dev_id));
SW_RTN_ON_ERROR(horus_portproperty_init(dev_id, cfg->cpu_mode));
HORUS_MIB_INIT(rv, dev_id);
HORUS_PORT_CTRL_INIT(rv, dev_id);
HORUS_PORTVLAN_INIT(rv, dev_id);
HORUS_VLAN_INIT(rv, dev_id);
HORUS_FDB_INIT(rv, dev_id);
HORUS_QOS_INIT(rv, dev_id);
HORUS_STP_INIT(rv, dev_id);
HORUS_MIRR_INIT(rv, dev_id);
HORUS_RATE_INIT(rv, dev_id);
HORUS_MISC_INIT(rv, dev_id);
HORUS_LEAKY_INIT(rv, dev_id);
HORUS_IGMP_INIT(rv, dev_id);
HORUS_LED_INIT(rv, dev_id);
{
hsl_api_t *p_api;
SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
p_api->dev_reset = horus_reset;
p_api->dev_clean = horus_cleanup;
}
SW_RTN_ON_ERROR(horus_hw_init(dev_id, cfg));
}
#endif
return SW_OK;
}
