int arch_cpu_init_dm(void) { hw_data_init(); #ifndef CONFIG_SKIP_LOWLEVEL_INIT early_system_init(); #endif return 0; }
void board_init_f(ulong dummy) { hw_data_init(); early_system_init(); board_early_init_f(); sdram_init(); /* dram_init must store complete ramsize in gd->ram_size */ gd->ram_size = get_ram_size( (void *)CONFIG_SYS_SDRAM_BASE, CONFIG_MAX_RAM_BANK_SIZE); }
int board_init(void) { struct l3f_cfg_bwlimiter *bwlimiter = (struct l3f_cfg_bwlimiter *)L3F_CFG_BWLIMITER; u32 mreqprio_0, mreqprio_1, modena_init0_bw_fractional, modena_init0_bw_integer, modena_init0_watermark_0; gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; gpmc_init(); /* * Call this to initialize *ctrl again */ hw_data_init(); /* Clear all important bits for DSS errata that may need to be tweaked*/ mreqprio_0 = readl(&cdev->mreqprio_0) & MREQPRIO_0_SAB_INIT1_MASK & MREQPRIO_0_SAB_INIT0_MASK; mreqprio_1 = readl(&cdev->mreqprio_1) & MREQPRIO_1_DSS_MASK; modena_init0_bw_fractional = readl(&bwlimiter->modena_init0_bw_fractional) & BW_LIMITER_BW_FRAC_MASK; modena_init0_bw_integer = readl(&bwlimiter->modena_init0_bw_integer) & BW_LIMITER_BW_INT_MASK; modena_init0_watermark_0 = readl(&bwlimiter->modena_init0_watermark_0) & BW_LIMITER_BW_WATERMARK_MASK; /* Setting MReq Priority of the DSS*/ mreqprio_0 |= 0x77; /* * Set L3 Fast Configuration Register * Limiting bandwith for ARM core to 700 MBPS */ modena_init0_bw_fractional |= 0x10; modena_init0_bw_integer |= 0x3; writel(mreqprio_0, &cdev->mreqprio_0); writel(mreqprio_1, &cdev->mreqprio_1); writel(modena_init0_bw_fractional, &bwlimiter->modena_init0_bw_fractional); writel(modena_init0_bw_integer, &bwlimiter->modena_init0_bw_integer); writel(modena_init0_watermark_0, &bwlimiter->modena_init0_watermark_0); return 0; }