int hw_reset(void)
{
TRY(hw_mem_reset());
TRY(hw_flash_reset());
TRY(hw_io_reset());
TRY(hw_hwp_reset());
TRY(hw_kbd_reset());
TRY(hw_dbus_reset());
TRY(hw_m68k_reset());
return 0;
}
void io_put_byte(uint32_t addr, uint8_t arg)
{
addr &= 31; //tihw.io_size-1;
switch(addr)
{
case 0x00: // rw <76...2..>
// %5: bit 0 of contrast (TI92)
if(tihw.calc_type == TI92)
bit_chg(tihw.contrast,0,bit_get(arg,5));
break;
case 0x01: // rw <.....2.0>
// %0 clr: interleave RAM (allows use of 256K of RAM)
if(tihw.hw_type == 1)
tihw.ram_size = bit_tst(arg, 0) ? 128*KB : 256*KB;
// %2 set: protected memory violation triggered when memory below [$000120] is written
break;
case 0x02: // ??
break;
case 0x03: // -w <.654.210>
// Bus waitstates
break;
case 0x04:
break;
case 0x05: // -w <...43210>
// turn off OSC1 (CPU), wake on int level 6 (ON key) and int level [5..1]
m68k_setstopped(1);
break;
case 0x06:
case 0x07:
case 0x08:
case 0x09:
case 0x0a:
case 0x0b:
break;
case 0x0c: // rw <765.3210>
// %[3:0]: Trigger interrupt level 4 on error, activity, tx empty, rx full
// see hardware.c
// %6: link disable (usually reset link port or direct access to wires)
if(bit_get(arg, 6))
hw_dbus_reset();
break;
case 0x0d: // r- <76543210>
break;
case 0x0e: // rw <....3210>
// set red/white wires (if direct access)
if(io_bit_tst(0x0c,6))
{
lc.set_red_wire(!bit_get(arg,0));
lc.set_white_wire(!bit_get(arg,1));
}
break;
case 0x0f: // rw <76543210>
// write a byte to the transmit buffer (1 byte buffer)
io_bit_clr(0x0d, 0); // STX=0 (tx reg is full)
hw_dbus_putbyte(arg);
break;
case 0x10: // -w <76543210> (hw1)
// address of LCD memory divided by 8 (msb)
if(tihw.hw_type == HW1)
tihw.lcd_adr = ((arg << 8) | tihw.io[0x11]) << 3;
break;
case 0x11: // -w <76543210> (hw1)
// address of LCD memory divided by 8 (lsb)
if(tihw.hw_type == HW1)
tihw.lcd_adr = ((tihw.io[0x10] << 8) | arg) << 3;
break;
case 0x12: // -w <76543210>
// LCD logical width = (64-n)*2 bytes = (64-n)*16 pixels <=> n = 64-w/16
tihw.log_w = (64 - arg) * 16;
break;
case 0x13: // -w <..543210>
// LCD logical height = (256-n) <=> n = 256-h
tihw.log_h = 0x100 - arg;
break;
case 0x14:
break;
case 0x15: // rw <7.6543210>
// %7 set: Master disable timer interrupts (level 1, 3 and 5)
// see hardware.c
// %[5-4]: Increment rate of $600017 (prescaler)
set_prescaler((arg >> 4) & 3);
// %3 set: Enable incrementing of $600017
// see hardware.c
// %2 set: Trigger interrupt level 3 at OSC2/2^19 (~1 Hz on HW2)
// see hardware.c
// %1 set: OSC2 (and OSC3?) enable (bit clear means oscillator stopped!)
// see hardware.c
// %0 set: LCD controller DMA enable else LCD blank ("white")
// could be implemented but redundant with tihw.on_off
break;
case 0x16:
break;
case 0x17: // rw <76543210>
// programmable rate generator
break;
case 0x18: // rw <......10>
// keyboard row mask (see keyboard.c)
break;
case 0x19: // rw <76543210>
// keyboard row mask (see keyboard.c)
break;
case 0x1a: // r- <......10>
// ON key status (see keyboard.c)
// Write any value to $60001A to acknowledge this interrupt (AutoInt6)
break;
case 0x1b: // r- <76543210>
// keyboard column status (see keyboard.c)
// Write any value to $60001B to acknowledge this interrupt (AutoInt2)
break;
case 0x1c: // -w <..5432..>
// %[5-2] set: LCD RS (row sync) frequency, OSC2/((16-n)*8)
// %1111 turns off the RS completely (used when LCD is off)
tihw.on_off = ((arg & 0x3c) == 0x3c) ? 0 : 1;
break;
case 0x1d: // -w <7..43210>
// %[3-0]: contrast
if(tihw.calc_type == TI92)
{
// %[3-0]: bits <4321.> of contrast
static int avg = 0;
avg = (avg + arg)/2; // filter value
tihw.contrast = (tihw.contrast & 1) | ((avg & 15) << 1);
}
else
{
// %[4/3-0]: LCD contrast bits 4/3-0 (bit 4/3 is msb on HW2/HW1)
tihw.contrast = arg & (io2_bit_tst(0x1f,0) ? 0x1f : 0x0f);
if(tihw.calc_type == TI89 || tihw.calc_type == TI89t)
{
if(tihw.hw_type == HW1)
tihw.contrast = 31 - 2*tihw.contrast;
else
tihw.contrast = 31 - tihw.contrast;
}
}
break;
case 0x1e:
break;
case 0x1f:
break;
}
tihw.io[addr] = arg;
}
