static int
memmmap(struct dev_mmap_args *ap)
{
cdev_t dev = ap->a_head.a_dev;
switch (minor(dev)) {
case 0:
/*
* minor device 0 is physical memory
*/
#if defined(__i386__)
ap->a_result = i386_btop(ap->a_offset);
#elif defined(__x86_64__)
ap->a_result = x86_64_btop(ap->a_offset);
#endif
return 0;
case 1:
/*
* minor device 1 is kernel memory
*/
#if defined(__i386__)
ap->a_result = i386_btop(vtophys(ap->a_offset));
#elif defined(__x86_64__)
ap->a_result = x86_64_btop(vtophys(ap->a_offset));
#endif
return 0;
default:
return EINVAL;
}
}
static int
xrpu_mmap(dev_t dev, vm_offset_t offset, int nprot)
{
struct softc *sc = dev->si_drv1;
if (offset >= 0x1000000)
return (-1);
return (i386_btop(sc->physbase + offset));
}
void
lapic_init(void)
{
int result;
vm_map_entry_t entry;
uint32_t lo;
uint32_t hi;
boolean_t is_boot_processor;
boolean_t is_lapic_enabled;
vm_offset_t lapic_base;
/* Examine the local APIC state */
rdmsr(MSR_IA32_APIC_BASE, lo, hi);
is_boot_processor = (lo & MSR_IA32_APIC_BASE_BSP) != 0;
is_lapic_enabled = (lo & MSR_IA32_APIC_BASE_ENABLE) != 0;
lapic_base = (lo & MSR_IA32_APIC_BASE_BASE);
kprintf("MSR_IA32_APIC_BASE %p %s %s\n", (void *) lapic_base,
is_lapic_enabled ? "enabled" : "disabled",
is_boot_processor ? "BSP" : "AP");
if (!is_boot_processor || !is_lapic_enabled)
panic("Unexpected local APIC state\n");
/* Establish a map to the local apic */
lapic_start = (vm_offset_t)vm_map_min(kernel_map);
result = vm_map_find_space(kernel_map,
(vm_map_address_t *) &lapic_start,
round_page(LAPIC_SIZE), 0,
VM_MAKE_TAG(VM_MEMORY_IOKIT), &entry);
if (result != KERN_SUCCESS) {
panic("smp_init: vm_map_find_entry FAILED (err=%d)", result);
}
vm_map_unlock(kernel_map);
/* Map in the local APIC non-cacheable, as recommended by Intel
* in section 8.4.1 of the "System Programming Guide".
*/
pmap_enter(pmap_kernel(),
lapic_start,
(ppnum_t) i386_btop(lapic_base),
VM_PROT_READ|VM_PROT_WRITE,
VM_WIMG_IO,
TRUE);
lapic_id = (unsigned long)(lapic_start + LAPIC_ID);
if ((LAPIC_READ(VERSION)&LAPIC_VERSION_MASK) < 0x14) {
panic("Local APIC version 0x%x, 0x14 or more expected\n",
(LAPIC_READ(VERSION)&LAPIC_VERSION_MASK));
}
/* Set up the lapic_id <-> cpu_number map and add this boot processor */
lapic_cpu_map_init();
lapic_cpu_map((LAPIC_READ(ID)>>LAPIC_ID_SHIFT)&LAPIC_ID_MASK, 0);
kprintf("Boot cpu local APIC id 0x%x\n", cpu_to_lapic[0]);
}
/*
* Write bytes to kernel address space for debugger.
*/
void
db_write_bytes(vaddr_t addr, size_t size, char *data)
{
char *dst;
pt_entry_t *ptep0 = 0;
pt_entry_t oldmap0 = { 0 };
vaddr_t addr1;
pt_entry_t *ptep1 = 0;
pt_entry_t oldmap1 = { 0 };
extern char etext;
if (addr >= VM_MIN_KERNEL_ADDRESS &&
addr < (vaddr_t)&etext) {
ptep0 = PTE_BASE + i386_btop(addr);
oldmap0 = *ptep0;
*(int *)ptep0 |= /* INTEL_PTE_WRITE */ PG_RW;
addr1 = i386_trunc_page(addr + size - 1);
if (i386_trunc_page(addr) != addr1) {
/* data crosses a page boundary */
ptep1 = PTE_BASE + i386_btop(addr1);
oldmap1 = *ptep1;
*(int *)ptep1 |= /* INTEL_PTE_WRITE */ PG_RW;
}
tlbflush();
}
dst = (char *)addr;
while (size-- > 0)
*dst++ = *data++;
if (ptep0) {
*ptep0 = oldmap0;
if (ptep1)
*ptep1 = oldmap1;
tlbflush();
}
}
int
spigot_mmap(dev_t dev, int offset, int nprot)
{
struct spigot_softc *ss = (struct spigot_softc *)&spigot_softc[0];
if(offset != 0) {
printf("spigot mmap failed, offset = 0x%x != 0x0\n", offset);
return -1;
}
if(nprot & PROT_EXEC)
return -1;
return i386_btop(ss->maddr);
}
static void
legacy_init(void)
{
int result;
vm_map_entry_t entry;
vm_map_offset_t lapic_vbase64;
/* Establish a map to the local apic */
lapic_vbase64 = (vm_offset_t)vm_map_min(kernel_map);
result = vm_map_find_space(kernel_map,
&lapic_vbase64,
round_page(LAPIC_SIZE), 0,
VM_MAKE_TAG(VM_MEMORY_IOKIT), &entry);
/* Convert 64-bit vm_map_offset_t to "pointer sized" vm_offset_t
*/
lapic_vbase = (vm_offset_t) lapic_vbase64;
if (result != KERN_SUCCESS) {
panic("legacy_init: vm_map_find_entry FAILED (err=%d)", result);
}
vm_map_unlock(kernel_map);
/*
* Map in the local APIC non-cacheable, as recommended by Intel
* in section 8.4.1 of the "System Programming Guide".
* In fact, this is redundant because EFI will have assigned an
* MTRR physical range containing the local APIC's MMIO space as
* UC and this will override the default PAT setting.
*/
pmap_enter(pmap_kernel(),
lapic_vbase,
(ppnum_t) i386_btop(lapic_pbase),
VM_PROT_READ|VM_PROT_WRITE,
VM_PROT_NONE,
VM_WIMG_IO,
TRUE);
}
