Exemplo n.º 1
0
static uint32_t sh7750_mem_readw(void *opaque, target_phys_addr_t addr)
{
    SH7750State *s = opaque;

    switch (addr) {
    case SH7750_BCR2_A7:
	return s->bcr2;
    case SH7750_BCR3_A7:
	if(!has_bcr3_and_bcr4(s))
	    error_access("word read", addr);
	return s->bcr3;
    case SH7750_FRQCR_A7:
	return 0;
    case SH7750_PCR_A7:
	return s->pcr;
    case SH7750_RFCR_A7:
	fprintf(stderr,
		"Read access to refresh count register, incrementing\n");
	return s->rfcr++;
    case SH7750_PDTRA_A7:
	return porta_lines(s);
    case SH7750_PDTRB_A7:
	return portb_lines(s);
    case SH7750_RTCOR_A7:
    case SH7750_RTCNT_A7:
    case SH7750_RTCSR_A7:
	ignore_access("word read", addr);
	return 0;
    default:
	error_access("word read", addr);
        abort();
    }
}
Exemplo n.º 2
0
static void sh7750_mem_writeb(void *opaque, target_phys_addr_t addr,
			      uint32_t mem_value)
{

    if (is_in_sdrmx(addr, 2) || is_in_sdrmx(addr, 3)) {
	ignore_access("byte write", addr);
	return;
    }

    error_access("byte write", addr);
    abort();
}
Exemplo n.º 3
0
static void sh7750_mem_writew(void *opaque, target_phys_addr_t addr,
			      uint32_t mem_value)
{
    SH7750State *s = opaque;
    uint16_t temp;

    switch (addr) {
	/* SDRAM controller */
    case SH7750_BCR2_A7:
        s->bcr2 = mem_value;
        return;
    case SH7750_BCR3_A7:
	if(!has_bcr3_and_bcr4(s))
	    error_access("word write", addr);
	s->bcr3 = mem_value;
	return;
    case SH7750_PCR_A7:
	s->pcr = mem_value;
	return;
    case SH7750_RTCNT_A7:
    case SH7750_RTCOR_A7:
    case SH7750_RTCSR_A7:
	ignore_access("word write", addr);
	return;
	/* IO ports */
    case SH7750_PDTRA_A7:
	temp = porta_lines(s);
	s->pdtra = mem_value;
	porta_changed(s, temp);
	return;
    case SH7750_PDTRB_A7:
	temp = portb_lines(s);
	s->pdtrb = mem_value;
	portb_changed(s, temp);
	return;
    case SH7750_RFCR_A7:
	fprintf(stderr, "Write access to refresh count register\n");
	s->rfcr = mem_value;
	return;
    case SH7750_GPIOIC_A7:
	s->gpioic = mem_value;
	if (mem_value != 0) {
	    fprintf(stderr, "I/O interrupts not implemented\n");
            abort();
	}
	return;
    default:
	error_access("word write", addr);
        abort();
    }
}
Exemplo n.º 4
0
static void sh7750_mem_writeb(void *opaque, target_phys_addr_t addr,
			      uint32_t mem_value)
{
    switch (addr) {
	/* PRECHARGE ? XXXXX */
    case SH7750_PRECHARGE0_A7:
    case SH7750_PRECHARGE1_A7:
	ignore_access("byte write", addr);
	return;
    default:
	error_access("byte write", addr);
	assert(0);
    }
}
Exemplo n.º 5
0
Arquivo: sh7750.c Projeto: 8tab/qemu
static uint32_t sh7750_mem_readl(void *opaque, hwaddr addr)
{
    SH7750State *s = opaque;
    SuperHCPUClass *scc;

    switch (addr) {
    case SH7750_BCR1_A7:
	return s->bcr1;
    case SH7750_BCR4_A7:
	if(!has_bcr3_and_bcr4(s))
	    error_access("long read", addr);
	return s->bcr4;
    case SH7750_WCR1_A7:
    case SH7750_WCR2_A7:
    case SH7750_WCR3_A7:
    case SH7750_MCR_A7:
        ignore_access("long read", addr);
        return 0;
    case SH7750_MMUCR_A7:
        return s->cpu->env.mmucr;
    case SH7750_PTEH_A7:
        return s->cpu->env.pteh;
    case SH7750_PTEL_A7:
        return s->cpu->env.ptel;
    case SH7750_TTB_A7:
        return s->cpu->env.ttb;
    case SH7750_TEA_A7:
        return s->cpu->env.tea;
    case SH7750_TRA_A7:
        return s->cpu->env.tra;
    case SH7750_EXPEVT_A7:
        return s->cpu->env.expevt;
    case SH7750_INTEVT_A7:
        return s->cpu->env.intevt;
    case SH7750_CCR_A7:
	return s->ccr;
    case 0x1f000030:		/* Processor version */
        scc = SUPERH_CPU_GET_CLASS(s->cpu);
        return scc->pvr;
    case 0x1f000040:		/* Cache version */
        scc = SUPERH_CPU_GET_CLASS(s->cpu);
        return scc->cvr;
    case 0x1f000044:		/* Processor revision */
        scc = SUPERH_CPU_GET_CLASS(s->cpu);
        return scc->prr;
    default:
	error_access("long read", addr);
        abort();
    }
}
Exemplo n.º 6
0
static uint32_t sh7750_mem_readl(void *opaque, target_phys_addr_t addr)
{
    SH7750State *s = opaque;

    switch (addr) {
    case SH7750_BCR1_A7:
	return s->bcr1;
    case SH7750_BCR4_A7:
	if(!has_bcr3_and_bcr4(s))
	    error_access("long read", addr);
	return s->bcr4;
    case SH7750_WCR1_A7:
    case SH7750_WCR2_A7:
    case SH7750_WCR3_A7:
    case SH7750_MCR_A7:
        ignore_access("long read", addr);
        return 0;
    case SH7750_MMUCR_A7:
	return s->cpu->mmucr;
    case SH7750_PTEH_A7:
	return s->cpu->pteh;
    case SH7750_PTEL_A7:
	return s->cpu->ptel;
    case SH7750_TTB_A7:
	return s->cpu->ttb;
    case SH7750_TEA_A7:
	return s->cpu->tea;
    case SH7750_TRA_A7:
	return s->cpu->tra;
    case SH7750_EXPEVT_A7:
	return s->cpu->expevt;
    case SH7750_INTEVT_A7:
	return s->cpu->intevt;
    case SH7750_CCR_A7:
	return s->ccr;
    case 0x1f000030:		/* Processor version */
	return s->cpu->pvr;
    case 0x1f000040:		/* Cache version */
	return s->cpu->cvr;
    case 0x1f000044:		/* Processor revision */
	return s->cpu->prr;
    default:
	error_access("long read", addr);
        abort();
    }
}
Exemplo n.º 7
0
static void sh7750_mem_writel(void *opaque, target_phys_addr_t addr,
			      uint32_t mem_value)
{
    SH7750State *s = opaque;
    uint16_t temp;

    switch (addr) {
	/* SDRAM controller */
    case SH7750_BCR1_A7:
        s->bcr1 = mem_value;
        return;
    case SH7750_BCR4_A7:
	if(!has_bcr3_and_bcr4(s))
	    error_access("long write", addr);
	s->bcr4 = mem_value;
	return;
    case SH7750_WCR1_A7:
    case SH7750_WCR2_A7:
    case SH7750_WCR3_A7:
    case SH7750_MCR_A7:
	ignore_access("long write", addr);
	return;
	/* IO ports */
    case SH7750_PCTRA_A7:
	temp = porta_lines(s);
	s->pctra = mem_value;
	s->portdira = portdir(mem_value);
	s->portpullupa = portpullup(mem_value);
	porta_changed(s, temp);
	return;
    case SH7750_PCTRB_A7:
	temp = portb_lines(s);
	s->pctrb = mem_value;
	s->portdirb = portdir(mem_value);
	s->portpullupb = portpullup(mem_value);
	portb_changed(s, temp);
	return;
    case SH7750_MMUCR_A7:
        if (mem_value & MMUCR_TI) {
            cpu_sh4_invalidate_tlb(s->cpu);
        }
        s->cpu->mmucr = mem_value & ~MMUCR_TI;
        return;
    case SH7750_PTEH_A7:
        /* If asid changes, clear all registered tlb entries. */
	if ((s->cpu->pteh & 0xff) != (mem_value & 0xff))
	    tlb_flush(s->cpu, 1);
	s->cpu->pteh = mem_value;
	return;
    case SH7750_PTEL_A7:
	s->cpu->ptel = mem_value;
	return;
    case SH7750_PTEA_A7:
	s->cpu->ptea = mem_value & 0x0000000f;
	return;
    case SH7750_TTB_A7:
	s->cpu->ttb = mem_value;
	return;
    case SH7750_TEA_A7:
	s->cpu->tea = mem_value;
	return;
    case SH7750_TRA_A7:
	s->cpu->tra = mem_value & 0x000007ff;
	return;
    case SH7750_EXPEVT_A7:
	s->cpu->expevt = mem_value & 0x000007ff;
	return;
    case SH7750_INTEVT_A7:
	s->cpu->intevt = mem_value & 0x000007ff;
	return;
    case SH7750_CCR_A7:
	s->ccr = mem_value;
	return;
    default:
	error_access("long write", addr);
        abort();
    }
}