static u8
init_ram_restrict_strap(struct nvbios_init *init)
{
/* This appears to be the behaviour of the VBIOS parser, and *is*
* important to cache the NV_PEXTDEV_BOOT0 on later chipsets to
* avoid f*****g up the memory controller (somehow) by reading it
* on every INIT_RAM_RESTRICT_ZM_GROUP opcode.
*
* Preserving the non-caching behaviour on earlier chipsets just
* in case *not* re-reading the strap causes similar breakage.
*/
if (!init->ramcfg || init->bios->version.major < 0x70)
init->ramcfg = init_rd32(init, 0x101000);
return (init->ramcfg & 0x00000003c) >> 2;
}
static bool
init_condition_met(struct nvbios_init *init, u8 cond)
{
struct nouveau_bios *bios = init->bios;
u16 table = init_condition_table(init);
if (table) {
u32 reg = nv_ro32(bios, table + (cond * 12) + 0);
u32 msk = nv_ro32(bios, table + (cond * 12) + 4);
u32 val = nv_ro32(bios, table + (cond * 12) + 8);
trace("\t[0x%02x] (R[0x%06x] & 0x%08x) == 0x%08x\n",
cond, reg, msk, val);
return (init_rd32(init, reg) & msk) == val;
}
return false;
}
struct bit_entry bit_M;
if (!bit_entry(bios, 'M', &bit_M)) {
if (bit_M.version == 1 && bit_M.length >= 5)
return nv_ro08(bios, bit_M.offset + 2);
if (bit_M.version == 2 && bit_M.length >= 3)
return nv_ro08(bios, bit_M.offset + 0);
}
return 0x00;
}
static u8
init_ram_restrict(struct nvbios_init *init)
{
u32 strap = (init_rd32(init, 0x101000) & 0x0000003c) >> 2;
u16 table = init_ram_restrict_table(init);
if (table)
return nv_ro08(init->bios, table + strap);
return 0x00;
}
static u8
init_xlat_(struct nvbios_init *init, u8 index, u8 offset)
{
struct nouveau_bios *bios = init->bios;
u16 table = init_xlat_table(init);
if (table) {
u16 data = nv_ro16(bios, table + (index * 2));
if (data)
return nv_ro08(bios, data + offset);
