static irqreturn_t skfp_interrupt(int irq, void *dev_id)
{
struct net_device *dev = dev_id;
struct s_smc *smc;
skfddi_priv *bp;
smc = netdev_priv(dev);
bp = &smc->os;
if (inpd(ADDR(B0_IMSK)) == 0) {
return IRQ_NONE;
}
if ((inpd(ISR_A) & smc->hw.is_imask) == 0) {
return IRQ_NONE;
}
CLI_FBI();
spin_lock(&bp->DriverLock);
fddi_isr(smc);
if (smc->os.ResetRequested) {
ResetAdapter(smc);
smc->os.ResetRequested = FALSE;
}
spin_unlock(&bp->DriverLock);
STI_FBI();
return IRQ_HANDLED;
}
int try_pci_type1() {
int ret = 0;
uint32_t tmp = inpd(0xCF8);
outpd(0xCF8,0x80000000);
if (inpd(0xCF8) == 0x80000000 && inpd(0xCFC) != 0xFFFFFFFFUL) ret=1; /* might be type 2 reflecting written data */
outpd(0xCF8,tmp);
return ret;
}
static void speedo_resume(struct dev *dev) {
struct nic *sp = (struct nic *) dev->privdata;
long ioaddr = sp->iobase;
outpw(ioaddr + SCBCmd, SCBMaskAll);
// Start with a Tx threshold of 256 (0x..20.... 8 byte units)
sp->tx_threshold = 0x01208000;
// Set the segment registers to '0'
wait_for_cmd_done(ioaddr + SCBCmd);
if (inp(ioaddr + SCBCmd)) {
outpd(ioaddr + SCBPort, PortPartialReset);
udelay(10);
}
outpd(ioaddr + SCBPointer, 0);
inpd(ioaddr + SCBPointer); // Flush to PCI
udelay(10); // Bogus, but it avoids the bug
// Note: these next two operations can take a while
do_slow_command(dev, RxAddrLoad);
do_slow_command(dev, CUCmdBase);
// Load the statistics block and rx ring addresses
outpd(ioaddr + SCBPointer, virt2phys(&sp->lstats));
inpd(ioaddr + SCBPointer); // Flush to PCI
outp(ioaddr + SCBCmd, CUStatsAddr);
sp->lstats.done_marker = 0;
wait_for_cmd_done(ioaddr + SCBCmd);
outpd(ioaddr + SCBPointer, virt2phys(sp->rx_ringp[sp->cur_rx % RX_RING_SIZE]));
inpd(ioaddr + SCBPointer); // Flush to PCI
// Note: RxStart should complete instantly.
do_slow_command(dev, RxStart);
do_slow_command(dev, CUDumpStats);
// Fill the first command with our physical address
{
int entry = sp->cur_tx++ % TX_RING_SIZE;
struct descriptor *cur_cmd = (struct descriptor *) &sp->tx_ring[entry];
// Avoid a bug(?!) here by marking the command already completed
cur_cmd->cmd_status = (CmdSuspend | CmdIASetup) | 0xa000;
cur_cmd->link = virt2phys(&sp->tx_ring[sp->cur_tx % TX_RING_SIZE]);
memcpy(cur_cmd->params, sp->hwaddr.addr, 6);
if (sp->last_cmd) clear_suspend(sp->last_cmd);
sp->last_cmd = cur_cmd;
}
// Start the chip's Tx process and unmask interrupts
outpd(ioaddr + SCBPointer, virt2phys(&sp->tx_ring[sp->dirty_tx % TX_RING_SIZE]));
outpw(ioaddr + SCBCmd, CUStart);
}
static U32 ReadPCI( U32 uAddress )
{
#ifdef _MSC_VER
#if (_MSC_VER <= 800)
// MS 16-bit compiler (i.e. 1.52c)
out32( PCI_INDEX_REG, uAddress );
return( in32( PCI_DATA_REG ) );
#else
// ME 32-bit compiler (i.e. MSVC 6.0+)
_outpd( PCI_INDEX_REG, uAddress );
return( _inpd( PCI_DATA_REG ) );
#endif
#else
// Open Watcom 32-bit compiler
outpd( PCI_INDEX_REG, uAddress );
return( inpd( PCI_DATA_REG ) );
#endif
}
int read_vtx86_gpio_pin_config(void) {
unsigned int i;
uint32_t tmp;
if (!(vtx86_86duino_flags & VTX86_86DUINO_FLAG_DETECTED))
return 0;
vtx86_gpio_port_cfg.gpio_dec_enable = inpd(vtx86_cfg.gpio_portconfig_base_io + 0x00);
for (i=0;i < 10;i++) {
tmp = inpd(vtx86_cfg.gpio_portconfig_base_io + 0x04 + (i * 4u));
vtx86_gpio_port_cfg.gpio_pingroup[i].data_io = (uint16_t)(tmp & 0xFFFFul);
vtx86_gpio_port_cfg.gpio_pingroup[i].dir_io = (uint16_t)(tmp >> 16ul);
}
return 1;
}
static struct stats_nic *rtl8139_get_stats(struct dev *dev) {
struct nic *tp = (struct nic *) dev->privdata;
long ioaddr = tp->iobase;
tp->stats.rx_missed_errors += inpd(ioaddr + RxMissed);
outpd(ioaddr + RxMissed, 0);
return &tp->stats;
}
uint32_t PCI_Device::read_dword(uint16_t pci_addr, uint8_t reg){
PCI::msg req;
req.data=0x80000000;
req.addr=pci_addr;
req.reg=reg;
outpd(PCI::CONFIG_ADDR,(uint32_t)0x80000000 | req.data );
return inpd(PCI::CONFIG_DATA);
};
uint32_t pci_read_cfg_TYPE1(uint8_t bus,uint8_t card,uint8_t func,uint8_t reg,uint8_t size) {
pci_type1_select(bus,card,func,reg);
switch (size) {
case 2: return inpd(0xCFC);
case 1: return inpw(0xCFC+(reg&3));
case 0: return inp(0xCFC+(reg&3));
}
return ~0UL;
}
uint32_t PCI_Device::read_dword(const uint16_t pci_addr, const uint8_t reg) noexcept {
PCI::msg req;
req.data = 0x80000000;
req.addr = pci_addr;
req.reg = reg;
outpd(PCI::CONFIG_ADDR, 0x80000000 | req.data);
return inpd(PCI::CONFIG_DATA);
}
static void rtl_error(struct dev *dev, int status, int link_changed) {
struct nic *tp = (struct nic *) dev->privdata;
long ioaddr = tp->iobase;
kprintf("%s: Abnormal interrupt, status %8.8x\n", dev->name, status);
// Update the error count
tp->stats.rx_missed_errors += inpd(ioaddr + RxMissed);
outpd(ioaddr + RxMissed, 0);
if (status & RxUnderrun) {
// This might actually be a link change event
if ((tp->flags & HAS_LNK_CHNG) && link_changed) {
// Really link-change on new chips
int lpar = inpw(ioaddr + NWayLPAR);
int duplex = (lpar & 0x0100) || (lpar & 0x01C0) == 0x0040 || tp->duplex_lock;
// Do not use MII_BMSR as that clears sticky bit
//if (inpw(ioaddr + GPPinData) & 0x0004)
// netif_link_down(dev);
//else
// netif_link_up(dev);
kprintf("%s: Link changed, link partner %4.4x new duplex %d\n", dev->name, lpar, duplex);
tp->full_duplex = duplex;
// Only count as errors with no link change
status &= ~RxUnderrun;
} else {
// If this does not work, we will do rtl_hw_start
outp(ioaddr + ChipCmd, CmdTxEnb);
rtl8139_set_rx_mode(dev); // Reset the multicast list
outp(ioaddr + ChipCmd, CmdRxEnb | CmdTxEnb);
tp->stats.rx_errors++;
tp->stats.rx_fifo_errors++;
}
}
if (status & (RxOverflow | RxErr | RxFIFOOver)) tp->stats.rx_errors++;
if (status & (PCSTimeout)) tp->stats.rx_length_errors++;
if (status & RxFIFOOver) tp->stats.rx_fifo_errors++;
if (status & RxOverflow) {
tp->stats.rx_over_errors++;
tp->cur_rx = inpw(ioaddr + RxBufAddr) % tp->rx_buf_len;
outpw(ioaddr + RxBufPtr, tp->cur_rx - 16);
}
if (status & PCIErr) {
unsigned long pci_cmd_status;
pci_cmd_status = pci_read_config_dword(dev->unit, PCI_CONFIG_CMD_STAT);
kprintf(KERN_ERR "%s: PCI Bus error %4.4x.\n", dev->name, pci_cmd_status);
}
}
/* WARNING: I have no hardware to verify this works */
uint32_t pci_read_cfg_TYPE2(uint8_t bus,uint8_t card,uint8_t func,uint8_t reg,uint8_t size) {
const uint16_t pt = 0xC000 + (card << 8) + reg;
pci_type2_select(bus,func);
switch (size) {
case 2: return inpd(pt);
case 1: return inpw(pt);
case 0: return inp(pt);
}
return ~0UL;
}
uint32_t dosbox_id_read_data_nrl() {
uint32_t r;
#if TARGET_MSDOS == 32
r = (uint32_t)inpd(DOSBOX_IDPORT(DOSBOX_ID_DATA));
#else
r = (uint32_t)inpw(DOSBOX_IDPORT(DOSBOX_ID_DATA));
r |= (uint32_t)inpw(DOSBOX_IDPORT(DOSBOX_ID_DATA)) << (uint32_t)16UL;
#endif
return r;
}
static int mdio_write(long ioaddr, int phy_id, int location, int value) {
int val, boguscnt = 64 * 10; // <64 usec. to complete, typ 27 ticks
outpd(ioaddr + SCBCtrlMDI, 0x04000000 | (location << 16) | (phy_id << 21) | value);
do {
val = inpd(ioaddr + SCBCtrlMDI);
if (--boguscnt < 0) {
kprintf(KERN_WARNING "eepro100: mdio_write() timed out with val = %8.8x\n", val);
break;
}
} while (!(val & 0x10000000));
return val & 0xffff;
}
uint32_t dosbox_id_read_regsel() {
uint32_t r;
dosbox_id_reset_latch();
#if TARGET_MSDOS == 32
r = (uint32_t)inpd(DOSBOX_IDPORT(DOSBOX_ID_INDEX));
#else
r = (uint32_t)inpw(DOSBOX_IDPORT(DOSBOX_ID_INDEX));
r |= (uint32_t)inpw(DOSBOX_IDPORT(DOSBOX_ID_INDEX)) << (uint32_t)16UL;
#endif
return r;
}
static void rtl8139_tx_timeout(struct dev *dev) {
struct nic *tp = (struct nic *) dev->privdata;
long ioaddr = tp->iobase;
int status = inpw(ioaddr + IntrStatus);
int mii_reg;
unsigned int i;
kprintf("%s: Transmit timeout, status %2.2x %4.4x media %2.2x\n",
dev->name, inp(ioaddr + ChipCmd), status, inp(ioaddr + GPPinData));
if (status & (TxOK | RxOK)) {
kprintf("%s: RTL8139 Interrupt line blocked, status %x\n", dev->name, status);
}
// Disable interrupts by clearing the interrupt mask
outpw(ioaddr + IntrMask, 0x0000);
// Emit info to figure out what went wrong
kprintf("%s: Tx queue start entry %d dirty entry %d\n", dev->name, tp->cur_tx, tp->dirty_tx);
for (i = 0; i < NUM_TX_DESC; i++) {
kprintf("%s: Tx descriptor %d is %8.8x.%s\n",
dev->name, i, inpd(ioaddr + TxStatus0 + i*4),
i == tp->dirty_tx % NUM_TX_DESC ? " (queue head)" : "");
}
kprintf("%s: MII #%d registers are:", dev->name, tp->phys[0]);
for (mii_reg = 0; mii_reg < 8; mii_reg++) kprintf(" %4.4x", mdio_read(dev, tp->phys[0], mii_reg));
kprintf("\n");
// Dump the unsent Tx packets
for (i = 0; i < NUM_TX_DESC; i++) {
if (tp->tx_pbuf[i]) {
pbuf_free(tp->tx_pbuf[i]);
tp->tx_pbuf[i] = NULL;
tp->stats.tx_dropped++;
}
}
// Reset chip
rtl_hw_start(dev);
// Clear tx ring
tp->dirty_tx = tp->cur_tx = 0;
set_sem(&tp->tx_sem, NUM_TX_DESC);
}
/*++
********************************************************************************
**
** FUNCTION:
** HECIReadPCI
**
** DESCRIPTION:
** Perform a PCI read through PCI data/index pair
**
** ARGUMENTS:
** [IN] offset - Offset into the HECI devices PCI config space
**
** RETURNS:
** U32 of data from selected PCI address
**
********************************************************************************
--*/
U32 HECIReadPCI(U8 offset)
{
//
//
// IMPORTANT NOTE - This function is a hack and was only added as a
// workaround for a HECI hardware issue. This cannot be used in a generic way
// to support HECI 2 as currently written
//
//
U32 address;
// always reads from HECI device at Bus0, Device3, Func 0
address = (0x80000000 | 0 << 16 | 3 << 11 | 0 << 8 | offset);
outpd(0xcf8, address);
return (inpd(0xcfc));
}
/************************
*
* hwt_read
*
* Stop hardware timer and read time elapsed since last start.
*
* u_long hwt_read(smc) ;
* In
* smc - A pointer to the SMT Context structure.
* Out
* The elapsed time since last start in units of 16us.
*
************************/
u_long hwt_read(struct s_smc *smc)
{
u_short tr ;
u_long is ;
if (smc->hw.timer_activ) {
hwt_stop(smc) ;
tr = (u_short)((inpd(ADDR(B2_TI_VAL))/200) & 0xffff) ;
is = GET_ISR() ;
/* Check if timer expired (or wraparound). */
if ((tr > smc->hw.t_start) || (is & IS_TIMINT)) {
hwt_restart(smc) ;
smc->hw.t_stop = smc->hw.t_start ;
}
else
smc->hw.t_stop = smc->hw.t_start - tr ;
}
<<<<<<< HEAD
zx_status_t PioCfgWrite(uint32_t addr, uint32_t val, size_t width) {
AutoSpinLock lock(&pio_lock);
size_t shift = (addr & 0x3) * 8u;
if (shift + width > 32) {
return ZX_ERR_INVALID_ARGS;
}
uint32_t width_mask = WidthMask(width);
uint32_t write_mask = width_mask << shift;
outpd(kPciConfigAddr, (addr & ~0x3) | kPciCfgEnable);
uint32_t tmp_val = LE32(inpd(kPciConfigData));
val &= width_mask;
tmp_val &= ~write_mask;
tmp_val |= (val << shift);
outpd(kPciConfigData, LE32(tmp_val));
return ZX_OK;
}
U32 mpt_read32(mpt_adap_t *adap, int offset, int bar)
{
U32 data;
#if DOS
if (bar == adap->mem)
data = *(U32 *)(adap->mem_virt + offset);
else if (bar == adap->diagmem)
data = *(U32 *)(adap->diagmem_virt + offset);
else
data = inpd(adap->io_addr + offset);
#endif
#if EFI
if (bar == adap->mem || bar == adap->diagmem)
adap->pci_io->Mem.Read(adap->pci_io, EfiPciIoWidthUint32, (char)bar, offset, 1, &data);
else
adap->pci_io->Io.Read(adap->pci_io, EfiPciIoWidthUint32, (char)bar, offset, 1, &data);
#endif
return data;
}
static int rtl8139_close(struct dev *dev) {
struct nic *tp = (struct nic *) dev->privdata;
long ioaddr = tp->iobase;
int i;
//netif_stop_tx_queue(dev);
kprintf("%s: Shutting down ethercard, status was 0x%4.4x\n", dev->name, inpw(ioaddr + IntrStatus));
// Disable interrupts by clearing the interrupt mask
outpw(ioaddr + IntrMask, 0x0000);
// Stop the chip's Tx and Rx DMA processes
outp(ioaddr + ChipCmd, 0x00);
// Update the error counts
tp->stats.rx_missed_errors += inpd(ioaddr + RxMissed);
outpd(ioaddr + RxMissed, 0);
del_timer(&tp->timer);
disable_irq(tp->irq);
for (i = 0; i < NUM_TX_DESC; i++) {
if (tp->tx_pbuf[i]) pbuf_free(tp->tx_pbuf[i]);
tp->tx_pbuf[i] = NULL;
}
kfree(tp->rx_ring);
tp->rx_ring = NULL;
// Green! Put the chip in low-power mode
outp(ioaddr + Cfg9346, 0xC0);
outp(ioaddr + Config1, tp->config1 | 0x03);
outp(ioaddr + HltClk, 'H'); // 'R' would leave the clock running
return 0;
}
trap_retval ReqRead_io( void )
{
read_io_req *acc;
void *ret;
trap_elen len;
/* Perform I/O on the target machine on behalf of the debugger.
* Since there are no kernel APIs in Linux to do this, we just
* enable IOPL and use regular I/O. We will bail if we can't get
* IOPL=3, so the debugger trap file will need to be run as root
* before it can be used for I/O access.
*/
acc = GetInPtr( 0 );
ret = GetOutPtr( 0 );
#ifdef __WATCOMC__
if( iopl( 3 ) == 0 ) {
len = acc->len;
switch( len ) {
case 1:
*((unsigned_8*)ret) = inpb( acc->IO_offset );
break;
case 2:
*((unsigned_16*)ret) = inpw( acc->IO_offset );
break;
case 4:
*((unsigned_32*)ret) = inpd( acc->IO_offset );
break;
}
} else {
len = 0;
}
#else
len = 0;
#endif
return( len );
}
static void do_slow_command(struct dev *dev, int cmd) {
struct nic *sp = (struct nic *) dev->privdata;
long cmd_ioaddr = sp->iobase + SCBCmd;
int wait = 0;
while (++wait <= 200) {
if (inp(cmd_ioaddr) == 0) break;
}
if (wait > 100) kprintf(KERN_WARNING "%s: Command %4.4x was never accepted (%d polls)!\n", dev->name, inp(cmd_ioaddr), wait);
outp(cmd_ioaddr, cmd);
for (wait = 0; wait <= 100; wait++) {
if (inp(cmd_ioaddr) == 0) return;
}
for (; wait <= 20000; wait++) {
if (inp(cmd_ioaddr) == 0) {
return;
} else {
udelay(1);
}
}
kprintf(KERN_WARNING "%s: Command %4.4x was not accepted after %d polls! Current status %8.8x\n", dev->name, cmd, wait, inpd(sp->iobase + SCBStatus));
}
static void rtl8139_dpc(void *arg) {
struct dev *dev = (struct dev *) arg;
struct nic *np = (struct nic *) dev->privdata;
struct nic *tp = np;
int boguscnt = np->max_interrupt_work;
long ioaddr = tp->iobase;
int link_changed = 0;
while (1) {
int status = inpw(ioaddr + IntrStatus);
// Acknowledge all of the current interrupt sources ASAP, but
// first get an additional status bit from CSCR
if (status & RxUnderrun) link_changed = inpw(ioaddr + CSCR) & CSCR_LinkChangeBit;
outpw(ioaddr + IntrStatus, status);
//kprintf("%s: dpc status=%#4.4x new intstat=%#4.4x\n", dev->name, status, inpw(ioaddr + IntrStatus));
if ((status & (PCIErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver | TxErr | TxOK | RxErr | RxOK)) == 0) break;
if (status & (RxOK | RxUnderrun | RxOverflow | RxFIFOOver)) {
// Rx interrupt
rtl8139_rx(dev);
}
if (status & (TxOK | TxErr)) {
unsigned int dirty_tx = tp->dirty_tx;
int entries_freed = 0;
while (tp->cur_tx - dirty_tx > 0) {
int entry = dirty_tx % NUM_TX_DESC;
int txstatus = inpd(ioaddr + TxStatus0 + entry * 4);
if (!(txstatus & (TxStatOK | TxUnderrun | TxAborted))) break; // It still hasn't been Txed
// Note: TxCarrierLost is always asserted at 100mbps
if (txstatus & (TxOutOfWindow | TxAborted)) {
// There was an major error, log it
kprintf("%s: Transmit error, Tx status %8.8x\n", dev->name, txstatus);
tp->stats.tx_errors++;
if (txstatus & TxAborted) {
tp->stats.tx_aborted_errors++;
outpd(ioaddr + TxConfig, TX_DMA_BURST << 8);
}
if (txstatus & TxCarrierLost) tp->stats.tx_carrier_errors++;
if (txstatus & TxOutOfWindow) tp->stats.tx_window_errors++;
} else {
//kprintf("%s: Transmit done, Tx status %8.8x\n", dev->name, txstatus);
if (txstatus & TxUnderrun) {
// Add 64 to the Tx FIFO threshold
if (tp->tx_flag < 0x00300000) tp->tx_flag += 0x00020000;
tp->stats.tx_fifo_errors++;
}
tp->stats.collisions += (txstatus >> 24) & 15;
tp->stats.tx_bytes += txstatus & 0x7ff;
tp->stats.tx_packets++;
}
// Free the original pbuf
pbuf_free(tp->tx_pbuf[entry]);
tp->tx_pbuf[entry] = NULL;
entries_freed++;
dirty_tx++;
}
tp->dirty_tx = dirty_tx;
release_sem(&tp->tx_sem, entries_freed);
}
// Check uncommon events with one test
if (status & (PCIErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver | TxErr | RxErr)) {
if (status == 0xffff) break; // Missing chip!
rtl_error(dev, status, link_changed);
}
if (--boguscnt < 0) {
kprintf("%s: Too much work at interrupt, IntrStatus=0x%4.4x\n", dev->name, status);
// Clear all interrupt sources
outpw(ioaddr + IntrStatus, 0xffff);
break;
}
}
void main()
{
unsigned long transmitted;
transmitted = inpd( DEVICE );
}
/**
* Clears a given set of bits in a register.
*/
static void ahci_ctrl_clear_bits(uint16_t iobase, uint16_t reg, uint32_t mask)
{
outpd(iobase + AHCI_REG_IDX, reg);
outpd(iobase + AHCI_REG_DATA, inpd(iobase + AHCI_REG_DATA) & ~mask);
}
/**
* Returns whether at least one of the bits in the given mask is set
* for a register.
*/
static uint8_t ahci_ctrl_is_bit_set(uint16_t iobase, uint16_t reg, uint32_t mask)
{
outpd(iobase + AHCI_REG_IDX, reg);
return (inpd(iobase + AHCI_REG_DATA) & mask) != 0;
}
void PortD(void) // PORTD
{
port=(unsigned short)AT;
datalong=(unsigned long)inpd(port);
AT=(int32)datalong;
}
