/***********************************************************************
*
* Function: sd_start_data_write
*
* Purpose: Start data write transfer operations to a card
*
* Processing:
* If the number of blocks to transfer is 0, return an error status
* to the caller. Install the standard data transmit interrupt
* handler. Set the data block size and data timeout clocks in the
* controller. Clear any latched data interrupts. Fill the transmit
* FIFO and decrement the amount to send by the filled amount.
* Enable data transfer interrupts as needed by the transmit
* interrupt handler. Decrement the number of blocks to transfer in
* the interrupt handler.
*
* Parameters:
* cmdreg : Command control register value
*
* Outputs: None
*
* Returns: _NO_ERROR if the configuration was ok, otherwise _ERROR
*
* Notes: None
*
**********************************************************************/
static STATUS sd_start_data_write(UNS_32 cmdreg)
{
volatile UNS_32 tmp;
UNS_32 datalen;
STATUS status = _ERROR;
/* Determine data length from block count */
datalen = sdcarddat.dctrl.blocksize *
sdcarddat.dctrl.xferdat.blocks;
if ((datalen > 0) && (datalen <= 65024))
{
/* Number of words to send */
sdcarddat.dctrl.tosend = datalen >> 2;
/* Set standard transmit handler */
int_install_irq_handler(IRQ_SD1, (PFV) sd1_tx_interrupt);
/* Decrement block count for start of transfer */
sdcarddat.dctrl.xferdat.blocks--;
/* Setup blocksize, data length, data timeout, and direction */
sdcarddat.regptr->sd_dtimer = sdcarddat.dctrl.data_to;
sdcarddat.regptr->sd_dlen = datalen;
sdcarddat.regptr->sd_dctrl &= ~SD_DIR_FROMCARD;
/* Start command state machine */
sdcarddat.regptr->sd_cmd = (cmdreg | SD_CPST_EN);
int_enable(IRQ_SD1);
status = _NO_ERROR;
}
/***********************************************************************
* Function: I2Cinit
* Purpose:I2C初始化函数
* Processing:
* 设置波特率
* 设置中断
**********************************************************************/
void I2Cinit(unsigned int i2c_clk)
{
I2CCLK_CTRL=0x03;
I2C1->i2c_ctrl= 1<<8;
while ((I2C1->i2c_ctrl &(1<<8))!=0);
switch(i2c_clk)
{
case I2C_CLK_100K:
I2C1->i2c_clk_hi= 520;
I2C1->i2c_clk_lo=520;
break;
case I2C_CLK_400K:
I2C1->i2c_clk_hi=96;
I2C1->i2c_clk_lo=166;
break;
default:
break;
}
int_install_irq_handler(IRQ_I2C_1,I2C_int_handler);
}
/***********************************************************************
*
* Function: c_entry
*
* Purpose: Application entry point from the startup code
*
* Processing:
* See function.
*
* Parameters: None
*
* Outputs: None
*
* Returns: Always returns 1, or <0 on an error
*
* Notes: None
*
**********************************************************************/
int c_entry(void)
{
SWIM_WINDOW_T win1;
COLOR_T *fblog;
INT_32 lcddev;
/* Disable interrupts in ARM core */
disable_irq_fiq();
/* Setup miscellaneous board functions */
phy3250_board_init();
/* Set virtual address of MMU table */
cp15_set_vmmu_addr((void *)
(IRAM_BASE + (256 * 1024) - (16 * 1024)));
/* Initialize interrupt system */
int_initialize(0xFFFFFFFF);
/* Install standard IRQ dispatcher at ARM IRQ vector */
int_install_arm_vec_handler(IRQ_VEC, (PFV) lpc32xx_irq_handler);
/* Install RTC interrupt handler as a IRQ interrupts */
int_install_irq_handler(IRQ_RTC, (PFV) rtc_user_interrupt);
/* Open RTC */
rtcdev = rtc_open(RTC, 0);
if (rtcdev == 0)
{
/* Error */
return -1;
}
/* Set a 1s match rate */
secs = lsecs = 0;
mstp.match_num = 0;
mstp.use_match_int = TRUE;
mstp.enable_onsw = FALSE;
mstp.match_tick_val = secs + 1;
rtc_ioctl(rtcdev, RTC_ENABLE, 0);
rtc_ioctl(rtcdev, RTC_SET_COUNT, 0);
rtc_ioctl(rtcdev, RTC_CLEAR_INTS, RTC_MATCH0_INT_STS);
rtc_ioctl(rtcdev, RTC_SETUP_MATCH, (INT_32) &mstp);
/* Setup LCD muxing for STN Color 16BPP */
clkpwr_setup_lcd(CLKPWR_LCDMUX_TFT16, 1);
/* Enable clock to LCD block (HCLK_EN)*/
clkpwr_clk_en_dis(CLKPWR_LCD_CLK, 1);
/* Setup LCD paramaters in the LCD controller */
lcddev = lcd_open(CLCDC, (INT_32) & LCD_DISPLAY);
/* Upper Panel Frame Base Address register */
lcd_ioctl(lcddev, LCD_SET_UP_FB, PHY_LCD_FRAME_BUF);
/* Enable LCD controller and power signals */
lcd_ioctl(lcddev, LCD_PWENABLE, 1);
/* Enable LCD backlight */
phy3250_lcd_backlight_enable(TRUE);
/* Enable LCD power */
phy3250_lcd_power_enable(TRUE);
/* Set frame buffer address */
fblog = (COLOR_T *) cp15_map_physical_to_virtual(PHY_LCD_FRAME_BUF);
/* Create a SWIM window */
swim_window_open(&win1, LCD_DISPLAY.pixels_per_line,
LCD_DISPLAY.lines_per_panel, fblog, 0, 0,
(LCD_DISPLAY.pixels_per_line - 1), (LCD_DISPLAY.lines_per_panel - 1),
1, WHITE, BLACK, BLACK);
swim_put_ltext(&win1, "RTC example: This example will print the message "
"TICK whenever an RTC interrupt occurs (1 second intervals). It will "
"quit after 10 seconds\n");
/* Enable RTC (starts counting) */
rtc_ioctl(rtcdev, RTC_ENABLE, 1);
/* Enable RTC interrupt in the interrupt controller */
int_enable(IRQ_RTC);
/* Enable IRQ interrupts in the ARM core */
enable_irq();
/* Loop for 10 seconds and let interrupts toggle the LEDs */
while (secs < 10)
{
if (lsecs < secs)
{
swim_put_ltext(&win1, "TICK\n");
lsecs = secs;
}
}
/* Disable RTC interrupt in the interrupt controller */
int_disable(IRQ_RTC);
/* Disable interrupts in ARM core */
disable_irq_fiq();
/* Prior to closing the RTC, the ONSW key value is set. This will
allow the RTC to keep it's value across resets as long as RTC
power is maintained */
rtc_ioctl(rtcdev, RTC_SETCLR_KEY, 1);
/* Close RTC and LCD */
rtc_close(rtcdev);
lcd_close(lcddev);
return 1;
}
/***********************************************************************
*
* Function: c_entry
*
* Purpose: Application entry point from the startup code
*
* Processing:
* See function.
*
* Parameters: None
*
* Outputs: None
*
* Returns: Always returns 1, or <0 on an error
*
* Notes: None
*
**********************************************************************/
int c_entry(void)
{
MST_MATCH_SETUP_T mstp;
/* Disable interrupts in ARM core */
disable_irq_fiq();
/* Set virtual address of MMU table */
cp15_set_vmmu_addr((void *)
(IRAM_BASE + (256 * 1024) - (16 * 1024)));
/* Initialize interrupt system */
int_initialize(0xFFFFFFFF);
/* Install standard IRQ dispatcher at ARM IRQ vector */
int_install_arm_vec_handler(IRQ_VEC, (PFV) lpc32xx_irq_handler);
/* Install mstimer interrupts handlers as a IRQ interrupts */
int_install_irq_handler(IRQ_MSTIMER, (PFV) mstimer_user_interrupt);
/* Open mstimer */
mstimerdev = mstimer_open(MSTIMER, 0);
if (mstimerdev == 0)
{
/* Error */
return -1;
}
/* Set a 10mS match rate */
mstp.timer_num = 0;
mstp.use_int = TRUE;
mstp.stop_on_match = FALSE;
mstp.reset_on_match = TRUE;
mstp.tick_val = 0;
mstp.ms_val = MSTICKRATE;
mstimer_ioctl(mstimerdev, MST_CLEAR_INT, 0);
mstimer_ioctl(mstimerdev, MST_TMR_SETUP_MATCH, (INT_32) &mstp);
/* Reset terminal count */
mstimer_ioctl(mstimerdev, MST_TMR_RESET, 0);
/* Enable mstimer (starts counting) */
msecs = 0;
mstimer_ioctl(mstimerdev, MST_TMR_ENABLE, 1);
/* Enable mstimer interrupts in the interrupt controller */
int_enable(IRQ_MSTIMER);
/* Enable IRQ interrupts in the ARM core */
enable_irq();
/* Loop for 10 seconds and let interrupts toggle the LEDs */
while (msecs < MSTIMEOUT);
/* Disable mstimer interrupts in the interrupt controller */
int_disable(IRQ_MSTIMER);
/* Disable interrupts in ARM core */
disable_irq_fiq();
/* Close mstimer */
mstimer_close(mstimerdev);
return 1;
}
/**********************************************************************
*
* Function: c_entry
*
* Purpose: Application entry point from the startup code
*
* Processing:
* See function.
*
* Parameters: None
*
* Outputs: None
*
* Returns: Nothing
*
* Notes: None
*
*********************************************************************/
void c_entry(void)
{
SWIM_WINDOW_T win1;
COLOR_T clr, *fblog;
int idx;
UNS_16 xgs, ygs, curx, cury, curym, xidx;
/* Disable interrupts in ARM core */
disable_irq_fiq();
/* Set virtual address of MMU table */
cp15_set_vmmu_addr((void *)
(IRAM_BASE + (256 * 1024) - (16 * 1024)));
/* Initialize interrupt system */
int_initialize(0xFFFFFFFF);
/* Install standard IRQ dispatcher at ARM IRQ vector */
int_install_arm_vec_handler(IRQ_VEC, (PFV) lpc32xx_irq_handler);
/* Setup miscellaneous board functions */
phy3250_board_init();
/* enable clock to ADC block - 32KHz clock */
clkpwr_clk_en_dis(CLKPWR_ADC_CLK,1);
/* TSC IRQ goes active when the FIFO reaches the Interrupt level */
int_install_irq_handler(IRQ_TS_IRQ, (PFV) tsc_user_interrupt);
/* Enable interrupt */
int_enable(IRQ_TS_IRQ);
/* Open TSC, sets default timing values, fifo = 16,
resolution = 10bits */
tscdev = tsc_open(TSC, 0);
/* TSC Auto mode enable, this also sets AUTO bit */
tsc_ioctl(tscdev,TSC_AUTO_EN, 1);
/* Setup LCD muxing for STN Color 16BPP */
clkpwr_setup_lcd(CLKPWR_LCDMUX_TFT16, 1);
/* Enable clock to LCD block (HCLK_EN)*/
clkpwr_clk_en_dis(CLKPWR_LCD_CLK, 1);
/* Setup LCD paramaters in the LCD controller */
lcddev = lcd_open(CLCDC, (INT_32) &LCD_DISPLAY);
/* Upper Panel Frame Base Address register */
lcd_ioctl(lcddev, LCD_SET_UP_FB, PHY_LCD_FRAME_BUF);
/* Enable LCD controller and power signals */
lcd_ioctl(lcddev, LCD_PWENABLE, 1);
/* Enable LCD backlight */
phy3250_lcd_backlight_enable(TRUE);
/* Enable LCD power */
phy3250_lcd_power_enable(TRUE);
/* write cursor image array data to cursor image RAM */
lcd_ioctl(lcddev, LCD_CRSR_INIT_IMG, (INT_32) &cursorimage[0]);
/* enable the default cursor 0 */
lcd_ioctl(lcddev,LCD_CRSR_EN,1);
/* set the cursor X/Y position */
lcd_ioctl(lcddev, LCD_CRSR_XY, 0x0);
/* set the cursor pallette BGR value, col0*/
lcd_ioctl(lcddev, LCD_CRSR_PAL0, 0x00ff0000);
/* set the cursor pallette BGR value, col1 */
lcd_ioctl(lcddev, LCD_CRSR_PAL1, 0x000000ff);
/* Enable IRQ interrupts in the ARM core */
enable_irq();
/* Set frame buffer address */
fblog = (COLOR_T *)cp15_map_physical_to_virtual(PHY_LCD_FRAME_BUF);
/* Create a SWIM window */
swim_window_open(&win1, LCD_DISPLAY.pixels_per_line,
LCD_DISPLAY.lines_per_panel, fblog, 0, 0,
(LCD_DISPLAY.pixels_per_line - 1),
(LCD_DISPLAY.lines_per_panel - 1),
1, WHITE, BLACK, BLACK);
/* Compute vertical size for bars */
ygs = LCD_DISPLAY.lines_per_panel / 3;
/* Draw Red bars */
cury = 0;
curx = 0;
curym = ygs - 1;
xgs = LCD_DISPLAY.pixels_per_line / RED_COLORS;
clr = BLACK;
for (xidx = 0; xidx < RED_COLORS; xidx++)
{
swim_set_pen_color(&win1, clr);
for (idx = 0; idx <= xgs; idx++)
{
swim_put_line(&win1, curx, cury, curx, curym);
curx++;
}
clr = clr + 0x0800;
}
/* Draw green bars */
cury = cury + ygs;
curx = 0;
curym = cury + (ygs - 1);
xgs = LCD_DISPLAY.pixels_per_line / GREEN_COLORS;
clr = BLACK;
for (xidx = 0; xidx < GREEN_COLORS; xidx++)
{
swim_set_pen_color(&win1, clr);
for (idx = 0; idx <= xgs; idx++)
{
swim_put_line(&win1, curx, cury, curx, curym);
curx++;
}
clr = clr + 0x0020;
}
/* Draw blue bars */
cury = cury + ygs;
curx = 0;
curym = cury + (ygs - 1);
xgs = LCD_DISPLAY.pixels_per_line / BLUE_COLORS;
clr = BLACK;
for (xidx = 0; xidx < BLUE_COLORS; xidx++)
{
swim_set_pen_color(&win1, clr);
for (idx = 0; idx <= xgs; idx++)
{
swim_put_line(&win1, curx, cury, curx, curym);
curx++;
}
clr = clr + 0x0001;
}
/* lets stay here forever */
while(1);
}
/***********************************************************************
*
* Function: sd0_cmd_interrupt
*
* Purpose: Default SD card command interrupt handler
*
* Processing:
* This function is called when an SD0 card interrupt is generated.
* This will save the command status and response if it is valid.
* The command state machine is cleared and any commands interrupts
* are cleared and masked. If the user defined command callback
* function exists, then it is called before exiting this function.
*
* Parameters: None
*
* Outputs: None
*
* Returns: Nothing
*
* Notes: The user callback function is called in interrupt context.
*
**********************************************************************/
static void sd0_cmd_interrupt(void)
{
int idx;
volatile UNS_32 tmp;
UNS_32 cmd;
/* Save status */
sdcarddat.dctrl.resp.cmd_status = sdcarddat.regptr->sd_status;
/* Save response */
sdcarddat.dctrl.resp.cmd_resp [0] = sdcarddat.regptr->sd_respcmd;
for (idx = 0; idx < 4; idx++)
{
sdcarddat.dctrl.resp.cmd_resp [idx + 1] =
sdcarddat.regptr->sd_resp [idx];
}
/* Stop command state machine */
sdcarddat.regptr->sd_cmd &= ~SD_CPST_EN;
/* Clear pending command statuses */
sdcarddat.regptr->sd_clear = (SD_CMD_CRC_FAIL | SD_CMD_TIMEOUT |
SD_CMD_RESP_RECEIVED | SD_CMD_SENT);
sdcarddat.regptr->sd_mask0 = 0;
if (sdcarddat.dctrl.xferdat.dataop == SD_DATAOP_WRITE)
{
/* Start data state machine */
sdcarddat.regptr->sd_dctrl |= SD_DATATRANSFER_EN;
/* Clear FIFO conditions */
sdcarddat.regptr->sd_clear = (SD_FIFO_TXDATA_HEMPTY |
SD_DATABLK_END | SD_FIFO_TXDATA_UFLOW | SD_DATA_TIMEOUT |
SD_DATA_CRC_FAIL);
if (sdcarddat.dmact.dma_enabled == TRUE)
{
/* Set DMA receive handler */
int_install_irq_handler(IRQ_SD1, (PFV) sd1_dmatx_interrupt);
/* Setup FIFO control conditions to interrupt when data
block has been received, start bit errors, data FIFO
overflow, data timeout, or data CRC error */
sdcarddat.regptr->sd_mask1 = (SD_DATA_END |
SD_FIFO_TXDATA_UFLOW | SD_DATA_TIMEOUT |
SD_DATA_CRC_FAIL);
sdcarddat.regptr->sd_dctrl |= SD_DMA_EN;
/* Setup DMA transfer */
if (sdcarddat.dctrl.xferdat.buff != NULL)
{
/* Setup source */
sdcarddat.dmact.pdmaregs->dma_chan [sdcarddat.
dmact.dmach].src_addr = (UNS_32) sdcarddat.dctrl.xferdat.buff;
sdcarddat.dmact.pdmaregs->dma_chan [sdcarddat.
dmact.dmach].lli = 0;
sdcarddat.dmact.pdmaregs->dma_chan [sdcarddat.
dmact.dmach].dest_addr = (UNS_32) & SDCARD->sd_fifo;
sdcarddat.dmact.pdmaregs->dma_chan [sdcarddat.
dmact.dmach].control = (DMAC_CHAN_SRC_AUTOINC |
DMAC_CHAN_SRC_AHB1 | DMAC_CHAN_DEST_WIDTH_32 |
DMAC_CHAN_SRC_WIDTH_32 | DMAC_CHAN_DEST_BURST_8 |
DMAC_CHAN_SRC_BURST_8);
}
/* Set DMA initial control */
sdcarddat.dmact.pdmaregs->sync |= DMA_PER_SDCARD;
/* Setup DMA config and start DMA controller */
sdcarddat.dmact.pdmaregs->dma_chan [sdcarddat.
dmact.dmach].config_ch = (DMAC_CHAN_IE | DMAC_CHAN_FLOW_P_M2P |
DMAC_DEST_PERIP(DMA_PERID_SDCARD) | DMAC_CHAN_ENABLE);
}
else
{
/* If not DMA, use FIFO mode */
/* Setup FIFO control conditions to interrupt when FIFO is
empty or half empty, data block has been trasmitted, data
has ended, data underflow, or data CRC error */
sdcarddat.regptr->sd_mask1 = (SD_FIFO_TXDATA_HEMPTY |
SD_DATABLK_END | SD_FIFO_TXDATA_UFLOW | SD_DATA_TIMEOUT |
SD_DATA_CRC_FAIL);
/* Enable DMA if needed */
sdcarddat.regptr->sd_dctrl &= ~SD_DMA_EN;
/* Fill transmit FIFO */
while ((sdcarddat.regptr->sd_status &
SD_FIFO_TXDATA_FULL) == 0)
{
sdcarddat.regptr->sd_fifo [0] =
*sdcarddat.dctrl.xferdat.buff;
sdcarddat.dctrl.xferdat.buff++;
sdcarddat.dctrl.tosend -= 1;
}
}
}
/* If a pending command is being used to stop this transfer,
then set it up now */
if (sdcarddat.dctrl.xferdat.usependcmd == TRUE)
{
sdcarddat.dctrl.xferdat.usependcmd = FALSE;
cmd = prep_cmd(&sdcarddat.dctrl.xferdat.pendcmd);
sdcarddat.regptr->sd_cmd = (cmd | 0 |
SD_CMDPEND_WAIT);
}
else
{
/* Disable SDMMC interrupt for now */
int_disable(IRQ_SD0);
/* Call command callback function if it exists */
if (sdcarddat.sd0_cb != NULL)
{
sdcarddat.sd0_cb();
}
}
}
/***********************************************************************
*
* Function: c_entry
*
* Purpose: Application entry point from the startup code
*
* Processing:
* See function.
*
* Parameters: None
*
* Outputs: None
*
* Returns: Always returns 1
*
* Notes: None
*
**********************************************************************/
int c_entry(void)
{
TMR_PSCALE_SETUP_T pscale;
TMR_MATCH_SETUP_T msetup;
/* Disable interrupts in ARM core */
disable_irq_fiq();
/* Set virtual address of MMU table */
cp15_set_vmmu_addr((void *)
(IRAM_BASE + (256 * 1024) - (16 * 1024)));
/* Initialize interrupt system */
int_initialize(0xFFFFFFFF);
/* Install standard IRQ dispatcher at ARM IRQ vector */
int_install_arm_vec_handler(IRQ_VEC, (PFV) lpc32xx_irq_handler);
/* Install timer interrupts handlers as a IRQ interrupts */
int_install_irq_handler(IRQ_TIMER0, (PFV) timer0_user_interrupt);
int_install_irq_handler(IRQ_TIMER1, (PFV) timer1_user_interrupt);
/* Open timers - this will enable the clocks for all timers when
match control, match output, and capture control functions
disabled. Default clock will be internal. */
timer0dev = timer_open(TIMER_CNTR0, 0);
timer1dev = timer_open(TIMER_CNTR1, 0);
/******************************************************************/
/* Setup timer 0 for a 10Hz match rate */
/* Use a prescale count time of 100uS */
pscale.ps_tick_val = 0; /* Use ps_us_val value */
pscale.ps_us_val = 100; /* 100uS */
timer_ioctl(timer0dev, TMR_SETUP_PSCALE, (INT_32) &pscale);
/* Use a match count value of 1000 (1000 * 100uS = 100mS (10Hz)) */
msetup.timer_num = 0; /* Use match register set 0 (of 0..3) */
msetup.use_match_int = TRUE; /* Generate match interrupt on match */
msetup.stop_on_match = FALSE; /* Do not stop timer on match */
msetup.reset_on_match = TRUE; /* Reset timer counter on match */
msetup.match_tick_val = 999; /* Match is when timer count is 1000 */
timer_ioctl(timer0dev, TMR_SETUP_MATCH, (INT_32) &msetup);
/* Clear any latched timer 0 interrupts and enable match
interrupt */
timer_ioctl(timer0dev, TMR_CLEAR_INTS,
(TIMER_CNTR_MTCH_BIT(0) | TIMER_CNTR_MTCH_BIT(1) |
TIMER_CNTR_MTCH_BIT(2) | TIMER_CNTR_MTCH_BIT(3) |
TIMER_CNTR_CAPT_BIT(0) | TIMER_CNTR_CAPT_BIT(1) |
TIMER_CNTR_CAPT_BIT(2) | TIMER_CNTR_CAPT_BIT(3)));
/******************************************************************/
/******************************************************************/
/* Setup timer 1 for a 4.9Hz match rate */
/* Use a prescale count time of 100uS */
pscale.ps_tick_val = 0; /* Use ps_us_val value */
pscale.ps_us_val = 10; /* 100uS */
timer_ioctl(timer1dev, TMR_SETUP_PSCALE, (INT_32) &pscale);
/* Use a match value of 490 (490 * 100uS) */
msetup.timer_num = 0; /* Use match register set 0 (of 0..3) */
msetup.use_match_int = TRUE; /* Generate match interrupt on match */
msetup.stop_on_match = FALSE; /* Do not stop timer on match */
msetup.reset_on_match = TRUE; /* Reset timer counter on match */
msetup.match_tick_val = 489;
timer_ioctl(timer1dev, TMR_SETUP_MATCH, (INT_32) &msetup);
/* Clear any latched timer 1 interrupts and enable match
interrupt */
timer_ioctl(timer1dev, TMR_CLEAR_INTS,
(TIMER_CNTR_MTCH_BIT(0) | TIMER_CNTR_MTCH_BIT(1) |
TIMER_CNTR_MTCH_BIT(2) | TIMER_CNTR_MTCH_BIT(3) |
TIMER_CNTR_CAPT_BIT(0) | TIMER_CNTR_CAPT_BIT(1) |
TIMER_CNTR_CAPT_BIT(2) | TIMER_CNTR_CAPT_BIT(3)));
/******************************************************************/
/* Enable timers (starts counting) */
msecs = 0;
timer_ioctl(timer0dev, TMR_ENABLE, 1);
timer_ioctl(timer1dev, TMR_ENABLE, 1);
/* Enable timer interrupts in the interrupt controller */
int_enable(IRQ_TIMER0);
int_enable(IRQ_TIMER1);
/* Enable IRQ interrupts in the ARM core */
enable_irq();
/* Loop for 20 seconds and let interrupts toggle the LEDs */
while (msecs < (10 * 1000));
/* Disable timer interrupts in the interrupt controller */
int_disable(IRQ_TIMER0);
int_disable(IRQ_TIMER1);
/* Disable interrupts in ARM core */
disable_irq_fiq();
/* Close timers */
timer_close(timer0dev);
timer_close(timer1dev);
return 1;
}
void ici_hdw_init(void)
{
//register long i;
UART_CBS_T cbs;
UART_CONTROL_T ucntl;
//- typedef enum
//- {
//- UART_PAR_NONE,
//- UART_PAR_EVEN,
//- UART_PAR_ODD
//- } UART_PAR_T;
//-
//- /* UART control */
//- typedef struct
//- {
//- UNS_32 baud_rate; /* Device baud rate */
//- UART_PAR_T parity; /* Parity selection */
//- UNS_32 databits; /* Number of data bits */
//- UNS_32 stopbits; /* Number of stop bits */
//- } UART_CONTROL_T;
timer0dev = Timer_open(TIMER_CNTR0, 0);
TIMER_CNTR_REGS_T *pTimer = TIMER_CNTR0;
/*
//-* Reset timer *-/
pTimer->tcr = TIMER_CNTR_TCR_RESET;
pTimer->tcr = 0;
//-* Count mode is PCLK edge *-/
pTimer->ctcr = TIMER_CNTR_SET_MODE(TIMER_CNTR_CTCR_TIMER_MODE);
//-* Set prescale counter value for a 1uS tick *-/
pTimer->pr = (UNS_32) Timer_usec_to_val(
CLKPWR_TIMER0_CLK, 1);
//case TMR_VALUE_ST:
// status = pTimer->tc;
// break;
//-* Enable the timer *-/
pTimer->tcr = TIMER_CNTR_TCR_EN;
//-* Stop timer *-/
//pTimer->tcr = 0;
*/
//Init Module New
//-* Enable timer system clock *-/
//.clkpwr_clk_en_dis(timer_num_to_clk_enum[timernum], 1);
//-* Reset timer *-/
pTimer->tcr = TIMER_CNTR_TCR_RESET;
pTimer->tcr = 0;pTimer->tc = 0;
//-* Clear and enable match function *-/
pTimer->ir = TIMER_CNTR_MTCH_BIT(0);
//-* Count mode is PCLK edge *-/
pTimer->ctcr = TIMER_CNTR_SET_MODE(TIMER_CNTR_CTCR_TIMER_MODE);
//-* Set prescale counter value for a 1uS tick *-/
pTimer->pr = (UNS_32) Timer_usec_to_val(
CLKPWR_TIMER0_CLK, 1);
//-* Set match for number of usecs *-/
pTimer->mr[0] = 20000;//-usec;
//-* Interrupt on match 0 *-/
pTimer->mcr = TIMER_CNTR_MCR_MTCH(0)|TIMER_CNTR_MCR_RESET(0);
//-* Install timer interrupts handlers as a IRQ interrupts *-/
int_install_irq_handler(IRQ_TIMER0, (PFV) timer0_user_interrupt);
//~ ucntl.baud_rate = 115200;
//~ ucntl.parity = UART_PAR_NONE;
//~ ucntl.databits = 8;
//~ ucntl.stopbits = 1;
//~ uartdev = Uart_open((void *) UART3, (INT_32) & ucntl);
//~ if (uartdev != 0)
//~ {
//~ /* Setup RX and TX callbacks */
//~ cbs.rxcb = recv_cb;
//~ cbs.txcb = send_cb;
//~ cbs.rxerrcb = NULL;
//~ Uart_ioctl(uartdev, UART_INSTALL_CBS, (INT_32) &cbs);
//~ //.int_enable(IRQ_UART_IIR3);
//~ }
//~
//~ /* Initialize TX and RX ring buffers */
//~ //txfill = txget = rxfill = rxget = txsize = rxsize = 0;
//~ Rst_LpduHSU2_TpCnState();
//~ /* Enable interrupts */
//~ int_enable(IRQ_UART_IIR3);
//~ hs7_uart_hdw_init();
//~ hs1_uart_hdw_init();
//~ hs2_uart_hdw_init();
//~
//~ enable_irq();
//~ //int_enable(IRQ_UART_IIR7);
//~ int_enable(IRQ_UART_IIR1);
//~ int_enable(IRQ_UART_IIR2);
ssp1_hdr_init();
Rst_LpduM2m_TpCnState();
Rst_LpduSpi_TpCnState();
GPIO->p0_mux_clr = 0xff;
GPIO->p0_dir_clr = 0xff;
GPIO->p0_dir_set = 0xf0;
GPIO->p0_outp_clr =0xf0;
M16_J18_K18_A15_PioInit();
//p3_outp_state
AppReqTransmitTotVerInfoBrBs = 1;
Int_install_ext_irq_handler(IRQ_GPIO_01,P02Int,FALLING_EDGE,0);//Interrupt in this place never can be workd look p606 datasheet - Only pin sic[8] activated
Int_install_ext_irq_handler(IRQ_P0_P1_IRQ,P02Int,FALLING_EDGE,0);
CLKPWR ->clkpwr_p01_er = CLKPWR_INTSRC_GPIO_01_BIT;// *((long*)0x40004018) |= 2;
Int_enable(IRQ_GPIO_01);
Int_enable(IRQ_P0_P1_IRQ);
MIC->er |= (1<<(IRQ_SUB2IRQ));
//~^ pTimer->tcr = TIMER_CNTR_TCR_EN;//timer_ioctl(timer0dev, TMR_ENABLE, 1);
//~^ int_enable(IRQ_TIMER0);
}
/**********************************************
ИНИЦИАЛИЗАЦИЯ СИСТЕМЫ ПРЕРЫВАНИЙ
**********************************************/
void InitializeInterruptSystem()
{
/* Initialize interrupt system */
int_initialize(0xFFFFFFFF);
/* Install standard IRQ dispatcher at ARM IRQ vector */
int_install_arm_vec_handler(IRQ_VEC, (PFV) lpc32xx_irq_handler);
/* Install standard FIQ dispatcher at ARM IRQ vector */
int_install_arm_vec_handler(FIQ_VEC, (PFV) lpc32xx_fiq_handler);
//---------------------HSTIMER------------------------------------
/* Install HSTIMER interrupt handler as a IRQ interrupts */
int_install_irq_handler(IRQ_HSTIMER,
(PFV) hstimer_user_interrupt);
// Save address of register block
hst_regptr = HSTIMER;
gpio_regptr = GPIO;
// LEDs off
//gpio_regptr->p3_outp_clr = LED1 | LED2;
//gpio_regptr->p1_dir_set = LED3;
// Enable timer system clock
clkpwr_clk_en_dis(CLKPWR_HSTIMER_CLK, 1);
// Disable high speed timer and match timers
hst_regptr->hstim_ctrl = HSTIM_CTRL_RESET_COUNT;
hst_regptr->hstim_mctrl = 0;
hst_regptr->hstim_ctrl = 0;
// Clear pending interrupts
hst_regptr->hstim_int = (HSTIM_MATCH0_INT |
HSTIM_MATCH1_INT | HSTIM_MATCH2_INT |
HSTIM_GPI_06_INT | HSTIM_RTC_TICK_INT);
hst_regptr->hstim_mctrl = HSTIM_CNTR_MCR_MTCH(0) | HSTIM_CNTR_MCR_RESET(0);
hst_regptr->hstim_pmatch = 13-1;
hst_regptr->hstim_match[0] = 1000;//1ms 000;
hst_regptr->hstim_ctrl = HSTIM_CTRL_COUNT_ENAB;//start hstimer
// Enable interrupt in the interrupt controller
int_enable(IRQ_HSTIMER);
//---------------------SSP1------------------------------------
ssp1_regptr = SSP1; // Pointer to SSP1 registers
// Enable ssp1 system clock
clkpwr_clk_en_dis(CLKPWR_SSP1_CLK, 1);
//конфигурация IO
gpio_regptr->p2_mux_clr = P2_GPIO04_SSEL1;
gpio_regptr->p2_dir_set = P2_DIR_GPIO(4);
gpio_regptr->p3_outp_set = P3_STATE_GPIO(4);
/* The MISO, MOSI, and SCK signals are controlled by the SSP1 */
gpio_regptr->p_mux_set = (P_SPI2DATAIO_MOSI1 |
P_SPI2DATAIN_MISO1 | P_SPI2CLK_SCK1);
ssp1_regptr->cpsr = SSP_CPSR_CPDVSR(16);//8);//4);//4);//prescale
//ssp_clk / ((cr0_div + 1) * prescale);
//prescale = 16; SCR = 4 - 1.25MGz
ssp1_regptr->cr0 = SSP_CR0_DSS(8) |//data size 8 bit
SSP_CR0_FRF_SPI |//Motorola SPI mode
SSP_CR0_SCR(4);//serial clock rate
// Default Master mode
// Disable SSP1
ssp1_regptr->cr1 &= ~SSP_CR1_SSP_ENABLE;
// interr handler SSP1 IRQ
//int_install_irq_handler(IRQ_SSP1, (PFV) ssp1_user_interrupt);
// Enable interrupt in the interrupt controller
//int_enable(IRQ_SSP1);
// Clear interrupt in the interrupt controller
//int_clear(IRQ_SSP1);
// Enable SSP1
ssp1_regptr->cr1 |= SSP_CR1_SSP_ENABLE;
}//InitializeInterruptSystem()
