static void crystalcove_gpio_set(struct gpio_chip *chip,
		unsigned gpio, int value)
{
	u8 ctlo = gpio < 8 ? GPIO0P0CTLO + gpio : GPIO1P0CTLO + (gpio - 8);

	if (value)
		intel_mid_pmic_setb(ctlo, 1);
	else
		intel_mid_pmic_clearb(ctlo, 1);
}
static int pmic_fg_reg_clearb(struct pmic_fg_info *info, int reg, u8 mask)
{
       int ret;

       ret = intel_mid_pmic_clearb(reg, mask);
       if (ret < 0)
               dev_err(&info->pdev->dev, "pmic reg set mask err:%d\n", ret);

       return ret;
}
static void __crystalcove_irq_mask(int gpio, int mask)
{
	u8 mirqs0 = gpio < 8 ? MGPIO0IRQS0 : MGPIO1IRQS0;
	int offset = gpio < 8 ? gpio : gpio - 8;

	if (mask)
		intel_mid_pmic_setb(mirqs0, 1 << offset);
	else
		intel_mid_pmic_clearb(mirqs0, 1 << offset);
}
static void __crystalcove_irq_type(int gpio, int type)
{
	int offset = gpio < 8 ? gpio : gpio - 8;
	u8 ctli = gpio < 8 ? GPIO0P0CTLI + gpio : GPIO1P0CTLI + (gpio - 8);

	type &= IRQ_TYPE_EDGE_BOTH;
	intel_mid_pmic_clearb(ctli, CTLI_INTCNT_BE);
	if (type == IRQ_TYPE_EDGE_BOTH)
		intel_mid_pmic_setb(ctli, CTLI_INTCNT_BE);
	else if (type == IRQ_TYPE_EDGE_RISING)
		intel_mid_pmic_setb(ctli, CTLI_INTCNT_PE);
	else if (type & IRQ_TYPE_EDGE_FALLING)
		intel_mid_pmic_setb(ctli, CTLI_INTCNT_NE);
}
static int pmic_chrg_reg_clearb(struct pmic_chrg_info *info, int reg, u8 mask)
{
    int ret, i;

    for (i = 0; i < RETRY_RW; i++) {
        ret = intel_mid_pmic_clearb(reg, mask);
        if (ret < 0) {
            dev_warn(&info->pdev->dev,
                     "failed to clear reg 0x%x: %d\n", reg, ret);
            usleep_range(1000, 2000);
        } else
            break;
    }

    return ret;
}