static int crystalcove_chgr_enable_charging(struct chgr_info *info, bool enable)
{
int ret;
dev_info(&info->pdev->dev, "crystalcove enable chargering\n");
ret = crystalcove_chgr_enable_charger(info, true);
if (ret < 0)
dev_warn(&info->pdev->dev, "vbus disable failed\n");
if (enable) {
ret = intel_mid_pmic_writeb(CRYSTALCOVE_MCHGRIRQS0_REG, 0x00);
if (ret < 0)
dev_warn(&info->pdev->dev, "chgr mask disable failed\n");
else
ret = intel_mid_pmic_writeb(CRYSTALCOVE_MCHGRIRQSX_REG, 0x00);
} else {
ret = intel_mid_pmic_writeb(CRYSTALCOVE_MCHGRIRQS0_REG, 0x01);
if (ret < 0)
dev_warn(&info->pdev->dev, "chgr mask enable failed\n");
else
ret = intel_mid_pmic_writeb(CRYSTALCOVE_MCHGRIRQSX_REG, 0x01);
}
return ret;
}
static void pmic_fg_init_hw_regs(struct pmic_fg_info *info)
{
/* program temperature thresholds */
intel_mid_pmic_writeb(DC_FG_VLTFW_REG, FG_VLTFW_N5C);
intel_mid_pmic_writeb(DC_FG_VHTFW_REG, FG_VHTFW_60C);
/* enable interrupts */
intel_mid_pmic_setb(DC_TEMP_IRQ_CFG_REG, TEMP_IRQ_CFG_MASK);
intel_mid_pmic_setb(DC_FG_IRQ_CFG_REG, FG_IRQ_CFG_LOWBATT_MASK);
}
static int __devinit crystalcove_gpadc_probe(struct platform_device *pdev)
{
int err;
struct gpadc_info *info;
struct iio_dev *indio_dev;
intel_mid_pmic_writeb(MADCIRQ0, 0x00);
intel_mid_pmic_writeb(MADCIRQ1, 0x00);
indio_dev = iio_allocate_device(sizeof(struct gpadc_info));
if (indio_dev == NULL) {
dev_err(&pdev->dev, "allocating iio device failed\n");
return -ENOMEM;
}
info = iio_priv(indio_dev);
mutex_init(&info->lock);
init_waitqueue_head(&info->wait);
info->dev = &pdev->dev;
info->irq = platform_get_irq(pdev, 0);
err = request_threaded_irq(info->irq, NULL, gpadc_isr,
IRQF_ONESHOT, "adc", indio_dev);
if (err) {
dev_err(&pdev->dev, "unable to register irq %d\n", info->irq);
goto err_free_device;
}
platform_set_drvdata(pdev, indio_dev);
indio_dev->dev.parent = &pdev->dev;
indio_dev->name = pdev->name;
indio_dev->channels = crystalcove_adc_channels;
indio_dev->num_channels = ARRAY_SIZE(crystalcove_adc_channels);
indio_dev->info = &crystalcove_adc_info;
indio_dev->modes = INDIO_DIRECT_MODE;
err = iio_map_array_register(indio_dev, iio_maps);
if (err)
goto err_release_irq;
err = iio_device_register(indio_dev);
if (err < 0)
goto err_array_unregister;
dev_info(&pdev->dev, "crystalcove adc probed\n");
return 0;
err_array_unregister:
iio_map_array_unregister(indio_dev, iio_maps);
err_release_irq:
free_irq(info->irq, info);
err_free_device:
iio_free_device(indio_dev);
return err;
}
static irqreturn_t gpadc_isr(int irq, void *data)
{
struct gpadc_info *info = iio_priv(data);
u8 pending0, pending1;
pending0 = intel_mid_pmic_readb(ADCIRQ0);
pending1 = intel_mid_pmic_readb(ADCIRQ1);
intel_mid_pmic_writeb(ADCIRQ0, pending0);
intel_mid_pmic_writeb(ADCIRQ0, pending1);
info->irq_pending |= pending0 + (pending1 << 8);
wake_up(&info->wait);
return IRQ_HANDLED;
}
/*
* WA for BTY as simple VRF management
*/
int camera_set_pmic_power(enum camera_pmic_pin pin, bool flag)
{
u8 reg_addr[CAMERA_POWER_NUM] = {VPROG_1P8V, VPROG_2P8V};
u8 reg_value[2] = {VPROG_DISABLE, VPROG_ENABLE};
static struct vprog_status status[CAMERA_POWER_NUM];
static DEFINE_MUTEX(mutex_power);
int ret = 0;
mutex_lock(&mutex_power);
/*
* only set power at:
* first to power on
* last to power off
*/
if ((flag && status[pin].user == 0)
|| (!flag && status[pin].user == 1))
ret = intel_mid_pmic_writeb(reg_addr[pin], reg_value[flag]);
/* no update counter if config failed */
if (ret)
goto done;
if (flag)
status[pin].user++;
else
if (status[pin].user)
status[pin].user--;
done:
mutex_unlock(&mutex_power);
return ret;
}
/**
* intel_pmic_reg_setvoltage - Set voltage to the regulator
* @rdev: regulator_dev structure
* @min_uV: Minimum required voltage in uV
* @max_uV: Maximum acceptable voltage in uV
* @selector: Voltage value passed back to core layer
* Sets a voltage regulator to the desired output voltage
* @return value : Returns 0 if success
* : Return error value on failure
*/
static int intel_pmic_reg_setvoltage(struct regulator_dev *rdev, int min_uV,
int max_uV, unsigned *selector)
{
struct intel_pmic_info *pmic_info = rdev_get_drvdata(rdev);
int reg_value;
u8 vsel;
for (vsel = 0; vsel < pmic_info->table_len; vsel++) {
int mV = pmic_info->table[vsel];
int uV = mV * 1000;
if (min_uV > uV || uV > max_uV)
continue;
*selector = vsel;
reg_value = intel_mid_pmic_readb(pmic_info->pmic_reg);
if (reg_value < 0) {
dev_err(&rdev->dev,
"intel_mid_pmic_readb returns error %08x\n", reg_value);
return reg_value;
}
reg_value &= ~REG_VSEL_MASK;
reg_value |= vsel << VSEL_SHIFT;
dev_dbg(&rdev->dev,
"intel_pmic_reg_setvoltage voltage: %u uV\n", uV);
return intel_mid_pmic_writeb(pmic_info->pmic_reg, reg_value);
}
return -EINVAL;
}
static void p088pw_disable(struct intel_dsi_device *dsi)
{
int val = 0;
struct intel_dsi *intel_dsi = container_of(dsi, struct intel_dsi, dev);
struct drm_device *dev = intel_dsi->base.base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
DRM_DEBUG_KMS("\n");
printk("p088pw_disable\n");
msleep(200);
dsi_vc_dcs_write_0(intel_dsi, 0, 0x28);
msleep(80);
dsi_vc_dcs_write_0(intel_dsi, 0, 0x10);
msleep(34);
val = intel_mid_pmic_readb(0x12);
val &= ~(1<<5);
intel_mid_pmic_writeb(0x12, val);
usleep_range(100000, 120000);
vlv_gpio_nc_write(dev_priv, GPIO_NC_9_PCONF0, 0x2000CC00);
vlv_gpio_nc_write(dev_priv, GPIO_NC_9_PAD, 0x00000004);
usleep_range(100000, 120000);
vlv_gpio_nc_write(dev_priv, GPIO_NC_10_PCONF0, 0x2000CC00);
vlv_gpio_nc_write(dev_priv, GPIO_NC_10_PAD, 0x00000004);
usleep_range(100000, 120000);
vlv_gpio_nc_write(dev_priv, GPIO_NC_11_PCONF0, 0x2000CC00);
vlv_gpio_nc_write(dev_priv, GPIO_NC_11_PAD, 0x00000004);
}
void p088pw_reset(struct intel_dsi_device *dsi)
{
int val;
struct intel_dsi *intel_dsi = container_of(dsi, struct intel_dsi, dev);
struct drm_device *dev = intel_dsi->base.base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
DRM_DEBUG_KMS("\n");
//printk("p088pw_reset\n");
val = intel_mid_pmic_readb(0x12);
val |= 1<<5;
intel_mid_pmic_writeb(0x12, val);
usleep_range(100000, 120000);
vlv_gpio_nc_write(dev_priv, GPIO_NC_9_PCONF0, 0x2000CC00);//reset
vlv_gpio_nc_write(dev_priv, GPIO_NC_9_PAD, 0x00000004);
usleep_range(100000, 120000);
vlv_gpio_nc_write(dev_priv, GPIO_NC_10_PCONF0, 0x2000CC00);
vlv_gpio_nc_write(dev_priv, GPIO_NC_10_PAD, 0x00000005);
usleep_range(100000, 120000);
vlv_gpio_nc_write(dev_priv, GPIO_NC_11_PCONF0, 0x2000CC00);
vlv_gpio_nc_write(dev_priv, GPIO_NC_11_PAD, 0x00000005);
msleep(10);
vlv_gpio_nc_write(dev_priv, GPIO_NC_9_PCONF0, 0x2000CC00);
vlv_gpio_nc_write(dev_priv, GPIO_NC_9_PAD, 0x00000005);
}
static int crystalcove_gpio_direction_input(struct gpio_chip *chip,
unsigned gpio)
{
u8 ctlo = gpio < 8 ? GPIO0P0CTLO + gpio : GPIO1P0CTLO + (gpio - 8);
intel_mid_pmic_writeb(ctlo, CTLO_INPUT_DEF);
return 0;
}
static int crystalcove_gpio_direction_output(struct gpio_chip *chip,
unsigned gpio, int value)
{
u8 ctlo = gpio < 8 ? GPIO0P0CTLO + gpio : GPIO1P0CTLO + (gpio - 8);
intel_mid_pmic_writeb(ctlo, CTLO_OUTPUT_DEF | value);
return 0;
}
void auo_reset(struct intel_dsi_device *dsi)
{
int val;
DRM_DEBUG_KMS("\n");
val = intel_mid_pmic_readb(0x12);
val |= 1<<5;
intel_mid_pmic_writeb(0x12, val);
msleep(40);
}
void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
{
struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
int pipe = intel_crtc->pipe;
u32 val;
DRM_DEBUG_KMS("\n");
I915_WRITE_BITS(MIPI_DEVICE_READY(pipe), ULPS_STATE_ENTER | DEVICE_READY,
ULPS_STATE_MASK | DEVICE_READY);
usleep_range(2000, 2500);
I915_WRITE_BITS(MIPI_DEVICE_READY(pipe), ULPS_STATE_EXIT | DEVICE_READY,
ULPS_STATE_MASK | DEVICE_READY);
usleep_range(2000, 2500);
I915_WRITE_BITS(MIPI_DEVICE_READY(pipe), ULPS_STATE_ENTER | DEVICE_READY,
ULPS_STATE_MASK | DEVICE_READY);
usleep_range(2000, 2500);
if (wait_for(((I915_READ(MIPI_PORT_CTRL(pipe)) & 0x20000)
== 0x00000), 30))
DRM_ERROR("DSI LP not going Low\n");
I915_WRITE_BITS(MIPI_PORT_CTRL(pipe), 0, LP_OUTPUT_HOLD);
usleep_range(1000, 1500);
I915_WRITE_BITS(MIPI_DEVICE_READY(pipe), 0x00, DEVICE_READY);
usleep_range(2000, 2500);
intel_disable_dsi_pll(intel_dsi);
val = I915_READ(DSPCLK_GATE_D);
val &= ~VSUNIT_CLOCK_GATE_DISABLE;
I915_WRITE(DSPCLK_GATE_D, val);
if (intel_dsi->dev.dev_ops->disable_panel_power)
intel_dsi->dev.dev_ops->disable_panel_power(&intel_dsi->dev);
#ifdef CONFIG_CRYSTAL_COVE
if (BYT_CR_CONFIG) {
/* Disable Panel */
vlv_gpio_nc_write(dev_priv, GPIO_NC_11_PCONF0, 0x2000CC00);
vlv_gpio_nc_write(dev_priv, GPIO_NC_11_PAD, 0x00000004);
udelay(500);
} else
intel_mid_pmic_writeb(PMIC_PANEL_EN, 0x00);
#else
/* need to code for BYT-CR for example where things have changed */
DRM_ERROR("PANEL Disable to supported yet\n");
#endif
msleep(intel_dsi->panel_off_delay);
msleep(intel_dsi->panel_pwr_cycle_delay);
}
static int imx134_power_ctrl(struct v4l2_subdev *sd, int flag)
{
int ret = 0;
if (flag) {
if (!camera_vprog1_on) {
#ifdef CONFIG_CRYSTAL_COVE
ret = intel_mid_pmic_writeb(VPROG_2P8V, VPROG_ENABLE);
if (ret)
return ret;
ret = intel_mid_pmic_writeb(VPROG_1P8V, VPROG_ENABLE);
#elif defined(CONFIG_INTEL_SCU_IPC_UTIL)
ret = intel_scu_ipc_msic_vprog1(1);
#else
pr_err("imx134 power is not set.\n");
#endif
if (!ret) {
/* imx1x5 VDIG rise to XCLR release */
usleep_range(1000, 1200);
camera_vprog1_on = 1;
}
return ret;
}
} else {
if (camera_vprog1_on) {
#ifdef CONFIG_CRYSTAL_COVE
ret = intel_mid_pmic_writeb(VPROG_2P8V, VPROG_DISABLE);
if (ret)
return ret;
ret = intel_mid_pmic_writeb(VPROG_1P8V, VPROG_DISABLE);
#elif defined(CONFIG_INTEL_SCU_IPC_UTIL)
ret = intel_scu_ipc_msic_vprog1(0);
#else
pr_err("imx134 power is not set.\n");
#endif
if (!ret)
camera_vprog1_on = 0;
return ret;
}
}
return ret;
}
static irqreturn_t pmic_irq_thread(int irq, void *data)
{
int i;
int pending;
mutex_lock(&pmic->irq_lock);
intel_mid_pmic_writeb(MIRQLVL1, (u8)pmic->irq_mask);
pending = intel_mid_pmic_readb(IRQLVL1) & (~pmic->irq_mask);
for (i = 0; i < PMIC_IRQ_NUM; i++)
if (pending & (1 << i))
handle_nested_irq(pmic->irq_base + i);
mutex_unlock(&pmic->irq_lock);
return IRQ_HANDLED;
}
static void auo_disable(struct intel_dsi_device *dsi)
{
struct intel_dsi *intel_dsi = container_of(dsi, struct intel_dsi, dev);
int val = 0;
DRM_DEBUG_KMS("\n");
dsi_vc_dcs_write_0(intel_dsi, 0, 0x28);
msleep(80);
dsi_vc_dcs_write_0(intel_dsi, 0, 0x10);
msleep(34);
val = intel_mid_pmic_readb(0x12);
val &= ~(1<<5);
intel_mid_pmic_writeb(0x12, val);
}
/**
* intel_pmic_reg_disable - To disable the regulator
* @rdev: regulator_dev structure
* @return value :0 - Regulator disabling success
* :nonzero - Regulator disabling failed
*/
static int intel_pmic_reg_disable(struct regulator_dev *rdev)
{
struct intel_pmic_info *pmic_info = rdev_get_drvdata(rdev);
int reg_value;
reg_value = intel_mid_pmic_readb(pmic_info->pmic_reg);
if (reg_value < 0) {
dev_err(&rdev->dev,
"intel_mid_pmic_readb returns error %08x\n", reg_value);
return reg_value;
}
return intel_mid_pmic_writeb(pmic_info->pmic_reg,
((reg_value | REG_CNT_ENBL) & REG_OFF));
}
/**
* intel_pmic_reg_get_cntrl - To get the control of the regulator
* @rdev: regulator_dev structure
* @return value :0 - success
* :nonzero - Error
*/
static int intel_pmic_reg_initialize(u16 pmic_reg, u8 state)
{
int reg_value;
u8 val;
reg_value = intel_mid_pmic_readb(pmic_reg);
if (reg_value < 0)
return reg_value;
if (state)
val = reg_value | REG_CNT_ENBL | REG_ON;
else
val = (reg_value & REG_OFF) | REG_CNT_ENBL;
return intel_mid_pmic_writeb(pmic_reg, val);
}
static int pmic_chrg_reg_writeb(struct pmic_chrg_info *info, int reg, u8 val)
{
int ret, i;
for (i = 0; i < RETRY_RW; i++) {
ret = intel_mid_pmic_writeb(reg, val);
if (ret < 0) {
dev_warn(&info->pdev->dev,
"failed to write reg 0x%x: %d\n", reg, ret);
usleep_range(1000, 2000);
} else
break;
}
return ret;
}
static int pmic_fg_reg_writeb(struct pmic_fg_info *info, int reg, u8 val)
{
int ret, i;
for (i = 0; i < NR_RETRY_CNT; i++) {
ret = intel_mid_pmic_writeb(reg, val);
if (ret == -EAGAIN || ret == -ETIMEDOUT)
continue;
else
break;
}
if (ret < 0)
dev_err(&info->pdev->dev, "pmic reg write err:%d\n", ret);
return ret;
}
static int pmic_irq_init(void)
{
int cur_irq;
int ret;
pmic->irq_mask = 0xff;
intel_mid_pmic_writeb(MIRQLVL1, pmic->irq_mask);
pmic->irq_mask = intel_mid_pmic_readb(MIRQLVL1);
pmic->irq_base = irq_alloc_descs(VV_PMIC_IRQBASE, 0, PMIC_IRQ_NUM, 0);
if (pmic->irq_base < 0) {
dev_warn(pmic->dev, "Failed to allocate IRQs: %d\n",
pmic->irq_base);
pmic->irq_base = 0;
return -EINVAL;
}
/* Register them with genirq */
for (cur_irq = pmic->irq_base;
cur_irq < PMIC_IRQ_NUM + pmic->irq_base;
cur_irq++) {
irq_set_chip_data(cur_irq, pmic);
irq_set_chip_and_handler(cur_irq, &pmic_irq_chip,
handle_edge_irq);
irq_set_nested_thread(cur_irq, 1);
irq_set_noprobe(cur_irq);
}
ret = request_threaded_irq(pmic->irq, pmic_irq_isr, pmic_irq_thread,
IRQF_TRIGGER_RISING | IRQF_ONESHOT,
"intel_mid_pmic", pmic);
if (ret != 0) {
dev_err(pmic->dev, "Failed to request IRQ %d: %d\n",
pmic->irq, ret);
return ret;
}
ret = enable_irq_wake(pmic->irq);
if (ret != 0) {
dev_warn(pmic->dev, "Can't enable PMIC IRQ as wake source: %d\n",
ret);
}
return 0;
}
static irqreturn_t crystalcove_gpio_irq_handler(int irq, void *data)
{
struct crystalcove_gpio *cg = data;
int pending;
int gpio;
pending = intel_mid_pmic_readb(GPIO0IRQ) & 0xff;
pending |= (intel_mid_pmic_readb(GPIO1IRQ) & 0xff) << 8;
intel_mid_pmic_writeb(GPIO0IRQ, pending & 0xff);
intel_mid_pmic_writeb(GPIO1IRQ, (pending >> 8) & 0xff);
local_irq_disable();
for (gpio = 0; gpio < cg->chip.ngpio; gpio++) {
if (pending & (1 << gpio)) {
pr_err("crystalcove pin %d triggered\n", gpio);
generic_handle_irq(cg->irq_base + gpio);
}
}
local_irq_enable();
return IRQ_HANDLED;
}
/*
* WA for BTY as simple VRF management
*/
int camera_set_pmic_power(enum camera_pmic_pin pin, bool flag)
{
u8 reg_addr[CAMERA_POWER_NUM] = {VPROG_1P8V, VPROG_2P8V};
u8 reg_value[2] = {VPROG_DISABLE, VPROG_ENABLE};
int val;
static DEFINE_MUTEX(mutex_power);
int ret = 0;
if (pin >= CAMERA_POWER_NUM)
return -EINVAL;
mutex_lock(&mutex_power);
val = intel_mid_pmic_readb(reg_addr[pin]) & 0x3;
if ((flag && (val == VPROG_DISABLE)) ||
(!flag && (val == VPROG_ENABLE)))
ret = intel_mid_pmic_writeb(reg_addr[pin], reg_value[flag]);
mutex_unlock(&mutex_power);
return ret;
}
static irqreturn_t crystalcove_chgr_isr(int irq, void *data)
{
struct chgr_info *info = data;
int chgrirq;
chgrirq = intel_mid_pmic_readb(CRYSTALCOVE_CHGRIRQ_REG);
if (chgrirq < 0) {
dev_err(&info->pdev->dev, "CHGRIRQ read failed\n");
goto pmic_irq_fail;
}
dev_dbg(&info->pdev->dev, "crystalcove charger irq happens, chgrirq=%x\n", chgrirq);
/*--------------CHGRIRQ HANDLER--------------*/
power_supply_changed(&info->psy_usb);
pmic_irq_fail:
intel_mid_pmic_writeb(CRYSTALCOVE_CHGRIRQ_REG, chgrirq);
return IRQ_HANDLED;
}
static int ov8865_power_ctrl(struct v4l2_subdev *sd, int flag)
{
int ret = 0;
int value = 0;
ov8865_power_pins();
if (flag) {
if (!camera_vprog1_on) {
#ifdef CONFIG_CRYSTAL_COVE
/* AVDD on First */
value = intel_mid_pmic_readb(VPROG_3P3V);
value = value | VPROG_ENABLE;
OV8865_PLAT_LOG(1,"try to enable VPROG_3P3V: value=0x%x\n", value);
ret = intel_mid_pmic_writeb(VPROG_3P3V, value);
usleep_range(2000, 2100);
/* power up sequence control via GPIO*/
gpio_set_value(camera_avdd_en, 1);
usleep_range(1000, 1500);
/* DOVDD and DVDD On*/
OV8865_PLAT_LOG(1,"try to enable VPROG_1P8V\n");
ret = intel_mid_pmic_writeb(VPROG_1P8V, VPROG_ENABLE);
if (ret)
return ret;
gpio_set_value(camera_reset, 1); /* reset is active low */
/* ov8865 reset pulse should be more than 2ms
*/
usleep_range(3500, 4000);
/* VCM 2P8 power on*/
OV8865_PLAT_LOG(1,"try to enable VPROG_2P8V\n");
ret = intel_mid_pmic_writeb(VPROG_2P8V, VPROG_ENABLE);
if (ret)
return ret;
#if 0
gpio_set_value(camera_power_down, 1);
//gpio_set_value(camera_dovdd_en, 1);
usleep_range(2500, 3500);
#endif
gpio_set_value(camera_dvdd_en, 1);
gpio_set_value(camera_vcm_en, 1);
usleep_range(1000, 1500);
#elif defined(CONFIG_INTEL_SCU_IPC_UTIL)
ret = intel_scu_ipc_msic_vprog1(1);
#else
pr_err("ov8865 power is not set.\n");
#endif
if (!ret) {
/* ov8865 VDIG rise to XCLR release */
usleep_range(1000, 1200);
camera_vprog1_on = 1;
}
return ret;
}
} else {
if (camera_vprog1_on) {
#ifdef CONFIG_CRYSTAL_COVE
/* power down sequence control via GPIO*/
gpio_set_value(camera_dvdd_en, 0);
gpio_set_value(camera_vcm_en, 0);
usleep_range(2500, 3500);
//gpio_set_value(camera_power_down, 0);
//gpio_set_value(camera_dovdd_en, 0);
/* power down power rail*/
ret = intel_mid_pmic_writeb(VPROG_2P8V, VPROG_DISABLE);
if (ret)
return ret;
ret = intel_mid_pmic_writeb(VPROG_1P8V, VPROG_DISABLE);
gpio_set_value(camera_reset, 0);
gpio_set_value(camera_avdd_en, 0);
/* WA: We don't know previous status of VPROG_3P3V
* So keep it ON here
*/
#elif defined(CONFIG_INTEL_SCU_IPC_UTIL)
ret = intel_scu_ipc_msic_vprog1(0);
#else
pr_err("ov8865 power is not set.\n");
#endif
if (!ret)
camera_vprog1_on = 0;
return ret;
}
}
return ret;
}
static int m10mo_power_ctrl(struct v4l2_subdev *sd, int flag)
{
int ret = 0;
pr_info("M10MO power control. flag=%d\n", flag);
if(Read_PROJ_ID() != PROJ_ID_ZX550ML){
pr_err("M10MO, this is not ZX550ML, break! \n");
return -1;
}
set_flis_value(0x3221, 0x2D18);
#ifdef CONFIG_CRYSTAL_COVE
if (flag) {
ret = intel_mid_pmic_writeb(VPROG_2P8V, VPROG_ENABLE);
if (ret) {
pr_err("Failed to power on V2P8SX.\n");
return ret;
}
ret = intel_mid_pmic_writeb(VPROG_1P2V, VPROG_ENABLE);
if (ret) {
pr_err("Failed to power on V1P2SX.\n");
/* Turn all powers off if one is failed. */
intel_mid_pmic_writeb(VPROG_2P8V, VPROG_DISABLE);
return ret;
}
/* Wait for 8ms to make all the power supplies to be stable. */
usleep_range(8000, 8000);
} else {
/* Turn all powers off even when some are failed. */
if (intel_mid_pmic_writeb(VPROG_2P8V, VPROG_DISABLE))
pr_err("Failed to power off V2P8SX.\n");
if (intel_mid_pmic_writeb(VPROG_1P2V, VPROG_DISABLE))
pr_err("Failed to power off V1P2SX.\n");
}
#else
if (camera_1p2_en < 0) {
lnw_gpio_set_alt(55, LNW_GPIO);
ret = camera_sensor_gpio(55,"INT_CAM_1V2_EN", GPIOF_DIR_OUT, 0);
if (ret < 0){
printk("camera_1p2_en is not available.\n");
return ret;
}
camera_1p2_en = ret;
printk(KERN_INFO "M10MO, gpio number, camera_1p2_en is %d\n", camera_1p2_en);
}
switch (Read_HW_ID()) {
case HW_ID_EVB:
case HW_ID_SR1:
case HW_ID_SR2:
case HW_ID_ER:
case HW_ID_ER1_1:
case HW_ID_ER1_2:
case HW_ID_PR:
case HW_ID_pre_PR:
case HW_ID_MP:
if (camera_3p3_en2 < 0) {
gpio_free(58);/////// temp WA.
lnw_gpio_set_alt(58, LNW_GPIO);
ret = camera_sensor_gpio(58, "3X_I2C_LED", GPIOF_DIR_OUT, 0);
if (ret < 0){
printk("GPIO58 is not available.\n");
}else{
camera_3p3_en2 = ret;
printk(KERN_INFO "M10MO, gpio number, camera_3p3_en2 is %d\n", camera_3p3_en2);
}
}
break;
default:
if (camera_3p3_en2 < 0) {
gpio_free(54);/////// temp WA.
lnw_gpio_set_alt(54, LNW_GPIO);
ret = camera_sensor_gpio(54, "3X_I2C_LED", GPIOF_DIR_OUT, 0);
if (ret < 0){
printk("GPIO54 is not available.\n");
}else{
camera_3p3_en2 = ret;
printk(KERN_INFO "M10MO, gpio number, camera_3p3_en2 is %d\n", camera_3p3_en2);
}
}
break;
}//switch
if (camera_2p8_en < 0) {
lnw_gpio_set_alt(56, LNW_GPIO);
ret = camera_sensor_gpio(56,"INT_CAM_2V8_EN", GPIOF_DIR_OUT, 0);
if (ret < 0){
printk("camera_2p8_en not available.\n");
return ret;
}
camera_2p8_en = ret;
printk(KERN_INFO "M10MO, gpio number, camera_2p8_en is %d\n", camera_2p8_en);
}
if (flag) {
/*
static int camera_1p2_en = -1;
static int camera_2p8_en = -1;
static int camera_isp_1p2_en = -1;
*/
if(camera_1p2_en > 0){
printk("@%s %d, project zx550ml pull up GPIO%d\n", __func__, __LINE__, camera_1p2_en);
gpio_set_value(camera_1p2_en, 1);
}
#if 0
ret = intel_scu_ipc_iowrite8(MSIC_VPROG2_MRFLD_CTRL, MSIC_VPROG2_ON_1P8);
if (ret) {
pr_err("Failed to power on M10MO MSIC_VPROG2_ON_1P8.\n");
return ret;
}
#endif
if(camera_3p3_en2 > 0){
mdelay(1);
printk("@%s %d, project zx550ml pull up GPIO%d\n", __func__, __LINE__, camera_3p3_en2);
gpio_set_value(camera_3p3_en2, 1);
}
mdelay(1);
ret = intel_scu_ipc_iowrite8(MSIC_VPROG1_MRFLD_CTRL, MSIC_VPROG1_ON_1P8);
if (ret) {
pr_err("Failed to power on M10MO MSIC_VPROG1_ON_1P8.\n");
return ret;
}else{
printk("@%s %d, project zx550ml pull up Vprog1, 1.8V \n", __func__, __LINE__);
}
if(camera_2p8_en > 0){
printk("@%s %d, project zx550ml pull up GPIO%d\n", __func__, __LINE__, camera_2p8_en);
gpio_set_value(camera_2p8_en, 1);
}
/* Wait for 8ms to make all the power supplies to be stable. */
usleep_range(8000, 8000);
} else {
/*
static int camera_1p2_en = -1;
static int camera_2p8_en = -1;
static int camera_isp_1p2_en = -1;
*/
ret = intel_scu_ipc_iowrite8(MSIC_VPROG1_MRFLD_CTRL, MSIC_VPROG1_OFF);
if (ret) {
pr_err("Failed to power off M10MO MSIC_VPROG1_ON_2P8.\n");
return ret;
}
gpio_set_value(camera_2p8_en, 0);
camera_sensor_gpio_free(camera_2p8_en);
camera_2p8_en = -1;
gpio_set_value(camera_1p2_en, 0);
camera_sensor_gpio_free(camera_1p2_en);
camera_1p2_en = -1;
gpio_set_value(camera_3p3_en2, 0);
camera_sensor_gpio_free(camera_3p3_en2);
camera_3p3_en2 = -1;
camera_sensor_gpio_free(camera_reset);
camera_reset = -1;
}
#endif
return ret;
}
static int camera_pmic_set(bool flag)
{
int val;
int ret = 0;
if (pmic_id == PMIC_MAX) {
pmic_id = camera_pmic_probe();
if (pmic_id == PMIC_MAX)
return -EINVAL;
}
if (flag) {
switch (pmic_id) {
case PMIC_ROHM:
ret = regulator_enable(v2p8_reg);
if (ret)
return ret;
ret = regulator_enable(v1p8_reg);
if (ret)
regulator_disable(v2p8_reg);
break;
case PMIC_XPOWER:
/* ALDO1 */
ret = intel_mid_pmic_writeb(ALDO1_SEL_REG, ALDO1_2P8V);
if (ret)
return ret;
/* PMIC Output CTRL 3 for ALDO1 */
val = intel_mid_pmic_readb(ALDO1_CTRL3_REG);
val |= (1 << ALDO1_CTRL3_SHIFT);
ret = intel_mid_pmic_writeb(ALDO1_CTRL3_REG, val);
if (ret)
return ret;
/* ELDO2 */
ret = intel_mid_pmic_writeb(ELDO2_SEL_REG, ELDO2_1P8V);
if (ret)
return ret;
/* PMIC Output CTRL 2 for ELDO2 */
val = intel_mid_pmic_readb(ELDO2_CTRL2_REG);
val |= (1 << ELDO2_CTRL2_SHIFT);
ret = intel_mid_pmic_writeb(ELDO2_CTRL2_REG, val);
break;
case PMIC_TI:
/* LDO9 */
ret = intel_mid_pmic_writeb(LDO9_REG, LDO9_2P8V_ON);
if (ret)
return ret;
/* LDO10 */
ret = intel_mid_pmic_writeb(LDO10_REG, LDO10_1P8V_ON);
if (ret)
return ret;
break;
default:
return -EINVAL;
}
} else {
switch (pmic_id) {
case PMIC_ROHM:
ret = regulator_disable(v2p8_reg);
ret += regulator_disable(v1p8_reg);
break;
case PMIC_XPOWER:
val = intel_mid_pmic_readb(ALDO1_CTRL3_REG);
val &= ~(1 << ALDO1_CTRL3_SHIFT);
ret = intel_mid_pmic_writeb(ALDO1_CTRL3_REG, val);
if (ret)
return ret;
val = intel_mid_pmic_readb(ELDO2_CTRL2_REG);
val &= ~(1 << ELDO2_CTRL2_SHIFT);
ret = intel_mid_pmic_writeb(ELDO2_CTRL2_REG, val);
break;
case PMIC_TI:
/* LDO9 */
ret = intel_mid_pmic_writeb(LDO9_REG, LDO9_2P8V_OFF);
if (ret)
return ret;
/* LDO10 */
ret = intel_mid_pmic_writeb(LDO10_REG, LDO10_1P8V_OFF);
if (ret)
return ret;
break;
default:
return -EINVAL;
}
}
return ret;
}
static void pmic_work(struct work_struct *work)
{
mutex_lock(&pmic->irq_lock);
intel_mid_pmic_writeb(MIRQLVL1, (u8)pmic->irq_mask);
mutex_unlock(&pmic->irq_lock);
}
static int camera_pmic_set(bool flag)
{
int val;
int ret = 0;
if (pmic_id == PMIC_MAX) {
pmic_id = camera_pmic_probe();
if (pmic_id == PMIC_MAX)
return -EINVAL;
}
if (flag) {
switch (pmic_id) {
case PMIC_ROHM:
ret = regulator_enable(v2p8_reg);
if (ret)
return ret;
ret = regulator_enable(v1p8_reg);
if (ret)
regulator_disable(v2p8_reg);
break;
case PMIC_XPOWER:
/* ALDO1 */
ret = intel_mid_pmic_writeb(0x28, 0x16);
if (ret)
return ret;
/* PMIC Output CTRL 3 for ALDO1 */
val = intel_mid_pmic_readb(0x13);
val |= (1 << 5);
ret = intel_mid_pmic_writeb(0x13, val);
if (ret)
return ret;
/* ELDO2 */
ret = intel_mid_pmic_writeb(0x1A, 0x16);
if (ret)
return ret;
/* PMIC Output CTRL 2 for ELDO2 */
val = intel_mid_pmic_readb(0x12);
val |= (1 << 1);
ret = intel_mid_pmic_writeb(0x12, val);
break;
case PMIC_TI:
/* LDO9 */
ret = intel_mid_pmic_writeb(0x49, 0x2F);
if (ret)
return ret;
/* LDO10 */
ret = intel_mid_pmic_writeb(0x4A, 0x59);
if (ret)
return ret;
/* LDO11 */
ret = intel_mid_pmic_writeb(0x4B, 0x59);
if (ret)
return ret;
break;
default:
return -EINVAL;
}
} else {
switch (pmic_id) {
case PMIC_ROHM:
ret = regulator_disable(v2p8_reg);
ret += regulator_disable(v1p8_reg);
break;
case PMIC_XPOWER:
val = intel_mid_pmic_readb(0x13);
val &= ~(1 << 5);
ret = intel_mid_pmic_writeb(0x13, val);
if (ret)
return ret;
val = intel_mid_pmic_readb(0x12);
val &= ~(1 << 1);
ret = intel_mid_pmic_writeb(0x12, val);
break;
case PMIC_TI:
/* LDO9 */
ret = intel_mid_pmic_writeb(0x49, 0x2E);
if (ret)
return ret;
/* LDO10 */
ret = intel_mid_pmic_writeb(0x4A, 0x58);
if (ret)
return ret;
/* LDO11 */
ret = intel_mid_pmic_writeb(0x4B, 0x58);
if (ret)
return ret;
break;
default:
return -EINVAL;
}
}
return ret;
}
void intel_dsi_device_ready(struct intel_encoder *encoder)
{
struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
int pipe = intel_crtc->pipe;
u32 tmp;
DRM_DEBUG_KMS("\n");
/* program rcomp for compliance
* reduce form 50 ohms to 45 ohms */
intel_flisdsi_write32(dev_priv, 0x04, 0x00f0);
band_gap_reset(dev_priv);
#ifdef CONFIG_CRYSTAL_COVE
/* Panel Enable */
if (BYT_CR_CONFIG) {
/* cabc disable */
vlv_gpio_nc_write(dev_priv, GPIO_NC_9_PCONF0, 0x2000CC00);
vlv_gpio_nc_write(dev_priv, GPIO_NC_9_PAD, 0x00000004);
/* panel enable */
vlv_gpio_nc_write(dev_priv, GPIO_NC_11_PCONF0, 0x2000CC00);
vlv_gpio_nc_write(dev_priv, GPIO_NC_11_PAD, 0x00000005);
udelay(500);
} else
intel_mid_pmic_writeb(PMIC_PANEL_EN, 0x01);
#else
/* need to code for BYT-CR for example where things have changed */
DRM_ERROR("PANEL Enable to supported yet\n");
#endif
msleep(intel_dsi->panel_on_delay);
if (intel_dsi->dev.dev_ops->panel_reset)
intel_dsi->dev.dev_ops->panel_reset(&intel_dsi->dev);
/* Disable DPOunit clock gating, can stall pipe */
tmp = I915_READ(DPLL(pipe));
tmp |= DPLL_RESERVED_BIT;
I915_WRITE(DPLL(pipe), tmp);
tmp = I915_READ(DSPCLK_GATE_D);
tmp |= VSUNIT_CLOCK_GATE_DISABLE;
I915_WRITE(DSPCLK_GATE_D, tmp);
intel_enable_dsi_pll(intel_dsi);
//in dual display config, dsi 0 is not init. so this function may not
//be called with pipe0. set this flag for pipe0 so that pipe b can work
#ifdef BYT_DUAL_MIPI_DSI
if(pipe != 0)
{
I915_WRITE_BITS(MIPI_PORT_CTRL(0), LP_OUTPUT_HOLD,
LP_OUTPUT_HOLD);
usleep_range(1000, 1500);
}
#endif
I915_WRITE_BITS(MIPI_PORT_CTRL(pipe), LP_OUTPUT_HOLD,
LP_OUTPUT_HOLD);
usleep_range(1000, 1500);
I915_WRITE_BITS(MIPI_DEVICE_READY(pipe), DEVICE_READY |
ULPS_STATE_EXIT, DEVICE_READY |
ULPS_STATE_MASK);
usleep_range(2000, 2500);
I915_WRITE_BITS(MIPI_DEVICE_READY(pipe), DEVICE_READY,
DEVICE_READY | ULPS_STATE_MASK);
usleep_range(2000, 2500);
I915_WRITE_BITS(MIPI_DEVICE_READY(pipe), 0x00,
DEVICE_READY | ULPS_STATE_MASK);
usleep_range(2000, 2500);
I915_WRITE_BITS(MIPI_DEVICE_READY(pipe), DEVICE_READY,
DEVICE_READY | ULPS_STATE_MASK);
usleep_range(2000, 2500);
}
void intel_dsi_device_ready(struct intel_encoder *encoder)
{
struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
int pipe = intel_crtc->pipe;
u32 tmp;
int count = 1;
DRM_DEBUG_KMS("\n");
/* program rcomp for compliance
* reduce form 50 ohms to 45 ohms */
intel_flisdsi_write32(dev_priv, 0x04, 0x0004);
band_gap_reset(dev_priv);
#ifdef CONFIG_CRYSTAL_COVE
if (BYT_CR_CONFIG) {
/* cabc disable */
vlv_gpio_nc_write(dev_priv, GPIO_NC_9_PCONF0, 0x2000CC00);
vlv_gpio_nc_write(dev_priv, GPIO_NC_9_PAD, 0x00000004);
/* panel enable */
vlv_gpio_nc_write(dev_priv, GPIO_NC_11_PCONF0, 0x2000CC00);
vlv_gpio_nc_write(dev_priv, GPIO_NC_11_PAD, 0x00000005);
udelay(500);
} else
intel_mid_pmic_writeb(PMIC_PANEL_EN, 0x01);
#else
/* need to code for BYT-CR for example where things have changed */
DRM_ERROR("PANEL Enable to supported yet\n");
#endif
msleep(intel_dsi->panel_on_delay);
if (intel_dsi->dev.dev_ops->panel_reset)
intel_dsi->dev.dev_ops->panel_reset(&intel_dsi->dev);
/* Disable DPOunit clock gating, can stall pipe */
tmp = I915_READ(DPLL(pipe));
tmp |= DPLL_RESERVED_BIT;
I915_WRITE(DPLL(pipe), tmp);
tmp = I915_READ(DSPCLK_GATE_D);
tmp |= VSUNIT_CLOCK_GATE_DISABLE;
I915_WRITE(DSPCLK_GATE_D, tmp);
intel_enable_dsi_pll(intel_dsi);
if (intel_dsi->operation_mode == DSI_VIDEO_MODE) {
I915_WRITE_BITS(MIPI_PORT_CTRL(pipe), LP_OUTPUT_HOLD,
LP_OUTPUT_HOLD);
usleep_range(1000, 1500);
if (intel_dsi->dual_link)
count = 2;
do {
I915_WRITE_BITS(MIPI_DEVICE_READY(pipe), DEVICE_READY |
ULPS_STATE_EXIT, DEVICE_READY |
ULPS_STATE_MASK);
usleep_range(2000, 2500);
I915_WRITE_BITS(MIPI_DEVICE_READY(pipe), DEVICE_READY,
DEVICE_READY | ULPS_STATE_MASK);
usleep_range(2000, 2500);
I915_WRITE_BITS(MIPI_DEVICE_READY(pipe), 0x00,
DEVICE_READY | ULPS_STATE_MASK);
usleep_range(2000, 2500);
I915_WRITE_BITS(MIPI_DEVICE_READY(pipe), DEVICE_READY,
DEVICE_READY | ULPS_STATE_MASK);
usleep_range(2000, 2500);
/* For Port C for dual link */
pipe = PIPE_B;
} while (--count > 0);
}
}
