static void
i915StencilOpSeparate(GLcontext * ctx, GLenum face, GLenum fail, GLenum zfail,
                      GLenum zpass)
{
   struct i915_context *i915 = I915_CONTEXT(ctx);
   int fop = intel_translate_stencil_op(fail);
   int dfop = intel_translate_stencil_op(zfail);
   int dpop = intel_translate_stencil_op(zpass);


   DBG("%s: fail : %s, zfail: %s, zpass : %s\n", __FUNCTION__,
       _mesa_lookup_enum_by_nr(fail),
       _mesa_lookup_enum_by_nr(zfail), _mesa_lookup_enum_by_nr(zpass));

   I915_STATECHANGE(i915, I915_UPLOAD_CTX);

   i915->state.Ctx[I915_CTXREG_LIS5] &= ~(S5_STENCIL_FAIL_MASK |
                                          S5_STENCIL_PASS_Z_FAIL_MASK |
                                          S5_STENCIL_PASS_Z_PASS_MASK);

   i915->state.Ctx[I915_CTXREG_LIS5] |= ((fop << S5_STENCIL_FAIL_SHIFT) |
                                         (dfop <<
                                          S5_STENCIL_PASS_Z_FAIL_SHIFT) |
                                         (dpop <<
                                          S5_STENCIL_PASS_Z_PASS_SHIFT));
}
/**
 * Creates the state cache entry for the given DEPTH_STENCIL_STATE state key.
 */
static drm_intel_bo *
depth_stencil_state_create_from_key(struct brw_context *brw,
				    struct brw_depth_stencil_state_key *key)
{
   struct gen6_depth_stencil_state ds;
   drm_intel_bo *bo;

   memset(&ds, 0, sizeof(ds));

   /* _NEW_STENCIL */
   if (key->stencil) {
      ds.ds0.stencil_enable = 1;
      ds.ds0.stencil_func =
	 intel_translate_compare_func(key->stencil_func[0]);
      ds.ds0.stencil_fail_op =
	 intel_translate_stencil_op(key->stencil_fail_op[0]);
      ds.ds0.stencil_pass_depth_fail_op =
	 intel_translate_stencil_op(key->stencil_pass_depth_fail_op[0]);
      ds.ds0.stencil_pass_depth_pass_op =
	 intel_translate_stencil_op(key->stencil_pass_depth_pass_op[0]);
      ds.ds1.stencil_write_mask = key->stencil_write_mask[0];
      ds.ds1.stencil_test_mask = key->stencil_test_mask[0];

      if (key->stencil_two_side) {
	 ds.ds0.bf_stencil_enable = 1;
	 ds.ds0.bf_stencil_func =
	    intel_translate_compare_func(key->stencil_func[1]);
	 ds.ds0.bf_stencil_fail_op =
	    intel_translate_stencil_op(key->stencil_fail_op[1]);
	 ds.ds0.bf_stencil_pass_depth_fail_op =
	    intel_translate_stencil_op(key->stencil_pass_depth_fail_op[1]);
	 ds.ds0.bf_stencil_pass_depth_pass_op =
	    intel_translate_stencil_op(key->stencil_pass_depth_pass_op[1]);
	 ds.ds1.bf_stencil_write_mask = key->stencil_write_mask[1];
	 ds.ds1.bf_stencil_test_mask = key->stencil_test_mask[1];
      }

      /* Not really sure about this:
       */
      if (key->stencil_write_mask[0] ||
	  (key->stencil_two_side && key->stencil_write_mask[1]))
	 ds.ds0.stencil_write_enable = 1;
   }

   /* _NEW_DEPTH */
   if (key->depth_test) {
      ds.ds2.depth_test_enable = 1;
      ds.ds2.depth_test_func = intel_translate_compare_func(key->depth_func);
      ds.ds2.depth_write_enable = key->depth_write;
   }

   bo = brw_upload_cache(&brw->cache, BRW_DEPTH_STENCIL_STATE,
			 key, sizeof(*key),
			 NULL, 0,
			 &ds, sizeof(ds));

   return bo;
}
Exemplo n.º 3
0
/**
 * Creates the state cache entry for the given CC unit key.
 */
static void upload_cc_unit(struct brw_context *brw)
{
   struct gl_context *ctx = &brw->ctx;
   struct brw_cc_unit_state *cc;

   cc = brw_state_batch(brw, AUB_TRACE_CC_STATE,
			sizeof(*cc), 64, &brw->cc.state_offset);
   memset(cc, 0, sizeof(*cc));

   /* _NEW_STENCIL | _NEW_BUFFERS */
   if (ctx->Stencil._Enabled) {
      const unsigned back = ctx->Stencil._BackFace;

      cc->cc0.stencil_enable = 1;
      cc->cc0.stencil_func =
	 intel_translate_compare_func(ctx->Stencil.Function[0]);
      cc->cc0.stencil_fail_op =
	 intel_translate_stencil_op(ctx->Stencil.FailFunc[0]);
      cc->cc0.stencil_pass_depth_fail_op =
	 intel_translate_stencil_op(ctx->Stencil.ZFailFunc[0]);
      cc->cc0.stencil_pass_depth_pass_op =
	 intel_translate_stencil_op(ctx->Stencil.ZPassFunc[0]);
      cc->cc1.stencil_ref = _mesa_get_stencil_ref(ctx, 0);
      cc->cc1.stencil_write_mask = ctx->Stencil.WriteMask[0];
      cc->cc1.stencil_test_mask = ctx->Stencil.ValueMask[0];

      if (ctx->Stencil._TestTwoSide) {
	 cc->cc0.bf_stencil_enable = 1;
	 cc->cc0.bf_stencil_func =
	    intel_translate_compare_func(ctx->Stencil.Function[back]);
	 cc->cc0.bf_stencil_fail_op =
	    intel_translate_stencil_op(ctx->Stencil.FailFunc[back]);
	 cc->cc0.bf_stencil_pass_depth_fail_op =
	    intel_translate_stencil_op(ctx->Stencil.ZFailFunc[back]);
	 cc->cc0.bf_stencil_pass_depth_pass_op =
	    intel_translate_stencil_op(ctx->Stencil.ZPassFunc[back]);
	 cc->cc1.bf_stencil_ref = _mesa_get_stencil_ref(ctx, back);
	 cc->cc2.bf_stencil_write_mask = ctx->Stencil.WriteMask[back];
	 cc->cc2.bf_stencil_test_mask = ctx->Stencil.ValueMask[back];
      }

      /* Not really sure about this:
       */
      if (ctx->Stencil.WriteMask[0] ||
	  (ctx->Stencil._TestTwoSide && ctx->Stencil.WriteMask[back]))
	 cc->cc0.stencil_write_enable = 1;
   }

   /* _NEW_COLOR */
   if (ctx->Color.ColorLogicOpEnabled && ctx->Color.LogicOp != GL_COPY) {
      cc->cc2.logicop_enable = 1;
      cc->cc5.logicop_func = intel_translate_logic_op(ctx->Color.LogicOp);
   } else if (ctx->Color.BlendEnabled) {
      GLenum eqRGB = ctx->Color.Blend[0].EquationRGB;
      GLenum eqA = ctx->Color.Blend[0].EquationA;
      GLenum srcRGB = ctx->Color.Blend[0].SrcRGB;
      GLenum dstRGB = ctx->Color.Blend[0].DstRGB;
      GLenum srcA = ctx->Color.Blend[0].SrcA;
      GLenum dstA = ctx->Color.Blend[0].DstA;

      /* If the renderbuffer is XRGB, we have to frob the blend function to
       * force the destination alpha to 1.0.  This means replacing GL_DST_ALPHA
       * with GL_ONE and GL_ONE_MINUS_DST_ALPHA with GL_ZERO.
       */
      if (ctx->DrawBuffer->Visual.alphaBits == 0) {
	 srcRGB = brw_fix_xRGB_alpha(srcRGB);
	 srcA   = brw_fix_xRGB_alpha(srcA);
	 dstRGB = brw_fix_xRGB_alpha(dstRGB);
	 dstA   = brw_fix_xRGB_alpha(dstA);
      }

      if (eqRGB == GL_MIN || eqRGB == GL_MAX) {
	 srcRGB = dstRGB = GL_ONE;
      }

      if (eqA == GL_MIN || eqA == GL_MAX) {
	 srcA = dstA = GL_ONE;
      }

      cc->cc6.dest_blend_factor = brw_translate_blend_factor(dstRGB);
      cc->cc6.src_blend_factor = brw_translate_blend_factor(srcRGB);
      cc->cc6.blend_function = brw_translate_blend_equation(eqRGB);

      cc->cc5.ia_dest_blend_factor = brw_translate_blend_factor(dstA);
      cc->cc5.ia_src_blend_factor = brw_translate_blend_factor(srcA);
      cc->cc5.ia_blend_function = brw_translate_blend_equation(eqA);

      cc->cc3.blend_enable = 1;
      cc->cc3.ia_blend_enable = (srcA != srcRGB ||
				dstA != dstRGB ||
				eqA != eqRGB);
   }

   /* _NEW_BUFFERS */
   if (ctx->Color.AlphaEnabled && ctx->DrawBuffer->_NumColorDrawBuffers <= 1) {
      cc->cc3.alpha_test = 1;
      cc->cc3.alpha_test_func =
	 intel_translate_compare_func(ctx->Color.AlphaFunc);
      cc->cc3.alpha_test_format = BRW_ALPHATEST_FORMAT_UNORM8;

      UNCLAMPED_FLOAT_TO_UBYTE(cc->cc7.alpha_ref.ub[0], ctx->Color.AlphaRef);
   }

   if (ctx->Color.DitherFlag) {
      cc->cc5.dither_enable = 1;
      cc->cc6.y_dither_offset = 0;
      cc->cc6.x_dither_offset = 0;
   }

   /* _NEW_DEPTH */
   if (ctx->Depth.Test) {
      cc->cc2.depth_test = 1;
      cc->cc2.depth_test_function =
	 intel_translate_compare_func(ctx->Depth.Func);
      cc->cc2.depth_write_enable = ctx->Depth.Mask;
   }

   if (brw->stats_wm || unlikely(INTEL_DEBUG & DEBUG_STATS))
      cc->cc5.statistics_enable = 1;

   /* CACHE_NEW_CC_VP */
   cc->cc4.cc_viewport_state_offset = (brw->batch.bo->offset +
				       brw->cc.vp_offset) >> 5; /* reloc */

   brw->state.dirty.cache |= CACHE_NEW_CC_UNIT;

   /* Emit CC viewport relocation */
   drm_intel_bo_emit_reloc(brw->batch.bo,
			   (brw->cc.state_offset +
			    offsetof(struct brw_cc_unit_state, cc4)),
			   brw->batch.bo, brw->cc.vp_offset,
			   I915_GEM_DOMAIN_INSTRUCTION, 0);
}
Exemplo n.º 4
0
/**
 * Creates the state cache entry for the given CC unit key.
 */
static dri_bo *
cc_unit_create_from_key(struct brw_context *brw, struct brw_cc_unit_key *key)
{
   struct brw_cc_unit_state cc;
   dri_bo *bo;

   memset(&cc, 0, sizeof(cc));

   /* _NEW_STENCIL */
   if (key->stencil) {
      cc.cc0.stencil_enable = 1;
      cc.cc0.stencil_func =
	 intel_translate_compare_func(key->stencil_func[0]);
      cc.cc0.stencil_fail_op =
	 intel_translate_stencil_op(key->stencil_fail_op[0]);
      cc.cc0.stencil_pass_depth_fail_op =
	 intel_translate_stencil_op(key->stencil_pass_depth_fail_op[0]);
      cc.cc0.stencil_pass_depth_pass_op =
	 intel_translate_stencil_op(key->stencil_pass_depth_pass_op[0]);
      cc.cc1.stencil_ref = key->stencil_ref[0];
      cc.cc1.stencil_write_mask = key->stencil_write_mask[0];
      cc.cc1.stencil_test_mask = key->stencil_test_mask[0];

      if (key->stencil_two_side) {
	 cc.cc0.bf_stencil_enable = 1;
	 cc.cc0.bf_stencil_func =
	    intel_translate_compare_func(key->stencil_func[1]);
	 cc.cc0.bf_stencil_fail_op =
	    intel_translate_stencil_op(key->stencil_fail_op[1]);
	 cc.cc0.bf_stencil_pass_depth_fail_op =
	    intel_translate_stencil_op(key->stencil_pass_depth_fail_op[1]);
	 cc.cc0.bf_stencil_pass_depth_pass_op =
	    intel_translate_stencil_op(key->stencil_pass_depth_pass_op[1]);
	 cc.cc1.bf_stencil_ref = key->stencil_ref[1];
	 cc.cc2.bf_stencil_write_mask = key->stencil_write_mask[1];
	 cc.cc2.bf_stencil_test_mask = key->stencil_test_mask[1];
      }

      /* Not really sure about this:
       */
      if (key->stencil_write_mask[0] ||
	  (key->stencil_two_side && key->stencil_write_mask[1]))
	 cc.cc0.stencil_write_enable = 1;
   }

   /* _NEW_COLOR */
   if (key->logic_op != GL_COPY) {
      cc.cc2.logicop_enable = 1;
      cc.cc5.logicop_func = intel_translate_logic_op(key->logic_op);
   } else if (key->color_blend) {
      GLenum eqRGB = key->blend_eq_rgb;
      GLenum eqA = key->blend_eq_a;
      GLenum srcRGB = key->blend_src_rgb;
      GLenum dstRGB = key->blend_dst_rgb;
      GLenum srcA = key->blend_src_a;
      GLenum dstA = key->blend_dst_a;

      if (eqRGB == GL_MIN || eqRGB == GL_MAX) {
	 srcRGB = dstRGB = GL_ONE;
      }

      if (eqA == GL_MIN || eqA == GL_MAX) {
	 srcA = dstA = GL_ONE;
      }

      cc.cc6.dest_blend_factor = brw_translate_blend_factor(dstRGB);
      cc.cc6.src_blend_factor = brw_translate_blend_factor(srcRGB);
      cc.cc6.blend_function = brw_translate_blend_equation(eqRGB);

      cc.cc5.ia_dest_blend_factor = brw_translate_blend_factor(dstA);
      cc.cc5.ia_src_blend_factor = brw_translate_blend_factor(srcA);
      cc.cc5.ia_blend_function = brw_translate_blend_equation(eqA);

      cc.cc3.blend_enable = 1;
      cc.cc3.ia_blend_enable = (srcA != srcRGB ||
				dstA != dstRGB ||
				eqA != eqRGB);
   }

   if (key->alpha_enabled) {
      cc.cc3.alpha_test = 1;
      cc.cc3.alpha_test_func = intel_translate_compare_func(key->alpha_func);
      cc.cc3.alpha_test_format = BRW_ALPHATEST_FORMAT_UNORM8;

      UNCLAMPED_FLOAT_TO_UBYTE(cc.cc7.alpha_ref.ub[0], key->alpha_ref);
   }

   if (key->dither) {
      cc.cc5.dither_enable = 1;
      cc.cc6.y_dither_offset = 0;
      cc.cc6.x_dither_offset = 0;
   }

   /* _NEW_DEPTH */
   if (key->depth_test) {
      cc.cc2.depth_test = 1;
      cc.cc2.depth_test_function = intel_translate_compare_func(key->depth_func);
      cc.cc2.depth_write_enable = key->depth_write;
   }

   /* CACHE_NEW_CC_VP */
   cc.cc4.cc_viewport_state_offset = brw->cc.vp_bo->offset >> 5; /* reloc */

   if (INTEL_DEBUG & DEBUG_STATS)
      cc.cc5.statistics_enable = 1;

   bo = brw_upload_cache(&brw->cache, BRW_CC_UNIT,
			 key, sizeof(*key),
			 &brw->cc.vp_bo, 1,
			 &cc, sizeof(cc),
			 NULL, NULL);

   /* Emit CC viewport relocation */
   dri_bo_emit_reloc(bo,
		     I915_GEM_DOMAIN_INSTRUCTION,
		     0,
		     0,
		     offsetof(struct brw_cc_unit_state, cc4),
		     brw->cc.vp_bo);

   return bo;
}
Exemplo n.º 5
0
void
i915_update_stencil(struct gl_context * ctx)
{
   struct i915_context *i915 = I915_CONTEXT(ctx);
   GLuint front_ref, front_writemask, front_mask;
   GLenum front_func, front_fail, front_pass_z_fail, front_pass_z_pass;
   GLuint back_ref, back_writemask, back_mask;
   GLenum back_func, back_fail, back_pass_z_fail, back_pass_z_pass;
   GLuint dirty = 0;

   /* The 915 considers CW to be "front" for two-sided stencil, so choose
    * appropriately.
    */
   /* _NEW_POLYGON | _NEW_STENCIL */
   if (ctx->Polygon.FrontFace == GL_CW) {
      front_ref = ctx->Stencil.Ref[0];
      front_mask = ctx->Stencil.ValueMask[0];
      front_writemask = ctx->Stencil.WriteMask[0];
      front_func = ctx->Stencil.Function[0];
      front_fail = ctx->Stencil.FailFunc[0];
      front_pass_z_fail = ctx->Stencil.ZFailFunc[0];
      front_pass_z_pass = ctx->Stencil.ZPassFunc[0];
      back_ref = ctx->Stencil.Ref[ctx->Stencil._BackFace];
      back_mask = ctx->Stencil.ValueMask[ctx->Stencil._BackFace];
      back_writemask = ctx->Stencil.WriteMask[ctx->Stencil._BackFace];
      back_func = ctx->Stencil.Function[ctx->Stencil._BackFace];
      back_fail = ctx->Stencil.FailFunc[ctx->Stencil._BackFace];
      back_pass_z_fail = ctx->Stencil.ZFailFunc[ctx->Stencil._BackFace];
      back_pass_z_pass = ctx->Stencil.ZPassFunc[ctx->Stencil._BackFace];
   } else {
      front_ref = ctx->Stencil.Ref[ctx->Stencil._BackFace];
      front_mask = ctx->Stencil.ValueMask[ctx->Stencil._BackFace];
      front_writemask = ctx->Stencil.WriteMask[ctx->Stencil._BackFace];
      front_func = ctx->Stencil.Function[ctx->Stencil._BackFace];
      front_fail = ctx->Stencil.FailFunc[ctx->Stencil._BackFace];
      front_pass_z_fail = ctx->Stencil.ZFailFunc[ctx->Stencil._BackFace];
      front_pass_z_pass = ctx->Stencil.ZPassFunc[ctx->Stencil._BackFace];
      back_ref = ctx->Stencil.Ref[0];
      back_mask = ctx->Stencil.ValueMask[0];
      back_writemask = ctx->Stencil.WriteMask[0];
      back_func = ctx->Stencil.Function[0];
      back_fail = ctx->Stencil.FailFunc[0];
      back_pass_z_fail = ctx->Stencil.ZFailFunc[0];
      back_pass_z_pass = ctx->Stencil.ZPassFunc[0];
   }
#define set_ctx_bits(reg, mask, set) do{ \
   GLuint dw = i915->state.Ctx[reg]; \
   dw &= ~(mask); \
   dw |= (set); \
   dirty |= dw != i915->state.Ctx[reg]; \
   i915->state.Ctx[reg] = dw; \
} while(0)

   /* Set front state. */
   set_ctx_bits(I915_CTXREG_STATE4,
                MODE4_ENABLE_STENCIL_TEST_MASK |
                MODE4_ENABLE_STENCIL_WRITE_MASK,
                ENABLE_STENCIL_TEST_MASK |
                ENABLE_STENCIL_WRITE_MASK |
                STENCIL_TEST_MASK(front_mask) |
                STENCIL_WRITE_MASK(front_writemask));

   set_ctx_bits(I915_CTXREG_LIS5,
                S5_STENCIL_REF_MASK |
                S5_STENCIL_TEST_FUNC_MASK |
                S5_STENCIL_FAIL_MASK |
                S5_STENCIL_PASS_Z_FAIL_MASK |
                S5_STENCIL_PASS_Z_PASS_MASK,
                (front_ref << S5_STENCIL_REF_SHIFT) |
                (intel_translate_compare_func(front_func) << S5_STENCIL_TEST_FUNC_SHIFT) |
                (intel_translate_stencil_op(front_fail) << S5_STENCIL_FAIL_SHIFT) |
                (intel_translate_stencil_op(front_pass_z_fail) <<
                 S5_STENCIL_PASS_Z_FAIL_SHIFT) |
                (intel_translate_stencil_op(front_pass_z_pass) <<
                 S5_STENCIL_PASS_Z_PASS_SHIFT));

   /* Set back state if different from front. */
   if (ctx->Stencil._TestTwoSide) {
      set_ctx_bits(I915_CTXREG_BF_STENCIL_OPS,
                   BFO_STENCIL_REF_MASK |
                   BFO_STENCIL_TEST_MASK |
                   BFO_STENCIL_FAIL_MASK |
                   BFO_STENCIL_PASS_Z_FAIL_MASK |
                   BFO_STENCIL_PASS_Z_PASS_MASK,
                   BFO_STENCIL_TWO_SIDE |
                   (back_ref << BFO_STENCIL_REF_SHIFT) |
                   (intel_translate_compare_func(back_func) << BFO_STENCIL_TEST_SHIFT) |
                   (intel_translate_stencil_op(back_fail) << BFO_STENCIL_FAIL_SHIFT) |
                   (intel_translate_stencil_op(back_pass_z_fail) <<
                    BFO_STENCIL_PASS_Z_FAIL_SHIFT) |
                   (intel_translate_stencil_op(back_pass_z_pass) <<
                    BFO_STENCIL_PASS_Z_PASS_SHIFT));

      set_ctx_bits(I915_CTXREG_BF_STENCIL_MASKS,
                   BFM_STENCIL_TEST_MASK_MASK |
                   BFM_STENCIL_WRITE_MASK_MASK,
                   BFM_STENCIL_TEST_MASK(back_mask) |
                   BFM_STENCIL_WRITE_MASK(back_writemask));
   } else {
      set_ctx_bits(I915_CTXREG_BF_STENCIL_OPS,
                   BFO_STENCIL_TWO_SIDE, 0);
   }

#undef set_ctx_bits

   if (dirty)
      I915_STATECHANGE(i915, I915_UPLOAD_CTX);
}
Exemplo n.º 6
0
static void
gen6_upload_depth_stencil_state(struct brw_context *brw)
{
   struct gl_context *ctx = &brw->ctx;
   struct gen6_depth_stencil_state *ds;
   struct intel_renderbuffer *depth_irb;

   /* _NEW_BUFFERS */
   depth_irb = intel_get_renderbuffer(ctx->DrawBuffer, BUFFER_DEPTH);

   ds = brw_state_batch(brw, AUB_TRACE_DEPTH_STENCIL_STATE,
			sizeof(*ds), 64,
			&brw->cc.depth_stencil_state_offset);
   memset(ds, 0, sizeof(*ds));

   /* _NEW_STENCIL | _NEW_BUFFERS */
   if (ctx->Stencil._Enabled) {
      int back = ctx->Stencil._BackFace;

      ds->ds0.stencil_enable = 1;
      ds->ds0.stencil_func =
	 intel_translate_compare_func(ctx->Stencil.Function[0]);
      ds->ds0.stencil_fail_op =
	 intel_translate_stencil_op(ctx->Stencil.FailFunc[0]);
      ds->ds0.stencil_pass_depth_fail_op =
	 intel_translate_stencil_op(ctx->Stencil.ZFailFunc[0]);
      ds->ds0.stencil_pass_depth_pass_op =
	 intel_translate_stencil_op(ctx->Stencil.ZPassFunc[0]);
      ds->ds1.stencil_write_mask = ctx->Stencil.WriteMask[0];
      ds->ds1.stencil_test_mask = ctx->Stencil.ValueMask[0];

      if (ctx->Stencil._TestTwoSide) {
	 ds->ds0.bf_stencil_enable = 1;
	 ds->ds0.bf_stencil_func =
	    intel_translate_compare_func(ctx->Stencil.Function[back]);
	 ds->ds0.bf_stencil_fail_op =
	    intel_translate_stencil_op(ctx->Stencil.FailFunc[back]);
	 ds->ds0.bf_stencil_pass_depth_fail_op =
	    intel_translate_stencil_op(ctx->Stencil.ZFailFunc[back]);
	 ds->ds0.bf_stencil_pass_depth_pass_op =
	    intel_translate_stencil_op(ctx->Stencil.ZPassFunc[back]);
	 ds->ds1.bf_stencil_write_mask = ctx->Stencil.WriteMask[back];
	 ds->ds1.bf_stencil_test_mask = ctx->Stencil.ValueMask[back];
      }

      ds->ds0.stencil_write_enable = ctx->Stencil._WriteEnabled;
   }

   /* _NEW_DEPTH */
   if (ctx->Depth.Test && depth_irb) {
      ds->ds2.depth_test_enable = ctx->Depth.Test;
      ds->ds2.depth_test_func = intel_translate_compare_func(ctx->Depth.Func);
      ds->ds2.depth_write_enable = ctx->Depth.Mask;
   }

   /* Point the GPU at the new indirect state. */
   if (brw->gen == 6) {
      BEGIN_BATCH(4);
      OUT_BATCH(_3DSTATE_CC_STATE_POINTERS << 16 | (4 - 2));
      OUT_BATCH(0);
      OUT_BATCH(brw->cc.depth_stencil_state_offset | 1);
      OUT_BATCH(0);
      ADVANCE_BATCH();
   } else {
      BEGIN_BATCH(2);
      OUT_BATCH(_3DSTATE_DEPTH_STENCIL_STATE_POINTERS << 16 | (2 - 2));
      OUT_BATCH(brw->cc.depth_stencil_state_offset | 1);
      ADVANCE_BATCH();
   }
}
Exemplo n.º 7
0
static void
gen6_upload_depth_stencil_state(struct brw_context *brw)
{
   struct gl_context *ctx = &brw->intel.ctx;
   struct gen6_depth_stencil_state *ds;
   struct intel_renderbuffer *depth_irb;

   /* _NEW_BUFFERS */
   depth_irb = intel_get_renderbuffer(ctx->DrawBuffer, BUFFER_DEPTH);

   ds = brw_state_batch(brw, AUB_TRACE_DEPTH_STENCIL_STATE,
			sizeof(*ds), 64,
			&brw->cc.depth_stencil_state_offset);
   memset(ds, 0, sizeof(*ds));

   /* _NEW_STENCIL */
   if (ctx->Stencil._Enabled) {
      int back = ctx->Stencil._BackFace;

      ds->ds0.stencil_enable = 1;
      ds->ds0.stencil_func =
	 intel_translate_compare_func(ctx->Stencil.Function[0]);
      ds->ds0.stencil_fail_op =
	 intel_translate_stencil_op(ctx->Stencil.FailFunc[0]);
      ds->ds0.stencil_pass_depth_fail_op =
	 intel_translate_stencil_op(ctx->Stencil.ZFailFunc[0]);
      ds->ds0.stencil_pass_depth_pass_op =
	 intel_translate_stencil_op(ctx->Stencil.ZPassFunc[0]);
      ds->ds1.stencil_write_mask = ctx->Stencil.WriteMask[0];
      ds->ds1.stencil_test_mask = ctx->Stencil.ValueMask[0];

      if (ctx->Stencil._TestTwoSide) {
	 ds->ds0.bf_stencil_enable = 1;
	 ds->ds0.bf_stencil_func =
	    intel_translate_compare_func(ctx->Stencil.Function[back]);
	 ds->ds0.bf_stencil_fail_op =
	    intel_translate_stencil_op(ctx->Stencil.FailFunc[back]);
	 ds->ds0.bf_stencil_pass_depth_fail_op =
	    intel_translate_stencil_op(ctx->Stencil.ZFailFunc[back]);
	 ds->ds0.bf_stencil_pass_depth_pass_op =
	    intel_translate_stencil_op(ctx->Stencil.ZPassFunc[back]);
	 ds->ds1.bf_stencil_write_mask = ctx->Stencil.WriteMask[back];
	 ds->ds1.bf_stencil_test_mask = ctx->Stencil.ValueMask[back];
      }

      /* Not really sure about this:
       */
      if (ctx->Stencil.WriteMask[0] ||
	  (ctx->Stencil._TestTwoSide && ctx->Stencil.WriteMask[back]))
	 ds->ds0.stencil_write_enable = 1;
   }

   /* _NEW_DEPTH */
   if (ctx->Depth.Test && depth_irb) {
      ds->ds2.depth_test_enable = ctx->Depth.Test;
      ds->ds2.depth_test_func = intel_translate_compare_func(ctx->Depth.Func);
      ds->ds2.depth_write_enable = ctx->Depth.Mask;
   }

   brw->state.dirty.cache |= CACHE_NEW_DEPTH_STENCIL_STATE;
}